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authorKevin Scott <kevin.c.scott@intel.com>2014-06-04 20:41:33 +0000
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2014-06-30 23:45:46 -0700
commit0b9754e9324b268d5ca14a0900ede7f350be489a (patch)
treefd9e9378b068a736b983bef34ee36401fce40ee9
parent838d41d92a90cc0395893006e20991aa9fd0ac85 (diff)
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i40e: Correct mask assignment value
Make mask value of all 1s. Value of -1 can't be used for u32 type. Change-ID: I49d58b77639939fe7447a229dbf1f4a1bf7419ce Signed-off-by: Kevin Scott <kevin.c.scott@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c b/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
index 5a603a5e9aa8..0d74b46d177f 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
@@ -858,7 +858,7 @@ static void i40e_write_dword(u8 *hmc_bits,
if (ce_info->width < 32)
mask = ((u32)1 << ce_info->width) - 1;
else
- mask = -1;
+ mask = 0xFFFFFFFF;
/* don't swizzle the bits until after the mask because the mask bits
* will be in a different bit position on big endian machines
@@ -910,7 +910,7 @@ static void i40e_write_qword(u8 *hmc_bits,
if (ce_info->width < 64)
mask = ((u64)1 << ce_info->width) - 1;
else
- mask = -1;
+ mask = 0xFFFFFFFFFFFFFFFF;
/* don't swizzle the bits until after the mask because the mask bits
* will be in a different bit position on big endian machines