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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2010-08-07 11:01:29 +0100 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2010-08-09 11:24:34 -0700 |
| commit | 20a0945951705246278f43641bb13611c030e112 (patch) | |
| tree | 89c998fd588361566b3a6ff60c1111dab165c7f9 | |
| parent | 1d8e1c75ffa84400758aef9cc59298920b8801f9 (diff) | |
| download | linux-20a0945951705246278f43641bb13611c030e112.tar.gz linux-20a0945951705246278f43641bb13611c030e112.tar.bz2 linux-20a0945951705246278f43641bb13611c030e112.zip | |
drm/i915: Write to display base last.
Writing to the DSPBASE register triggers the double-buffered update to
all the control registers, so always write it last in the update
sequence.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 25e3866f9159..874ae30d5e4a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1585,15 +1585,13 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, Start, Offset, x, y, crtc->fb->pitch); I915_WRITE(dspstride, crtc->fb->pitch); if (IS_I965G(dev)) { - I915_WRITE(dspbase, Offset); - I915_READ(dspbase); I915_WRITE(dspsurf, Start); - I915_READ(dspsurf); I915_WRITE(dsptileoff, (y << 16) | x); + I915_WRITE(dspbase, Offset); } else { I915_WRITE(dspbase, Start + Offset); - I915_READ(dspbase); } + POSTING_READ(dspbase); if ((IS_I965G(dev) || plane == 0)) intel_update_fbc(crtc, &crtc->mode); |