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authorPaul Mundt <lethal@linux-sh.org>2007-11-28 15:56:27 +0900
committerPaul Mundt <lethal@linux-sh.org>2008-01-28 13:18:58 +0900
commit3ee7702903c346fc814bd7540ba37eebef75054d (patch)
treea8862c569085da7e019d7830ba2b54e0b5aa73a7
parent66d485b45a5493f6a2ca067c6f472e7b2ca342c2 (diff)
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sh: CCR1->CCR renaming for SH-2 parts.
Avoid namespace collision with a CCR1 definition. The general SH code always expects CCR anyways, so there's no point in keeping the CCR1 naming around. Fixes up synclink collisions: drivers/char/pcmcia/synclink_cs.c:283:1: warning: "CCR1" redefined In file included from include/asm/cache.h:13, from include/asm/processor_32.h:15, from include/asm/processor.h:60, from include/linux/prefetch.h:14, from include/linux/list.h:8, from include/linux/module.h:9, from drivers/char/pcmcia/synclink_cs.c:38: include/asm/cpu/cache.h:21:1: warning: this is the location of the previous definition Reported-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--include/asm-sh/cpu-sh2/cache.h3
-rw-r--r--include/asm-sh/cpu-sh2a/cache.h6
2 files changed, 2 insertions, 7 deletions
diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h
index 66388ce16c30..4e0b16500686 100644
--- a/include/asm-sh/cpu-sh2/cache.h
+++ b/include/asm-sh/cpu-sh2/cache.h
@@ -18,8 +18,7 @@
#define SH_CACHE_ASSOC 8
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
-#define CCR1 0xffffffec
-#define CCR CCR1
+#define CCR 0xffffffec
#define CCR_CACHE_CE 0x01 /* Cache enable */
#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
diff --git a/include/asm-sh/cpu-sh2a/cache.h b/include/asm-sh/cpu-sh2a/cache.h
index d88774169b58..afe228b3f493 100644
--- a/include/asm-sh/cpu-sh2a/cache.h
+++ b/include/asm-sh/cpu-sh2a/cache.h
@@ -17,12 +17,9 @@
#define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8
-#define CCR1 0xfffc1000
+#define CCR 0xfffc1000 /* CCR1 */
#define CCR2 0xfffc1004
-/* CCR1 behaves more like the traditional CCR */
-#define CCR CCR1
-
/*
* Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
* listed here are reserved.
@@ -41,4 +38,3 @@
#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI)
#endif /* __ASM_CPU_SH2A_CACHE_H */
-