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| author | Jay Agarwal <jagarwal@nvidia.com> | 2013-06-12 12:43:43 +0530 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2013-06-16 11:25:45 -0700 |
| commit | ff49fad1d9bf2c49f52817b04cde8e4412434637 (patch) | |
| tree | a5ff971c0769b8443f6cc1b86bd146c758d4cd0a | |
| parent | 346f372f7b72a05bfa9b4e6d1b1e5de289a18d8a (diff) | |
| download | linux-ff49fad1d9bf2c49f52817b04cde8e4412434637.tar.gz linux-ff49fad1d9bf2c49f52817b04cde8e4412434637.tar.bz2 linux-ff49fad1d9bf2c49f52817b04cde8e4412434637.zip | |
ARM: tegra30: clocks: Fix pciex clock registration
Registering pciex as peripheral clock instead of fixed clock
as tegra_perih_reset_assert(deassert) api of this clock api
gives warning and ultimately does not succeed to assert(deassert)
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra30.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c index c6921f538e28..ba99e3844106 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1598,6 +1598,12 @@ static void __init tegra30_periph_clk_init(void) clk_register_clkdev(clk, "afi", "tegra-pcie"); clks[afi] = clk; + /* pciex */ + clk = tegra_clk_register_periph_gate("pciex", "pll_e", 0, clk_base, 0, + 74, &periph_u_regs, periph_clk_enb_refcnt); + clk_register_clkdev(clk, "pciex", "tegra-pcie"); + clks[pciex] = clk; + /* kfuse */ clk = tegra_clk_register_periph_gate("kfuse", "clk_m", TEGRA_PERIPH_ON_APB, @@ -1716,11 +1722,6 @@ static void __init tegra30_fixed_clk_init(void) 1, 0, &cml_lock); clk_register_clkdev(clk, "cml1", NULL); clks[cml1] = clk; - - /* pciex */ - clk = clk_register_fixed_rate(NULL, "pciex", "pll_e", 0, 100000000); - clk_register_clkdev(clk, "pciex", NULL); - clks[pciex] = clk; } static void __init tegra30_osc_clk_init(void) |