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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-05-18 12:48:46 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-05-18 12:48:46 -0700 |
| commit | f7df9be067160eef52f04bd2f137a20683fb1c12 (patch) | |
| tree | ab1e6b8325946f937d7029c34601e5440d0cc842 | |
| parent | 9f8f2022786dae0bd48ba35006d6c3ed1ffb469d (diff) | |
| parent | ec42083b98bc7a85c736a8ae1b4c045901ed259e (diff) | |
| download | linux-f7df9be067160eef52f04bd2f137a20683fb1c12.tar.gz linux-f7df9be067160eef52f04bd2f137a20683fb1c12.tar.bz2 linux-f7df9be067160eef52f04bd2f137a20683fb1c12.zip | |
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are all the updates to device tree files for 32-bit platforms,
which as usual makes up the bulk of the ARM SoC changes: 462 non-merge
changesets, 450 files changed, 23340 insertions, 5216 deletions.
The three platforms that are added with the "soc" branch are here as
well, and we add some related machine files:
- For Aspeed AST2400/AST2500, we get the evaluation platform and the
Tyan Palmetto POWER8 mainboard that uses the AST2400 BMC
- For Oxnas 810SE, the Western Digital "My Book World Edition" is
added as the only platform at the moment.
- For ARM MPS2, the AN385 (Cortex-M3) and AN399 (Cortex-M7) are
supported
On the ARM Realview development platform, we now support all machines
with device tree, previously only the board files were supported,
which in turn will likely be removed soon.
Qualcomm IPQ4019 is the second generation ARM based "Internet
Processor", following the IPQ806x that is used in many high-end WiFi
routers. This one integrates two ath10k wifi radios that were
previously on separate chips.
Other boards that got added for existing chips are:
Ti OMAP family:
- Amazon Kindle Fire, first generation, tablet and ebook reader
- OnRISC Baltos iR 2110 and 3220 embedded industrial PCs
- TI AM5728 IDK, TI AM3359 ICE-V2, and TI DRA722 Rev C EVM
development systems
Samsung EXYNOS platform:
- Samsung ARTIK5 evaluation board, see
https://www.artik.io/modules/overview/artik-5/
NXP i.MX platforms:
- Ka-Ro electronics TX6S-8034, TX6S-8035, TX6U-8033, TX6U-81xx,
TX6Q-1036, TX6Q-1110/-1130, TXUL-0010 and TXUL-0011 industrial
SoM modules
- Embest MarS Board i.MX6Dual DIY platform
- Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX and SoloX
Nitrogen6sx embedded boards
- Technexion Pico i.MX6UL compute module
- ZII VF610 Development Board
Marvell embedded (mvebu, orion, kirkwood) platforms:
- Linksys Viper (E4200v2 / EA4500) WiFi router
- Buffalo Kurobox Pro NAS
Qualcomm Snapdragon:
- Arrow DragonBoard 600c (96boards) with APQ8064 Snapdragon 600
Rockchips platform:
- mqmaker MiQi single-board computer
Altera SoCFPGA:
- samtec VIN|ING 1000 vehicle communication interface
Allwinner Sunxi platforms:
- Dserve DSRV9703C tablet
- Difrnce DIT4350 tablet
- Colorfly E708 Q1 tablet
- Polaroid MID2809PXE04 tablet
- Olimex A20 OLinuXino LIME2 single board computer
- Xunlong Orange Pi 2, Orange Pi One, and Orange Pi PC single board
computers
Across many platforms, bug fixes went in to address warnings that dtc
now emits with 'make dtbs W=1'. Further changes for device enablement
went into Ti OMAP, bcm283x (Raspberry Pi), bcm47xx (wifi router), Ti
Davinci, Samsung EXYNOS, Marvell mvebu/kirkwood/orion, NXP i.MX/Vybrid
NXP LPC18xx, NXP LPC32xx, Renesas shmobile/r-mobile/r-car, Rockchips
rk3xxx, ST Ux500, ST STi, Atmel AT91/SAMA5, Altera SoCFPGA, Allwinner
Sunxi, Sigma Designs Tango, NVIDIA Tegra, Socionext Uniphier and ARM
Versatile Express"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (458 commits)
ARM: dts: tango4: Import watchdog node
ARM: dts: tango4: Update cpus node for cpufreq
ARM: dts: tango4: Update DT to match clk driver
ARM: dts: tango4: Initial thermal support
arm/dst: Add Aspeed ast2500 device tree
arm/dts: Add Aspeed ast2400 device tree
ARM: sun7i: dt: Add pll3 and pll7 clocks
ARM: dts: sunxi: Add a olinuxino-lime2-emmc
ARM: dts: at91: sama5d4: add trng node
ARM: dts: at91: sama5d3: add trng node
ARM: dts: at91: sama5d2: add trng node
ARM: dts: at91: at91sam9g45 family: reduce the trng register map size
ARM: sun4i: dt: Add pll3 and pll7 clocks
ARM: sun5i: chip: Enable the TV Encoder
ARM: sun5i: r8: Add display blocks to the DTSI
ARM: sun5i: a13: Add display and TCON clocks
ARM: dts: ux500: configure the accelerometers open drain
ARM: mx5: dts: Enable USB OTG on M53EVK
ARM: dts: imx6ul-14x14-evk: Add audio support
ARM: dts: imx6qdl: Remove unneeded unit-addresses
...
448 files changed, 23088 insertions, 5151 deletions
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards index 0226bc2cc1f6..ab318a56fca2 100644 --- a/Documentation/devicetree/bindings/arm/arm-boards +++ b/Documentation/devicetree/bindings/arm/arm-boards @@ -93,6 +93,14 @@ Required nodes: a core-module with regs and the compatible strings "arm,core-module-versatile", "syscon" +Optional nodes: + +- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface + board mounted, this has a separate system controller that is + defined in this node. + Required properties: + compatible = "arm,versatile-ib2-syscon", "syscon" + ARM RealView Boards ------------------- The RealView boards cover tailored evaluation boards that are used to explore diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.txt b/Documentation/devicetree/bindings/arm/atmel-at91.txt index 0b1fcbfe2299..1d8004633479 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.txt +++ b/Documentation/devicetree/bindings/arm/atmel-at91.txt @@ -159,7 +159,7 @@ elsewhere. required properties: - compatible: Should be "atmel,<chip>-sfr", "syscon". - <chip> can be "sama5d3" or "sama5d4". + <chip> can be "sama5d3", "sama5d4" or "sama5d2". - reg: Should contain registers location and length sfr@f0038000 { diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index 21e71a5e866e..94b57f247615 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -133,6 +133,9 @@ Boards: - AM335X Bone : Low cost community board compatible = "ti,am335x-bone", "ti,am33xx", "ti,omap3" +- AM3359 ICEv2 : Low cost Industrial Communication Engine EVM. + compatible = "ti,am3359-icev2", "ti,am33xx", "ti,omap3" + - AM335X OrionLXm : Substation Automation Platform compatible = "novatech,am335x-lxm", "ti,am33xx" @@ -169,6 +172,9 @@ Boards: - AM57XX SBC-AM57x compatible = "compulab,sbc-am57x", "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" +- AM5728 IDK + compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7" + - DRA742 EVM: Software Development Board for DRA742 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7" diff --git a/Documentation/devicetree/bindings/arm/oxnas.txt b/Documentation/devicetree/bindings/arm/oxnas.txt new file mode 100644 index 000000000000..b9e49711ba05 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/oxnas.txt @@ -0,0 +1,9 @@ +Oxford Semiconductor OXNAS SoCs Family device tree bindings +------------------------------------------- + +Boards with the OX810SE SoC shall have the following properties: + Required root node property: + compatible: "oxsemi,ox810se" + +Board compatible values: + - "wd,mbwe" (OX810SE) diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 078c14fcdaaa..585496f203df 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -87,6 +87,10 @@ Rockchip platforms device tree bindings "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; +- mqmaker MiQi: + Required root node properties: + - compatible = "mqmaker,miqi", "rockchip,rk3288"; + - Rockchip RK3368 evb: Required root node properties: - compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt index 12129c011c8f..f5deace2b380 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt @@ -2,6 +2,8 @@ Required root node properties: - compatible = should be one or more of the following. + - "samsung,artik5" - for Exynos3250-based Samsung ARTIK5 module. + - "samsung,artik5-eval" - for Exynos3250-based Samsung ARTIK5 eval board. - "samsung,monk" - for Exynos3250-based Samsung Simband board. - "samsung,rinato" - for Exynos3250-based Samsung Gear2 board. - "samsung,smdkv310" - for Exynos4210-based Samsung SMDKV310 eval board. diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt index dc8d3aac1aa9..175f0e44ed85 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt @@ -58,6 +58,15 @@ The third cell specifies the transfer priority as below. 1 Medium 2 Low +Optional properties: + +- gpr : The phandle to the General Purpose Register (GPR) node. +- fsl,sdma-event-remap : Register bits of sdma event remap, the format is + <reg shift val>. + reg is the GPR register offset. + shift is the bit position inside the GPR register. + val is the value of the bit (0 or 1). + Examples: sdma@83fb0000 { @@ -83,3 +92,21 @@ ssi2: ssi@70014000 { dma-names = "rx", "tx"; fsl,fifo-depth = <15>; }; + +Using the fsl,sdma-event-remap property: + +If we want to use SDMA on the SAI1 port on a MX6SX: + +&sdma { + gpr = <&gpr>; + /* SDMA events remap for SAI1_RX and SAI1_TX */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; + +The fsl,sdma-event-remap property in this case has two values: +- <0 15 1> means that the offset is 0, so GPR0 is the register of the +SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX. +Setting bit 15 to 1 selects SAI1_RX. +- <0 16 1> means that the offset is 0, so GPR0 is the register of the +SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX. +Setting bit 16 to 1 selects SAI1_TX. diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt index c9cf605bb995..2a1d16bdf834 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt @@ -6,7 +6,7 @@ controllers are OR:ed together and fed to the CPU tile's IRQ input. Each instance can handle up to 32 interrupts. Required properties: -- compatible: "arm,versatile-fpga-irq" +- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq" - interrupt-controller: Identifies the node as an interrupt controller - #interrupt-cells: The number of cells to define the interrupts. Must be 1 as the FPGA IRQ controller has no configuration options for interrupt diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt index 2d6c8bb4d827..6428a6ba9f4a 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt @@ -71,8 +71,8 @@ Bank 1: 24: DMA8 25: DMA9 26: DMA10 -27: DMA11 -28: DMA12 +27: DMA11-14 - shared interrupt for DMA 11 to 14 +28: DMAALL - triggers on all dma interrupts (including chanel 15) 29: AUX 30: ARM 31: VPUDMA diff --git a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt index 539adca19e8f..38211f344dc8 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt @@ -1,38 +1,60 @@ -* NXP LPC32xx Main Interrupt Controller - (MIC, including SIC1 and SIC2 secondary controllers) +* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers Required properties: -- compatible: Should be "nxp,lpc3220-mic" -- interrupt-controller: Identifies the node as an interrupt controller. -- interrupt-parent: Empty for the interrupt controller itself -- #interrupt-cells: The number of cells to define the interrupts. Should be 2. - The first cell is the IRQ number - The second cell is used to specify mode: - 1 = low-to-high edge triggered - 2 = high-to-low edge triggered - 4 = active high level-sensitive - 8 = active low level-sensitive - Default for internal sources should be set to 4 (active high). -- reg: Should contain MIC registers location and length +- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". +- reg: should contain IC registers location and length. +- interrupt-controller: identifies the node as an interrupt controller. +- #interrupt-cells: the number of cells to define an interrupt, should be 2. + The first cell is the IRQ number, the second cell is used to specify + one of the supported IRQ types: + IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, + IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, + IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, + IRQ_TYPE_LEVEL_LOW = active low level-sensitive. + Reset value is IRQ_TYPE_LEVEL_LOW. + +Optional properties: +- interrupt-parent: empty for MIC interrupt controller, link to parent + MIC interrupt controller for SIC1 and SIC2 +- interrupts: empty for MIC interrupt controller, cascaded MIC + hardware interrupts for SIC1 and SIC2 Examples: - /* - * MIC - */ + + /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ mic: interrupt-controller@40008000 { compatible = "nxp,lpc3220-mic"; + reg = <0x40008000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sic1: interrupt-controller@4000c000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x4000c000 0x4000>; interrupt-controller; - interrupt-parent; #interrupt-cells = <2>; - reg = <0x40008000 0xC000>; + + interrupt-parent = <&mic>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>, + <30 IRQ_TYPE_LEVEL_LOW>; }; - /* - * ADC - */ + sic2: interrupt-controller@40010000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x40010000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>, + <31 IRQ_TYPE_LEVEL_LOW>; + }; + + /* ADC */ adc@40048000 { compatible = "nxp,lpc3220-adc"; reg = <0x40048000 0x1000>; - interrupt-parent = <&mic>; - interrupts = <39 4>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/Documentation/devicetree/bindings/phy/phy-lpc18xx-usb-otg.txt b/Documentation/devicetree/bindings/phy/phy-lpc18xx-usb-otg.txt index bd61b467e30a..3bb821cd6a7f 100644 --- a/Documentation/devicetree/bindings/phy/phy-lpc18xx-usb-otg.txt +++ b/Documentation/devicetree/bindings/phy/phy-lpc18xx-usb-otg.txt @@ -18,7 +18,7 @@ creg: syscon@40043000 { compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd"; reg = <0x40043000 0x1000>; - usb0_otg_phy: phy@004 { + usb0_otg_phy: phy { compatible = "nxp,lpc1850-usb-otg-phy"; clocks = <&ccu1 CLK_USB0>; #phy-cells = <0>; diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt new file mode 100644 index 000000000000..b74e4d4785ab --- /dev/null +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt @@ -0,0 +1,48 @@ +DT bindings for the Renesas R-Car System Controller + +== System Controller Node == + +The R-Car System Controller provides power management for the CPU cores and +various coprocessors. + +Required properties: + - compatible: Must contain exactly one of the following: + - "renesas,r8a7779-sysc" (R-Car H1) + - "renesas,r8a7790-sysc" (R-Car H2) + - "renesas,r8a7791-sysc" (R-Car M2-W) + - "renesas,r8a7792-sysc" (R-Car V2H) + - "renesas,r8a7793-sysc" (R-Car M2-N) + - "renesas,r8a7794-sysc" (R-Car E2) + - "renesas,r8a7795-sysc" (R-Car H3) + - reg: Address start and address range for the device. + - #power-domain-cells: Must be 1. + + +Example: + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7791-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + +== PM Domain Consumers == + +Devices residing in a power area must refer to that power area, as documented +by the generic PM domain bindings in +Documentation/devicetree/bindings/power/power_domain.txt. + +Required properties: + - power-domains: A phandle and symbolic PM domain specifier, as defined in + <dt-bindings/power/r8a77*-sysc.h>. + + +Example: + + L2_CA15: cache-controller@0 { + compatible = "cache"; + power-domains = <&sysc R8A7791_PD_CA15_SCU>; + cache-unified; + cache-level = <2>; + }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt b/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt new file mode 100644 index 000000000000..bdb782918a72 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/auxadc.txt @@ -0,0 +1,21 @@ +MediaTek AUXADC +=============== + +The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found +in some Mediatek SoCs which among other things measures the temperatures +in the SoC. It can be used directly with register accesses, but it is also +used by thermal controller which reads the temperatures from the AUXADC +directly via its own bus interface. See +Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +for the Thermal Controller which holds a phandle to the AUXADC. + +Required properties: +- compatible: Must be "mediatek,mt8173-auxadc" +- reg: Address range of the AUXADC unit + +Example: + +auxadc: auxadc@11001000 { + compatible = "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; +}; diff --git a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt index ddeb5b6a53c1..107700d00df4 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt +++ b/Documentation/devicetree/bindings/soc/mediatek/pwrap.txt @@ -18,6 +18,7 @@ IP Pairing Required properties in pwrap device node. - compatible: + "mediatek,mt2701-pwrap" for MT2701/7623 SoCs "mediatek,mt8135-pwrap" for MT8135 SoCs "mediatek,mt8173-pwrap" for MT8173 SoCs - interrupts: IRQ for pwrap in SOC diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt new file mode 100644 index 000000000000..013e71a2cdc7 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt @@ -0,0 +1,35 @@ +* Rockchip General Register Files (GRF) + +The general register file will be used to do static set by software, which +is composed of many registers for system control. + +From RK3368 SoCs, the GRF is divided into two sections, +- GRF, used for general non-secure system, +- PMUGRF, used for always on system + +Required Properties: + +- compatible: GRF should be one of the followings + - "rockchip,rk3066-grf", "syscon": for rk3066 + - "rockchip,rk3188-grf", "syscon": for rk3188 + - "rockchip,rk3228-grf", "syscon": for rk3228 + - "rockchip,rk3288-grf", "syscon": for rk3288 + - "rockchip,rk3368-grf", "syscon": for rk3368 + - "rockchip,rk3399-grf", "syscon": for rk3399 +- compatible: PMUGRF should be one of the followings + - "rockchip,rk3368-pmugrf", "syscon": for rk3368 + - "rockchip,rk3399-pmugrf", "syscon": for rk3399 +- reg: physical base address of the controller and length of memory mapped + region. + +Example: GRF and PMUGRF of RK3399 SoCs + + pmugrf: syscon@ff320000 { + compatible = "rockchip,rk3399-pmugrf", "syscon"; + reg = <0x0 0xff320000 0x0 0x1000>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon"; + reg = <0x0 0xff770000 0x0 0x10000>; + }; diff --git a/Documentation/devicetree/bindings/spi/ti_qspi.txt b/Documentation/devicetree/bindings/spi/ti_qspi.txt index cc8304aa64ac..50b14f6b53a3 100644 --- a/Documentation/devicetree/bindings/spi/ti_qspi.txt +++ b/Documentation/devicetree/bindings/spi/ti_qspi.txt @@ -19,6 +19,13 @@ Optional properties: - syscon-chipselects: Handle to system control region contains QSPI chipselect register and offset of that register. +NOTE: TI QSPI controller requires different pinmux and IODelay +paramaters for Mode-0 and Mode-3 operations, which needs to be set up by +the bootloader (U-Boot). Default configuration only supports Mode-0 +operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be +specified in the slave nodes of TI QSPI controller without appropriate +modification to bootloader. + Example: For am4372: diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 86740d4a270d..d06dd3eba05c 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -16,6 +16,7 @@ al Annapurna Labs allwinner Allwinner Technology Co., Ltd. alphascale AlphaScale Integrated Circuits Systems, Inc. altr Altera Corp. +amazon Amazon.com, Inc. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amd Advanced Micro Devices (AMD), Inc. amlogic Amlogic, Inc. @@ -29,6 +30,7 @@ arm ARM Ltd. armadeus ARMadeus Systems SARL artesyn Artesyn Embedded Technologies Inc. asahi-kasei Asahi Kasei Corp. +aspeed ASPEED Technology Inc. atlas Atlas Scientific LLC atmel Atmel Corporation auo AU Optronics Corporation @@ -152,6 +154,7 @@ mitsubishi Mitsubishi Electric Corporation mosaixtech Mosaix Technologies, Inc. moxa Moxa mpl MPL AG +mqmaker mqmaker Inc. msi Micro-Star International Co. Ltd. mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) mundoreader Mundo Reader S.L. @@ -177,6 +180,7 @@ option Option NV ortustech Ortus Technology Co., Ltd. ovti OmniVision Technologies ORCL Oracle Corporation +oxsemi Oxford Semiconductor, Ltd. panasonic Panasonic Corporation parade Parade Technologies Inc. pericom Pericom Technology Inc. @@ -250,6 +254,7 @@ tplink TP-LINK Technologies Co., Ltd. tronfy Tronfy tronsmart Tronsmart truly Truly Semiconductors Limited +tyan Tyan Computer Corporation upisemi uPI Semiconductor Corp. urt United Radiant Technology Corporation usi Universal Scientific Industrial Co., Ltd. @@ -259,6 +264,7 @@ via VIA Technologies, Inc. virtio Virtual I/O Device Specification, developed by the OASIS consortium vivante Vivante Corporation voipac Voipac Technologies s.r.o. +wd Western Digital Corp. wexler Wexler winbond Winbond Electronics corp. wlf Wolfson Microelectronics diff --git a/MAINTAINERS b/MAINTAINERS index 8d61475b0a1e..eb23a20d0e5b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1271,7 +1271,7 @@ M: Santosh Shilimkar <ssantosh@kernel.org> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/mach-keystone/ -F: arch/arm/boot/dts/k2* +F: arch/arm/boot/dts/keystone-* T: git git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git ARM/TEXAS INSTRUMENT KEYSTONE CLOCK FRAMEWORK diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 95c1923ce6fa..0f89d87cb2a0 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -112,6 +112,7 @@ dtb-$(CONFIG_ARCH_DIGICOLOR) += \ dtb-$(CONFIG_ARCH_EFM32) += \ efm32gg-dk3750.dtb dtb-$(CONFIG_ARCH_EXYNOS3) += \ + exynos3250-artik5-eval.dtb \ exynos3250-monk.dtb \ exynos3250-rinato.dtb dtb-$(CONFIG_ARCH_EXYNOS4) += \ @@ -158,9 +159,9 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \ integratorap.dtb \ integratorcp.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += \ - k2hk-evm.dtb \ - k2l-evm.dtb \ - k2e-evm.dtb \ + keystone-k2hk-evm.dtb \ + keystone-k2l-evm.dtb \ + keystone-k2e-evm.dtb \ keystone-k2g-evm.dtb dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-b3.dtb \ @@ -177,6 +178,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-ds109.dtb \ kirkwood-ds110jv10.dtb \ kirkwood-ds111.dtb \ + kirkwood-ds112.dtb \ kirkwood-ds209.dtb \ kirkwood-ds210.dtb \ kirkwood-ds212.dtb \ @@ -199,6 +201,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-linkstation-lswsxl.dtb \ kirkwood-linkstation-lswvl.dtb \ kirkwood-linkstation-lswxl.dtb \ + kirkwood-linksys-viper.dtb \ kirkwood-lschlv2.dtb \ kirkwood-lsxhl.dtb \ kirkwood-mplcec4.dtb \ @@ -214,6 +217,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \ kirkwood-ns2mini.dtb \ kirkwood-nsa310.dtb \ kirkwood-nsa310a.dtb \ + kirkwood-nsa320.dtb \ kirkwood-nsa325.dtb \ kirkwood-openblocks_a6.dtb \ kirkwood-openblocks_a7.dtb \ @@ -241,7 +245,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \ lpc4350-hitex-eval.dtb \ lpc4357-ea4357-devkit.dtb dtb-$(CONFIG_ARCH_LPC32XX) += \ - ea3250.dtb phy3250.dtb + lpc3250-ea3250.dtb \ + lpc3250-phy3250.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb dtb-$(CONFIG_MACH_MESON8) += \ @@ -253,6 +258,9 @@ dtb-$(CONFIG_ARCH_MMP) += \ dtb-$(CONFIG_MACH_MESON8B) += \ meson8b-mxq.dtb \ meson8b-odroidc1.dtb +dtb-$(CONFIG_ARCH_MPS2) += \ + mps2-an385.dtb \ + mps2-an399.dtb dtb-$(CONFIG_ARCH_MOXART) += \ moxart-uc7112lx.dtb dtb-$(CONFIG_SOC_IMX1) += \ @@ -320,8 +328,12 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ imx6dl-tx6dl-comtft.dtb \ + imx6dl-tx6s-8034.dtb \ + imx6dl-tx6s-8035.dtb \ imx6dl-tx6u-801x.dtb \ + imx6dl-tx6u-8033.dtb \ imx6dl-tx6u-811x.dtb \ + imx6dl-tx6u-81xx-mb7.dtb \ imx6dl-udoo.dtb \ imx6dl-wandboard.dtb \ imx6dl-wandboard-revb1.dtb \ @@ -346,6 +358,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw552x.dtb \ imx6q-hummingboard.dtb \ imx6q-icore-rqs.dtb \ + imx6q-marsboard.dtb \ imx6q-nitrogen6x.dtb \ imx6q-nitrogen6_max.dtb \ imx6q-novena.dtb \ @@ -360,21 +373,30 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-tx6q-1010-comtft.dtb \ imx6q-tx6q-1020.dtb \ imx6q-tx6q-1020-comtft.dtb \ + imx6q-tx6q-1036.dtb \ imx6q-tx6q-1110.dtb \ + imx6q-tx6q-11x0-mb7.dtb \ imx6q-udoo.dtb \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb \ + imx6qp-nitrogen6_max.dtb \ imx6qp-sabreauto.dtb \ imx6qp-sabresd.dtb dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ imx6sl-warp.dtb dtb-$(CONFIG_SOC_IMX6SX) += \ + imx6sx-nitrogen6sx.dtb \ imx6sx-sabreauto.dtb \ imx6sx-sdb-reva.dtb \ + imx6sx-sdb-sai.dtb \ imx6sx-sdb.dtb dtb-$(CONFIG_SOC_IMX6UL) += \ - imx6ul-14x14-evk.dtb + imx6ul-14x14-evk.dtb \ + imx6ul-pico-hobbit.dtb \ + imx6ul-tx6ul-0010.dtb \ + imx6ul-tx6ul-0011.dtb \ + imx6ul-tx6ul-mainboard.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-sbc-imx7.dtb \ @@ -388,7 +410,8 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610m4-colibri.dtb \ vf610-cosmic.dtb \ vf610m4-cosmic.dtb \ - vf610-twr.dtb + vf610-twr.dtb \ + vf610-zii-dev-rev-b.dtb dtb-$(CONFIG_ARCH_MXS) += \ imx23-evk.dtb \ imx23-olinuxino.dtb \ @@ -485,6 +508,8 @@ dtb-$(CONFIG_SOC_TI81XX) += \ dm8168-evm.dtb \ dra62x-j5eco-evm.dtb dtb-$(CONFIG_SOC_AM33XX) += \ + am335x-baltos-ir2110.dtb \ + am335x-baltos-ir3220.dtb \ am335x-baltos-ir5221.dtb \ am335x-base0033.dtb \ am335x-bone.dtb \ @@ -494,6 +519,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-cm-t335.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ + am335x-icev2.dtb \ am335x-lxm.dtb \ am335x-nano.dtb \ am335x-pepper.dtb \ @@ -503,6 +529,7 @@ dtb-$(CONFIG_SOC_AM33XX) += \ am335x-wega-rdk.dtb dtb-$(CONFIG_ARCH_OMAP4) += \ omap4-duovero-parlor.dtb \ + omap4-kc1.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ omap4-panda-es.dtb \ @@ -526,9 +553,12 @@ dtb-$(CONFIG_SOC_DRA7XX) += \ am57xx-beagle-x15.dtb \ am57xx-cl-som-am57x.dtb \ am57xx-sbc-am57x.dtb \ + am572x-idk.dtb \ dra7-evm.dtb \ - dra72-evm.dtb + dra72-evm.dtb \ + dra72-evm-revc.dtb dtb-$(CONFIG_ARCH_ORION5X) += \ + orion5x-kuroboxpro.dtb \ orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ orion5x-linkstation-lsgl.dtb \ @@ -538,7 +568,10 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb +dtb-$(CONFIG_ARCH_OXNAS) += \ + wd-mbwe.dtb dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8064-arrow-db600c.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ qcom-apq8064-sony-xperia-yuga.dtb \ @@ -546,13 +579,20 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8074-dragonboard.dtb \ qcom-apq8084-ifc6540.dtb \ qcom-apq8084-mtp.dtb \ + qcom-ipq4019-ap.dk01.1-c1.dtb \ qcom-ipq8064-ap148.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ qcom-msm8974-sony-xperia-honami.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ - arm-realview-pb11mp.dtb + arm-realview-pb11mp.dtb \ + arm-realview-eb.dtb \ + arm-realview-eb-11mp.dtb \ + arm-realview-eb-11mp-revb.dtb \ + arm-realview-eb-a9mp.dtb \ + arm-realview-pba8.dtb \ + arm-realview-pbx-a9.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3036-evb.dtb \ rk3036-kylin.dtb \ @@ -565,6 +605,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-evb-rk808.dtb \ rk3288-firefly-beta.dtb \ rk3288-firefly.dtb \ + rk3288-miqi.dtb \ rk3288-popmetal.dtb \ rk3288-r89.dtb \ rk3288-rock2-square.dtb \ @@ -608,6 +649,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_de0_sockit.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ + socfpga_cyclone5_vining_fpga.dtb \ socfpga_vt.dtb dtb-$(CONFIG_ARCH_SPEAR13XX) += \ spear1310-evb.dtb \ @@ -637,6 +679,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-ba10-tvbox.dtb \ sun4i-a10-chuwi-v7-cw0825.dtb \ sun4i-a10-cubieboard.dtb \ + sun4i-a10-dserve-dsrv9703c.dtb \ sun4i-a10-gemei-g9.dtb \ sun4i-a10-hackberry.dtb \ sun4i-a10-hyundai-a7hd.dtb \ @@ -660,6 +703,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a10s-olinuxino-micro.dtb \ sun5i-a10s-r7-tv-dongle.dtb \ sun5i-a10s-wobo-i5.dtb \ + sun5i-a13-difrnce-dit4350.dtb \ sun5i-a13-empire-electronix-d709.dtb \ sun5i-a13-hsg-h702.dtb \ sun5i-a13-inet-98v-rev2.dtb \ @@ -675,6 +719,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-i7.dtb \ sun6i-a31-m9.dtb \ sun6i-a31-mele-a1000g-quad.dtb \ + sun6i-a31s-colorfly-e708-q1.dtb \ sun6i-a31s-cs908.dtb \ sun6i-a31s-primo81.dtb \ sun6i-a31s-sina31s.dtb \ @@ -707,6 +752,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-gt90h-v4.dtb \ sun8i-a23-ippo-q8h-v5.dtb \ sun8i-a23-ippo-q8h-v1.2.dtb \ + sun8i-a23-polaroid-mid2809pxe04.dtb \ sun8i-a23-q8-tablet.dtb \ sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-ga10h-v1.1.dtb \ @@ -715,6 +761,9 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a33-sinlinx-sina33.dtb \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ sun8i-a83t-cubietruck-plus.dtb \ + sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-one.dtb \ + sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-plus.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ @@ -839,6 +888,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt8127-moose.dtb \ mt8135-evbp1.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb +dtb-$(CONFIG_ARCH_ASPEED) += aspeed-bmc-opp-palmetto.dtb \ + aspeed-ast2500-evb.dtb endif dtstree := $(srctree)/$(src) diff --git a/arch/arm/boot/dts/am335x-baltos-ir2110.dts b/arch/arm/boot/dts/am335x-baltos-ir2110.dts new file mode 100644 index 000000000000..a9a97307d66c --- /dev/null +++ b/arch/arm/boot/dts/am335x-baltos-ir2110.dts @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am335x-baltos.dtsi" + +/ { + model = "OnRISC Baltos iR 2110"; +}; + +&am33xx_pinmux { + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ + AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ + AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */ + AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ + AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ + AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ + AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <7>; + phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <2>; +}; + +&phy_sel { + rmii-clock-ext = <1>; +}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir3220.dts b/arch/arm/boot/dts/am335x-baltos-ir3220.dts new file mode 100644 index 000000000000..fe002a17c04b --- /dev/null +++ b/arch/arm/boot/dts/am335x-baltos-ir3220.dts @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +/dts-v1/; + +#include "am335x-baltos.dtsi" + +/ { + model = "OnRISC Baltos iR 3220"; +}; + +&am33xx_pinmux { + tca6416_pins: pinmux_tca6416_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ + AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ + AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */ + AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */ + AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ + AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ + AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ + AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ + AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ + AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ + AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ + AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ + AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ + AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ + AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */ + + AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */ + >; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +&i2c1 { + tca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio0>; + interrupts = <20 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tca6416_pins>; + }; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&cpsw_emac0 { + phy-mode = "rmii"; + dual_emac_res_vlan = <1>; + fixed-link { + speed = <100>; + full-duplex; + }; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <7>; + phy-mode = "rgmii-txid"; + dual_emac_res_vlan = <2>; +}; + +&phy_sel { + rmii-clock-ext = <1>; +}; diff --git a/arch/arm/boot/dts/am335x-baltos-ir5221.dts b/arch/arm/boot/dts/am335x-baltos-ir5221.dts index 4e28d87e9356..d0faa7b8c5da 100644 --- a/arch/arm/boot/dts/am335x-baltos-ir5221.dts +++ b/arch/arm/boot/dts/am335x-baltos-ir5221.dts @@ -13,83 +13,19 @@ /dts-v1/; -#include "am33xx.dtsi" -#include <dt-bindings/pwm/pwm.h> -#include <dt-bindings/interrupt-controller/irq.h> +#include "am335x-baltos.dtsi" / { model = "OnRISC Baltos iR 5221"; - compatible = "vscom,onrisc", "ti,am33xx"; - - cpus { - cpu@0 { - cpu0-supply = <&vdd1_reg>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x10000000>; /* 256 MB */ - }; - - vbat: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "vbat"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-boot-on; - }; - - wl12xx_vmmc: fixedregulator@2 { - pinctrl-names = "default"; - pinctrl-0 = <&wl12xx_gpio>; - compatible = "regulator-fixed"; - regulator-name = "vwl1271"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio3 8 0>; - startup-delay-us = <70000>; - enable-active-high; - }; }; &am33xx_pinmux { - mmc2_pins: pinmux_mmc2_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ - AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ - AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ - AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ - AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ - AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ - AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */ - >; - }; - - wl12xx_gpio: pinmux_wl12xx_gpio { - pinctrl-single,pins = < - AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ - >; - }; - - tps65910_pins: pinmux_tps65910_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ - >; - }; - tca6416_pins: pinmux_tca6416_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */ >; }; - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ - AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ - >; - }; dcan1_pins: pinmux_dcan1_pins { pinctrl-single,pins = < @@ -98,19 +34,12 @@ >; }; - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - uart1_pins: pinmux_uart1_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */ AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */ - AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn, INPUT | MODE0 */ - AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn, OUTPUT | MODE0 */ + AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0) /* uart1_ctsn */ + AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn */ AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */ AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */ AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */ @@ -122,8 +51,8 @@ pinctrl-single,pins = < AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */ AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */ - AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) /* i2c0_sda.uart2_ctsn_mux0 */ - AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* i2c0_scl.uart2_rtsn_mux0 */ + AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */ + AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */ AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */ AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */ AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */ @@ -133,151 +62,6 @@ >; }; - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ - - - /* Slave 2 */ - AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ - AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ - AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ - AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ - AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ - AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - - /* Slave 2 reset value*/ - AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - nandflash_pins_s0: nandflash_pins_s0 { - pinctrl-single,pins = < - AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ - AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ - AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ - AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ - AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ - AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ - AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ - AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ - AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ - AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ - AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ - AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ - AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ - AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ - AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ - >; - }; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ - status = "okay"; - - nand@0,0 { - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - nand-bus-width = <8>; - ti,nand-ecc-opt = "bch8"; - ti,nand-xfer-type = "polled"; - - gpmc,device-nand = "true"; - gpmc,device-width = <1>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - elm_id = <&elm>; - }; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; }; &uart1 { @@ -287,8 +71,6 @@ dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -300,35 +82,11 @@ dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; - cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; - rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; status = "okay"; }; &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - - status = "okay"; - clock-frequency = <400000>; - - tps: tps@2d { - reg = <0x2d>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio1>; - interrupts = <28 GPIO_ACTIVE_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&tps65910_pins>; - }; - - at24@50 { - compatible = "at24,24c02"; - pagesize = <8>; - reg = <0x50>; - }; - tca6416: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; @@ -341,14 +99,6 @@ }; }; -&usb { - status = "okay"; -}; - -&usb_ctrl_mod { - status = "okay"; -}; - &usb0_phy { status = "okay"; }; @@ -367,108 +117,6 @@ dr_mode = "otg"; }; -&cppi41dma { - status = "okay"; -}; - -#include "tps65910.dtsi" - -&tps { - vcc1-supply = <&vbat>; - vcc2-supply = <&vbat>; - vcc3-supply = <&vbat>; - vcc4-supply = <&vbat>; - vcc5-supply = <&vbat>; - vcc6-supply = <&vbat>; - vcc7-supply = <&vbat>; - vccio-supply = <&vbat>; - - ti,en-ck32k-xtal = <1>; - - regulators { - vrtc_reg: regulator@0 { - regulator-always-on; - }; - - vio_reg: regulator@1 { - regulator-always-on; - }; - - vdd1_reg: regulator@2 { - /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ - regulator-name = "vdd_mpu"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1312500>; - regulator-boot-on; - regulator-always-on; - }; - - vdd2_reg: regulator@3 { - /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ - regulator-name = "vdd_core"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1150000>; - regulator-boot-on; - regulator-always-on; - }; - - vdd3_reg: regulator@4 { - regulator-always-on; - }; - - vdig1_reg: regulator@5 { - regulator-always-on; - }; - - vdig2_reg: regulator@6 { - regulator-always-on; - }; - - vpll_reg: regulator@7 { - regulator-always-on; - }; - - vdac_reg: regulator@8 { - regulator-always-on; - }; - - vaux1_reg: regulator@9 { - regulator-always-on; - }; - - vaux2_reg: regulator@10 { - regulator-always-on; - }; - - vaux33_reg: regulator@11 { - regulator-always-on; - }; - - vmmc_reg: regulator@12 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - }; -}; - -&mac { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - dual_emac = <1>; - - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - - status = "okay"; -}; - &cpsw_emac0 { phy-mode = "rmii"; dual_emac_res_vlan = <1>; @@ -488,42 +136,6 @@ rmii-clock-ext = <1>; }; -&mmc1 { - vmmc-supply = <&vmmc_reg>; - status = "okay"; -}; - -&mmc2 { - status = "okay"; - vmmc-supply = <&wl12xx_vmmc>; - ti,non-removable; - bus-width = <4>; - cap-power-off-card; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - - #address-cells = <1>; - #size-cells = <0>; - wlcore: wlcore@2 { - compatible = "ti,wl1835"; - reg = <2>; - interrupt-parent = <&gpio3>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - }; -}; - -&sham { - status = "okay"; -}; - -&aes { - status = "okay"; -}; - -&gpio0 { - ti,no-reset-on-init; -}; - &dcan1 { pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins>; diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi new file mode 100644 index 000000000000..c8609d8d2c55 --- /dev/null +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -0,0 +1,408 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * VScom OnRISC + * http://www.vscom.de + */ + +#include "am33xx.dtsi" +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "vscom,onrisc", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + wl12xx_vmmc: fixedregulator@2 { + pinctrl-names = "default"; + pinctrl-0 = <&wl12xx_gpio>; + compatible = "regulator-fixed"; + regulator-name = "vwl1271"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 8 0>; + startup-delay-us = <70000>; + enable-active-high; + }; +}; + +&am33xx_pinmux { + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */ + AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */ + AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */ + AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */ + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */ + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */ + AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */ + >; + }; + + wl12xx_gpio: pinmux_wl12xx_gpio { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */ + >; + }; + + tps65910_pins: pinmux_tps65910_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */ + AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */ + + + /* Slave 2 */ + AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */ + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */ + AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */ + AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */ + AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */ + AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */ + AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */ + AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */ + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */ + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */ + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */ + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + + /* Slave 2 reset value*/ + AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + nandflash_pins_s0: nandflash_pins_s0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ + AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ + AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ + AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ + AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ + AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ + AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ + AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ + AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ + AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ + AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ + AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ + >; + }; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&nandflash_pins_s0>; + ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + status = "okay"; + + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + nand-bus-width = <8>; + ti,nand-ecc-opt = "bch8"; + ti,nand-xfer-type = "polled"; + + gpmc,device-nand = "true"; + gpmc,device-width = <1>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-on-ns = <0>; + gpmc,we-off-ns = <40>; + gpmc,oe-on-ns = <0>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + elm_id = <&elm>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <28 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65910_pins>; + }; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <8>; + reg = <0x50>; + }; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&cppi41dma { + status = "okay"; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + ti,en-ck32k-xtal = <1>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1312500>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + + status = "okay"; +}; + +&mmc1 { + vmmc-supply = <&vmmc_reg>; + status = "okay"; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&wl12xx_vmmc>; + ti,non-removable; + bus-width = <4>; + cap-power-off-card; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1835"; + reg = <2>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&gpio0 { + ti,no-reset-on-init; +}; diff --git a/arch/arm/boot/dts/am335x-chiliboard.dts b/arch/arm/boot/dts/am335x-chiliboard.dts index 15d47ab28865..2a624b3c9258 100644 --- a/arch/arm/boot/dts/am335x-chiliboard.dts +++ b/arch/arm/boot/dts/am335x-chiliboard.dts @@ -35,6 +35,59 @@ }; &am33xx_pinmux { + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ + AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ + AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ + AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ + AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ + AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* mdio_data.mdio_data */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) + /* mdio_clk.mdio_clk */ + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) + AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + usb1_drvvbus: usb1_drvvbus { pinctrl-single,pins = < AM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */ @@ -61,12 +114,34 @@ }; }; +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + &ldo4_reg { regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; /* Ethernet */ +&mac { + slaves = <1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + &cpsw_emac0 { phy_id = <&davinci_mdio>, <0>; phy-mode = "rmii"; diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi index 95461a28bc98..1d647358f1c1 100644 --- a/arch/arm/boot/dts/am335x-chilisom.dtsi +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi @@ -35,59 +35,6 @@ >; }; - uart0_pins: pinmux_uart0_pins { - pinctrl-single,pins = < - AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ - AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ - >; - }; - - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 1 */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ - AM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ - AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ - AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ - AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ - AM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii_ref_clk */ - >; - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 1 reset value */ - AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* mdio_data.mdio_data */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) - /* mdio_clk.mdio_clk */ - AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - /* MDIO reset value */ - AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) - AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) - >; - }; - nandflash_pins: nandflash_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ @@ -109,13 +56,6 @@ }; }; -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; - - status = "okay"; -}; - &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -182,20 +122,8 @@ }; }; -/* Ethernet MAC */ -&mac { - slaves = <1>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; - status = "okay"; -}; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; - status = "okay"; +&rtc { + system-power-controller; }; /* NAND Flash */ @@ -214,6 +142,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index e835644c5054..817b1dec0683 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -411,6 +411,7 @@ status = "okay"; interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 28b916210271..516673bb023d 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -524,6 +524,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts new file mode 100644 index 000000000000..e271013e78a6 --- /dev/null +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -0,0 +1,306 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * AM335x ICE V2 board + * http://www.ti.com/tool/tmdsice3359 + */ + +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "TI AM3359 ICE-V2"; + compatible = "ti,am3359-icev2", "ti,am33xx"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vtt"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + }; + + leds@0 { + compatible = "gpio-leds"; + + led@0 { + label = "out0"; + gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@1 { + label = "out1"; + gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "out2"; + gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@3 { + label = "out3"; + gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@4 { + label = "out4"; + gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "out5"; + gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@6 { + label = "out6"; + gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@7 { + label = "out7"; + gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + /* Tricolor status LEDs */ + leds@1 { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>; + + led@0 { + label = "status0:red:cpu0"; + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + led@1 { + label = "status0:green:usr"; + gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@2 { + label = "status0:yellow:usr"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@3 { + label = "status1:red:mmc0"; + gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + + led@4 { + label = "status1:green:usr"; + gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led@5 { + label = "status1:yellow:usr"; + gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&am33xx_pinmux { + user_leds: user_leds { + pinctrl-single,pins = < + AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ + AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ + AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ + AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ + AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ + AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ + >; + }; + + mmc0_pins_default: mmc0_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */ + >; + }; + + i2c0_pins_default: i2c0_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ + AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ + >; + }; + + spi0_pins_default: spi0_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ + AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ + AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ + >; + }; + + uart3_pins_default: uart3_pins_default { + pinctrl-single,pins = < + AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ + AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_default>; + + status = "okay"; + clock-frequency = <400000>; + + tps: power-controller@2d { + reg = <0x2d>; + }; + + tpic2810: gpio@60 { + compatible = "ti,tpic2810"; + reg = <0x60>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +#include "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + vrtc_reg: regulator@0 { + regulator-always-on; + }; + + vio_reg: regulator@1 { + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-name = "vdd_mpu"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1326000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-name = "vdd_core"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1144000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd3_reg: regulator@4 { + regulator-always-on; + }; + + vdig1_reg: regulator@5 { + regulator-always-on; + }; + + vdig2_reg: regulator@6 { + regulator-always-on; + }; + + vpll_reg: regulator@7 { + regulator-always-on; + }; + + vdac_reg: regulator@8 { + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&vmmc_reg>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_default>; +}; + +&gpio0 { + /* Do not idle the GPIO used for holding the VTT regulator */ + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_default>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 6c3a9bf3638a..df63484ef9b3 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -135,6 +135,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; gpmc,device-width = <1>; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index d4b7f3bd553f..86f773165d5c 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -171,6 +171,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; gpmc,device-nand = "true"; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index 865de8500f1c..837d5b80ea1d 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -138,7 +138,7 @@ &epwmss1 { status = "okay"; - ehrpwm1: ehrpwm@48302200 { + ehrpwm1: pwm@48302200 { pinctrl-names = "default"; pinctrl-0 = <&ehrpwm1_pins>; status = "okay"; diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index afb4b3a7bab4..8d8319590cde 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck { + sys_clkin_ck: sys_clkin_ck@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; @@ -163,7 +163,7 @@ clock-frequency = <12000000>; }; - dpll_core_ck: dpll_core_ck { + dpll_core_ck: dpll_core_ck@490 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; @@ -176,7 +176,7 @@ clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck { + dpll_core_m4_ck: dpll_core_m4_ck@480 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -185,7 +185,7 @@ ti,index-starts-at-one; }; - dpll_core_m5_ck: dpll_core_m5_ck { + dpll_core_m5_ck: dpll_core_m5_ck@484 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -194,7 +194,7 @@ ti,index-starts-at-one; }; - dpll_core_m6_ck: dpll_core_m6_ck { + dpll_core_m6_ck: dpll_core_m6_ck@4d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -203,14 +203,14 @@ ti,index-starts-at-one; }; - dpll_mpu_ck: dpll_mpu_ck { + dpll_mpu_ck: dpll_mpu_ck@488 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0488>, <0x0420>, <0x042c>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck { + dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; @@ -219,14 +219,14 @@ ti,index-starts-at-one; }; - dpll_ddr_ck: dpll_ddr_ck { + dpll_ddr_ck: dpll_ddr_ck@494 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0494>, <0x0434>, <0x0440>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck { + dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>; @@ -243,14 +243,14 @@ clock-div = <2>; }; - dpll_disp_ck: dpll_disp_ck { + dpll_disp_ck: dpll_disp_ck@498 { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x0498>, <0x0448>, <0x0454>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck { + dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_disp_ck>; @@ -260,14 +260,14 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck { + dpll_per_ck: dpll_per_ck@48c { #clock-cells = <0>; compatible = "ti,am3-dpll-no-gate-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x048c>, <0x0470>, <0x049c>; }; - dpll_per_m2_ck: dpll_per_m2_ck { + dpll_per_m2_ck: dpll_per_m2_ck@4ac { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; @@ -292,7 +292,7 @@ clock-div = <4>; }; - cefuse_fck: cefuse_fck { + cefuse_fck: cefuse_fck@a20 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_clkin_ck>; @@ -316,7 +316,7 @@ clock-div = <732>; }; - clkdiv32k_ick: clkdiv32k_ick { + clkdiv32k_ick: clkdiv32k_ick@14c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ck>; @@ -332,14 +332,14 @@ clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk { + pruss_ocp_gclk: pruss_ocp_gclk@530 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; reg = <0x0530>; }; - mmu_fck: mmu_fck { + mmu_fck: mmu_fck@914 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_core_m4_ck>; @@ -347,56 +347,56 @@ reg = <0x0914>; }; - timer1_fck: timer1_fck { + timer1_fck: timer1_fck@528 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; reg = <0x0528>; }; - timer2_fck: timer2_fck { + timer2_fck: timer2_fck@508 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x0508>; }; - timer3_fck: timer3_fck { + timer3_fck: timer3_fck@50c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x050c>; }; - timer4_fck: timer4_fck { + timer4_fck: timer4_fck@510 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x0510>; }; - timer5_fck: timer5_fck { + timer5_fck: timer5_fck@518 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x0518>; }; - timer6_fck: timer6_fck { + timer6_fck: timer6_fck@51c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x051c>; }; - timer7_fck: timer7_fck { + timer7_fck: timer7_fck@504 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x0504>; }; - usbotg_fck: usbotg_fck { + usbotg_fck: usbotg_fck@47c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_ck>; @@ -412,7 +412,7 @@ clock-div = <2>; }; - ieee5000_fck: ieee5000_fck { + ieee5000_fck: ieee5000_fck@e4 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_core_m4_div2_ck>; @@ -420,7 +420,7 @@ reg = <0x00e4>; }; - wdt1_fck: wdt1_fck { + wdt1_fck: wdt1_fck@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; @@ -483,21 +483,21 @@ clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { + cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; reg = <0x0520>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { + gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; reg = <0x053c>; }; - gpio0_dbclk: gpio0_dbclk { + gpio0_dbclk: gpio0_dbclk@408 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&gpio0_dbclk_mux_ck>; @@ -505,7 +505,7 @@ reg = <0x0408>; }; - gpio1_dbclk: gpio1_dbclk { + gpio1_dbclk: gpio1_dbclk@ac { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>; @@ -513,7 +513,7 @@ reg = <0x00ac>; }; - gpio2_dbclk: gpio2_dbclk { + gpio2_dbclk: gpio2_dbclk@b0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>; @@ -521,7 +521,7 @@ reg = <0x00b0>; }; - gpio3_dbclk: gpio3_dbclk { + gpio3_dbclk: gpio3_dbclk@b4 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>; @@ -529,7 +529,7 @@ reg = <0x00b4>; }; - lcd_gclk: lcd_gclk { + lcd_gclk: lcd_gclk@534 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; @@ -545,7 +545,7 @@ clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { + gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; @@ -553,7 +553,7 @@ reg = <0x052c>; }; - gfx_fck_div_ck: gfx_fck_div_ck { + gfx_fck_div_ck: gfx_fck_div_ck@52c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&gfx_fclk_clksel_ck>; @@ -561,14 +561,14 @@ ti,max-div = <2>; }; - sysclkout_pre_ck: sysclkout_pre_ck { + sysclkout_pre_ck: sysclkout_pre_ck@700 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; reg = <0x0700>; }; - clkout2_div_ck: clkout2_div_ck { + clkout2_div_ck: clkout2_div_ck@700 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sysclkout_pre_ck>; @@ -577,7 +577,7 @@ reg = <0x0700>; }; - dbg_sysclk_ck: dbg_sysclk_ck { + dbg_sysclk_ck: dbg_sysclk_ck@414 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_clkin_ck>; @@ -585,7 +585,7 @@ reg = <0x0414>; }; - dbg_clka_ck: dbg_clka_ck { + dbg_clka_ck: dbg_clka_ck@414 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_core_m4_ck>; @@ -593,7 +593,7 @@ reg = <0x0414>; }; - stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck { + stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; @@ -601,7 +601,7 @@ reg = <0x0414>; }; - trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck { + trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; @@ -609,7 +609,7 @@ reg = <0x0414>; }; - stm_clk_div_ck: stm_clk_div_ck { + stm_clk_div_ck: stm_clk_div_ck@414 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&stm_pmd_clock_mux_ck>; @@ -619,7 +619,7 @@ ti,index-power-of-two; }; - trace_clk_div_ck: trace_clk_div_ck { + trace_clk_div_ck: trace_clk_div_ck@414 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&trace_pmd_clk_mux_ck>; @@ -629,7 +629,7 @@ ti,index-power-of-two; }; - clkout2_ck: clkout2_ck { + clkout2_ck: clkout2_ck@700 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkout2_div_ck>; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 0467846b4cc3..52be48bbd2dd 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -688,7 +688,7 @@ status = "disabled"; }; - ehrpwm0: ehrpwm@48300200 { + ehrpwm0: pwm@48300200 { compatible = "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; @@ -718,7 +718,7 @@ status = "disabled"; }; - ehrpwm1: ehrpwm@48302200 { + ehrpwm1: pwm@48302200 { compatible = "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; @@ -748,7 +748,7 @@ status = "disabled"; }; - ehrpwm2: ehrpwm@48304200 { + ehrpwm2: pwm@48304200 { compatible = "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; @@ -868,6 +868,8 @@ #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi index 18cc826e9db5..00dd1f091be5 100644 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &scm_clocks { - emac_ick: emac_ick { + emac_ick: emac_ick@32c { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>; @@ -16,7 +16,7 @@ ti,bit-shift = <1>; }; - emac_fck: emac_fck { + emac_fck: emac_fck@32c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&rmii_ck>; @@ -24,7 +24,7 @@ ti,bit-shift = <9>; }; - vpfe_ick: vpfe_ick { + vpfe_ick: vpfe_ick@32c { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>; @@ -32,7 +32,7 @@ ti,bit-shift = <2>; }; - vpfe_fck: vpfe_fck { + vpfe_fck: vpfe_fck@32c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&pclk_ck>; @@ -40,7 +40,7 @@ ti,bit-shift = <10>; }; - hsotgusb_ick_am35xx: hsotgusb_ick_am35xx { + hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&ipss_ick>; @@ -48,7 +48,7 @@ ti,bit-shift = <0>; }; - hsotgusb_fck_am35xx: hsotgusb_fck_am35xx { + hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_ck>; @@ -56,7 +56,7 @@ ti,bit-shift = <8>; }; - hecc_ck: hecc_ck { + hecc_ck: hecc_ck@32c { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; clocks = <&sys_ck>; @@ -65,7 +65,7 @@ }; }; &cm_clocks { - ipss_ick: ipss_ick { + ipss_ick: ipss_ick@a10 { #clock-cells = <0>; compatible = "ti,am35xx-interface-clock"; clocks = <&core_l3_ick>; @@ -85,7 +85,7 @@ clock-frequency = <27000000>; }; - uart4_ick_am35xx: uart4_ick_am35xx { + uart4_ick_am35xx: uart4_ick_am35xx@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -93,7 +93,7 @@ ti,bit-shift = <23>; }; - uart4_fck_am35xx: uart4_fck_am35xx { + uart4_fck_am35xx: uart4_fck_am35xx@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index ba580a9da390..12fcde4d4d2e 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -679,7 +679,7 @@ status = "disabled"; }; - ehrpwm0: ehrpwm@48300200 { + ehrpwm0: pwm@48300200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48300200 0x80>; @@ -705,7 +705,7 @@ status = "disabled"; }; - ehrpwm1: ehrpwm@48302200 { + ehrpwm1: pwm@48302200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48302200 0x80>; @@ -731,7 +731,7 @@ status = "disabled"; }; - ehrpwm2: ehrpwm@48304200 { + ehrpwm2: pwm@48304200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48304200 0x80>; @@ -749,7 +749,7 @@ ti,hwmods = "epwmss3"; status = "disabled"; - ehrpwm3: ehrpwm@48306200 { + ehrpwm3: pwm@48306200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48306200 0x80>; @@ -767,7 +767,7 @@ ti,hwmods = "epwmss4"; status = "disabled"; - ehrpwm4: ehrpwm@48308200 { + ehrpwm4: pwm@48308200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x48308200 0x80>; @@ -785,7 +785,7 @@ ti,hwmods = "epwmss5"; status = "disabled"; - ehrpwm5: ehrpwm@4830a200 { + ehrpwm5: pwm@4830a200 { compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x4830a200 0x80>; @@ -896,6 +896,8 @@ #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 8889be1ca1c3..5bcd3aa025bc 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -119,7 +119,7 @@ clock-frequency = <32768>; }; - sound0: sound@0 { + sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "AM437x-GP-EVM"; simple-audio-card,widgets = @@ -817,6 +817,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index d5dd72047a7e..3549b8c9ac49 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -107,7 +107,7 @@ default-brightness-level = <8>; }; - sound0: sound@0 { + sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "AM43-EPOS-EVM"; simple-audio-card,widgets = @@ -568,6 +568,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index a38af2bfbfcf..7630ba1d89e4 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &scm_clocks { - sys_clkin_ck: sys_clkin_ck { + sys_clkin_ck: sys_clkin_ck@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>; @@ -16,7 +16,7 @@ reg = <0x0040>; }; - crystal_freq_sel_ck: crystal_freq_sel_ck { + crystal_freq_sel_ck: crystal_freq_sel_ck@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; @@ -104,7 +104,7 @@ clock-div = <1>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk { + ehrpwm0_tbclk: ehrpwm0_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; @@ -112,7 +112,7 @@ reg = <0x0664>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk { + ehrpwm1_tbclk: ehrpwm1_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; @@ -120,7 +120,7 @@ reg = <0x0664>; }; - ehrpwm2_tbclk: ehrpwm2_tbclk { + ehrpwm2_tbclk: ehrpwm2_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; @@ -128,7 +128,7 @@ reg = <0x0664>; }; - ehrpwm3_tbclk: ehrpwm3_tbclk { + ehrpwm3_tbclk: ehrpwm3_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; @@ -136,7 +136,7 @@ reg = <0x0664>; }; - ehrpwm4_tbclk: ehrpwm4_tbclk { + ehrpwm4_tbclk: ehrpwm4_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; @@ -144,7 +144,7 @@ reg = <0x0664>; }; - ehrpwm5_tbclk: ehrpwm5_tbclk { + ehrpwm5_tbclk: ehrpwm5_tbclk@664 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4ls_gclk>; @@ -195,7 +195,7 @@ clock-frequency = <26000000>; }; - dpll_core_ck: dpll_core_ck { + dpll_core_ck: dpll_core_ck@2d20 { #clock-cells = <0>; compatible = "ti,am3-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; @@ -208,7 +208,7 @@ clocks = <&dpll_core_ck>; }; - dpll_core_m4_ck: dpll_core_m4_ck { + dpll_core_m4_ck: dpll_core_m4_ck@2d38 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -219,7 +219,7 @@ ti,invert-autoidle-bit; }; - dpll_core_m5_ck: dpll_core_m5_ck { + dpll_core_m5_ck: dpll_core_m5_ck@2d3c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -230,7 +230,7 @@ ti,invert-autoidle-bit; }; - dpll_core_m6_ck: dpll_core_m6_ck { + dpll_core_m6_ck: dpll_core_m6_ck@2d40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -241,14 +241,14 @@ ti,invert-autoidle-bit; }; - dpll_mpu_ck: dpll_mpu_ck { + dpll_mpu_ck: dpll_mpu_ck@2d60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2d60>, <0x2d64>, <0x2d6c>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck { + dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; @@ -267,14 +267,14 @@ clock-div = <2>; }; - dpll_ddr_ck: dpll_ddr_ck { + dpll_ddr_ck: dpll_ddr_ck@2da0 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2da0>, <0x2da4>, <0x2dac>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck { + dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>; @@ -285,14 +285,14 @@ ti,invert-autoidle-bit; }; - dpll_disp_ck: dpll_disp_ck { + dpll_disp_ck: dpll_disp_ck@2e20 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e20>, <0x2e24>, <0x2e2c>; }; - dpll_disp_m2_ck: dpll_disp_m2_ck { + dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_disp_ck>; @@ -304,14 +304,14 @@ ti,set-rate-parent; }; - dpll_per_ck: dpll_per_ck { + dpll_per_ck: dpll_per_ck@2de0 { #clock-cells = <0>; compatible = "ti,am3-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2de0>, <0x2de4>, <0x2dec>; }; - dpll_per_m2_ck: dpll_per_m2_ck { + dpll_per_m2_ck: dpll_per_m2_ck@2df0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; @@ -354,7 +354,7 @@ clock-div = <732>; }; - clkdiv32k_ick: clkdiv32k_ick { + clkdiv32k_ick: clkdiv32k_ick@2a38 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ck>; @@ -370,7 +370,7 @@ clock-div = <1>; }; - pruss_ocp_gclk: pruss_ocp_gclk { + pruss_ocp_gclk: pruss_ocp_gclk@4248 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk_div>, <&dpll_disp_m2_ck>; @@ -383,56 +383,56 @@ clock-frequency = <32768>; }; - timer1_fck: timer1_fck { + timer1_fck: timer1_fck@4200 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4200>; }; - timer2_fck: timer2_fck { + timer2_fck: timer2_fck@4204 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4204>; }; - timer3_fck: timer3_fck { + timer3_fck: timer3_fck@4208 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4208>; }; - timer4_fck: timer4_fck { + timer4_fck: timer4_fck@420c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x420c>; }; - timer5_fck: timer5_fck { + timer5_fck: timer5_fck@4210 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4210>; }; - timer6_fck: timer6_fck { + timer6_fck: timer6_fck@4214 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4214>; }; - timer7_fck: timer7_fck { + timer7_fck: timer7_fck@4218 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; reg = <0x4218>; }; - wdt1_fck: wdt1_fck { + wdt1_fck: wdt1_fck@422c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; @@ -487,14 +487,14 @@ clock-div = <2>; }; - cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { + cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>; reg = <0x4238>; }; - dpll_clksel_mac_clk: dpll_clksel_mac_clk { + dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5_ck>; @@ -509,14 +509,14 @@ clock-frequency = <32768>; }; - gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { + gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>; reg = <0x4240>; }; - gpio0_dbclk: gpio0_dbclk { + gpio0_dbclk: gpio0_dbclk@2b68 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&gpio0_dbclk_mux_ck>; @@ -524,7 +524,7 @@ reg = <0x2b68>; }; - gpio1_dbclk: gpio1_dbclk { + gpio1_dbclk: gpio1_dbclk@8c78 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>; @@ -532,7 +532,7 @@ reg = <0x8c78>; }; - gpio2_dbclk: gpio2_dbclk { + gpio2_dbclk: gpio2_dbclk@8c80 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>; @@ -540,7 +540,7 @@ reg = <0x8c80>; }; - gpio3_dbclk: gpio3_dbclk { + gpio3_dbclk: gpio3_dbclk@8c88 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>; @@ -548,7 +548,7 @@ reg = <0x8c88>; }; - gpio4_dbclk: gpio4_dbclk { + gpio4_dbclk: gpio4_dbclk@8c90 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>; @@ -556,7 +556,7 @@ reg = <0x8c90>; }; - gpio5_dbclk: gpio5_dbclk { + gpio5_dbclk: gpio5_dbclk@8c98 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkdiv32k_ick>; @@ -572,7 +572,7 @@ clock-div = <2>; }; - gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { + gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk_div>, <&dpll_per_m2_ck>; @@ -580,7 +580,7 @@ reg = <0x423c>; }; - gfx_fck_div_ck: gfx_fck_div_ck { + gfx_fck_div_ck: gfx_fck_div_ck@423c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&gfx_fclk_clksel_ck>; @@ -588,7 +588,7 @@ ti,max-div = <2>; }; - disp_clk: disp_clk { + disp_clk: disp_clk@4244 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; @@ -596,14 +596,14 @@ ti,set-rate-parent; }; - dpll_extdev_ck: dpll_extdev_ck { + dpll_extdev_ck: dpll_extdev_ck@2e60 { #clock-cells = <0>; compatible = "ti,am3-dpll-clock"; clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; reg = <0x2e60>, <0x2e64>, <0x2e6c>; }; - dpll_extdev_m2_ck: dpll_extdev_m2_ck { + dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_extdev_ck>; @@ -614,14 +614,14 @@ ti,invert-autoidle-bit; }; - mux_synctimer32k_ck: mux_synctimer32k_ck { + mux_synctimer32k_ck: mux_synctimer32k_ck@4230 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>; reg = <0x4230>; }; - synctimer_32kclk: synctimer_32kclk { + synctimer_32kclk: synctimer_32kclk@2a30 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&mux_synctimer32k_ck>; @@ -629,28 +629,28 @@ reg = <0x2a30>; }; - timer8_fck: timer8_fck { + timer8_fck: timer8_fck@421c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x421c>; }; - timer9_fck: timer9_fck { + timer9_fck: timer9_fck@4220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4220>; }; - timer10_fck: timer10_fck { + timer10_fck: timer10_fck@4224 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; reg = <0x4224>; }; - timer11_fck: timer11_fck { + timer11_fck: timer11_fck@4228 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>; @@ -679,7 +679,7 @@ clocks = <&dpll_ddr_ck>; }; - dpll_ddr_m4_ck: dpll_ddr_m4_ck { + dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_x2_ck>; @@ -690,7 +690,7 @@ ti,invert-autoidle-bit; }; - dpll_per_clkdcoldo: dpll_per_clkdcoldo { + dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; clocks = <&dpll_per_ck>; @@ -701,7 +701,7 @@ ti,invert-autoidle-bit; }; - dll_aging_clk_div: dll_aging_clk_div { + dll_aging_clk_div: dll_aging_clk_div@4250 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin_ck>; @@ -733,14 +733,14 @@ clock-div = <2>; }; - usbphy_32khz_clkmux: usbphy_32khz_clkmux { + usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>; reg = <0x4260>; }; - usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k { + usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&usbphy_32khz_clkmux>; @@ -748,7 +748,7 @@ reg = <0x2a40>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { + usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&usbphy_32khz_clkmux>; @@ -756,7 +756,7 @@ reg = <0x2a48>; }; - usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m { + usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_clkdcoldo>; @@ -764,11 +764,65 @@ reg = <0x8a60>; }; - usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { + usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_clkdcoldo>; ti,bit-shift = <8>; reg = <0x8a68>; }; + + clkout1_osc_div_ck: clkout1_osc_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&sys_clkin_ck>; + ti,bit-shift = <20>; + ti,max-div = <4>; + reg = <0x4100>; + }; + + clkout1_src2_mux_ck: clkout1_src2_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>, + <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>, + <&dpll_mpu_m2_ck>; + reg = <0x4100>; + }; + + clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout1_src2_mux_ck>; + ti,bit-shift = <4>; + ti,max-div = <8>; + reg = <0x4100>; + }; + + clkout1_src2_post_div_ck: clkout1_src2_post_div_ck { + #clock-cells = <0>; + compatible = "ti,divider-clock"; + clocks = <&clkout1_src2_pre_div_ck>; + ti,bit-shift = <8>; + ti,max-div = <32>; + ti,index-power-of-two; + reg = <0x4100>; + }; + + clkout1_mux_ck: clkout1_mux_ck { + #clock-cells = <0>; + compatible = "ti,mux-clock"; + clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>, + <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>; + ti,bit-shift = <16>; + reg = <0x4100>; + }; + + clkout1_ck: clkout1_ck { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&clkout1_mux_ck>; + ti,bit-shift = <23>; + reg = <0x4100>; + }; }; diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts new file mode 100644 index 000000000000..e3acb99703e1 --- /dev/null +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "dra74x.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include "am57xx-idk-common.dtsi" + +/ { + model = "TI AM5728 IDK"; + compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", + "ti,dra7"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + }; + + status-leds { + compatible = "gpio-leds"; + cpu0-led { + label = "status0:red:cpu0"; + gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu0"; + }; + + usr0-led { + label = "status0:green:usr"; + gpios = <&gpio3 11 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + heartbeat-led { + label = "status0:blue:heartbeat"; + gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + cpu1-led { + label = "status1:red:cpu1"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "cpu1"; + }; + + usr1-led { + label = "status1:green:usr"; + gpios = <&gpio7 23 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + mmc0-led { + label = "status1:blue:mmc0"; + gpios = <&gpio7 22 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + }; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&mmc1 { + status = "okay"; + vmmc-supply = <&v3_3d>; + vmmc_aux-supply = <&ldo1_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 0>; /* gpio 219 */ +}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index 4168eb9dd369..81d6c3033b51 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "dra74x.dtsi" +#include "am57xx-commercial-grade.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> @@ -144,7 +145,7 @@ }; }; - sound0: sound@0 { + sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "BeagleBoard-X15"; simple-audio-card,widgets = @@ -166,8 +167,6 @@ sound0_master: simple-audio-card,codec { sound-dai = <&tlv320aic3104>; - assigned-clocks = <&clkoutmux2_clk_mux>; - assigned-clock-parents = <&sys_clk2_dclk_div>; clocks = <&clkout2_clk>; }; }; @@ -427,7 +426,7 @@ /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ regulator-name = "smps45"; regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; @@ -436,7 +435,7 @@ /* VDD_CORE */ regulator-name = "smps6"; regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1030000>; + regulator-max-microvolt = <1150000>; regulator-always-on; regulator-boot-on; }; @@ -571,6 +570,9 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&clkout2_pins_default>; pinctrl-1 = <&clkout2_pins_sleep>; + assigned-clocks = <&clkoutmux2_clk_mux>; + assigned-clock-parents = <&sys_clk2_dclk_div>; + status = "okay"; adc-settle-ms = <40>; @@ -795,6 +797,8 @@ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 2 0 0 >; + tx-num-evt = <32>; + rx-num-evt = <32>; }; &mailbox5 { diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 14f912a1b4fd..378b142ef88c 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -51,7 +51,7 @@ regulator-max-microvolt = <3300000>; }; - sound0: sound@0 { + sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "CL-SOM-AM57x-Sound-Card"; simple-audio-card,format = "i2s"; diff --git a/arch/arm/boot/dts/am57xx-commercial-grade.dtsi b/arch/arm/boot/dts/am57xx-commercial-grade.dtsi new file mode 100644 index 000000000000..c183654464e9 --- /dev/null +++ b/arch/arm/boot/dts/am57xx-commercial-grade.dtsi @@ -0,0 +1,23 @@ +&cpu_alert0 { + temperature = <80000>; /* milliCelsius */ +}; + +&cpu_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&gpu_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&core_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&dspeve_crit { + temperature = <90000>; /* milliCelsius */ +}; + +&iva_crit { + temperature = <90000>; /* milliCelsius */ +}; diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi new file mode 100644 index 000000000000..b01a5948cdd0 --- /dev/null +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -0,0 +1,304 @@ +/* + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "am57xx-industrial-grade.dtsi" + +/ { + aliases { + rtc0 = &tps659038_rtc; + rtc1 = &rtc; + }; + + vmain: fixedregulator-vmain { + compatible = "regulator-fixed"; + regulator-name = "VMAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + v3_3d: fixedregulator-v3_3d { + compatible = "regulator-fixed"; + regulator-name = "V3_3D"; + vin-supply = <&smps9_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&v3_3d>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_HIGH + &dra7_pmx_core 0x418>; + #interrupt-cells = <2>; + interrupt-controller; + ti,system-power-controller; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + vin-supply = <&vmain>; + regulator-name = "smps12"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR EMIF1 EMIF2 */ + vin-supply = <&vmain>; + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE on AM572 */ + /* VDD_IVA + VDD_DSP on AM571 */ + vin-supply = <&vmain>; + regulator-name = "smps45"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_GPU */ + vin-supply = <&vmain>; + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps7_reg: smps7 { + /* VDD_CORE */ + vin-supply = <&vmain>; + regulator-name = "smps7"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + smps8_reg: smps8 { + /* 5728 - VDD_IVAHD */ + /* 5718 - N.C. test point */ + vin-supply = <&vmain>; + regulator-name = "smps8"; + }; + + smps9_reg: smps9 { + /* VDD_3_3D */ + vin-supply = <&vmain>; + regulator-name = "smps9"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: ldo1 { + /* VDDSHV8 - VSDMMC */ + /* NOTE: on rev 1.3a, data supply */ + vin-supply = <&vmain>; + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + /* VDDSH18V */ + vin-supply = <&vmain>; + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* R1.3a 572x V1_8PHY_LDO3: USB, SATA */ + vin-supply = <&vmain>; + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/ + vin-supply = <&vmain>; + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* LDO5-8 unused */ + + ldo9_reg: ldo9 { + /* VDD_RTC */ + vin-supply = <&vmain>; + regulator-name = "ldo9"; + regulator-min-microvolt = <840000>; + regulator-max-microvolt = <1160000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + vin-supply = <&vmain>; + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + vin-supply = <&vmain>; + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldortc_reg: ldortc { + /* VDDA_RTC */ + vin-supply = <&vmain>; + regulator-name = "ldortc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + + regen2: regen2 { + /* Needed for PMIC internal resource */ + regulator-name = "regen2"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH + &dra7_pmx_core 0x248>; +}; + +&rtc { + status = "okay"; + ext-clk-src; +}; + +&mac { + status = "okay"; + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <0>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; +}; + +&usb2 { + dr_mode = "otg"; +}; + +&mmc2 { + status = "okay"; + vmmc-supply = <&v3_3d>; + bus-width = <8>; + ti,non-removable; + max-frequency = <96000000>; +}; diff --git a/arch/arm/boot/dts/am57xx-industrial-grade.dtsi b/arch/arm/boot/dts/am57xx-industrial-grade.dtsi new file mode 100644 index 000000000000..70c8c4ba1933 --- /dev/null +++ b/arch/arm/boot/dts/am57xx-industrial-grade.dtsi @@ -0,0 +1,23 @@ +&cpu_alert0 { + temperature = <90000>; /* milliCelsius */ +}; + +&cpu_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&gpu_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&core_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&dspeve_crit { + temperature = <105000>; /* milliCelsius */ +}; + +&iva_crit { + temperature = <105000>; /* milliCelsius */ +}; diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts b/arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts new file mode 100644 index 000000000000..e68527b0d552 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts @@ -0,0 +1,93 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-11mp.dts" + +/ { + model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B"; +}; + +/* + * The revision B has a distinctly different layout of the syscon, so + * append a specific compatible-string. + */ +&syscon { + compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd"; +}; + +&intc { + reg = <0x10101000 0x1000>, + <0x10100100 0x100>; +}; + +&L2 { + reg = <0x10102000 0x1000>; +}; + +&scu { + reg = <0x10100000 0x100>; +}; + +&twd_timer { + reg = <0x10100600 0x20>; +}; + +&twd_wdog { + reg = <0x10100620 0x20>; +}; + +/* + * On revision B, we cannot reach the secondary interrupt + * controller, as a result, some peripherals that are dependent + * on their IRQ cannot be reached, so disable them. + */ +&intc_second { + status = "disabled"; +}; + +&gpio0 { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; + +&gpio2 { + status = "disabled"; +}; + +&serial2 { + status = "disabled"; +}; + +&serial3 { + status = "disabled"; +}; + +&ssp { + status = "disabled"; +}; + +&wdog { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp.dts b/arch/arm/boot/dts/arm-realview-eb-11mp.dts new file mode 100644 index 000000000000..87ff602a2a2d --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb-11mp.dts @@ -0,0 +1,74 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include "arm-realview-eb-mp.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C"; + arm,hbi = <0x146>; + + /* + * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB. + * Reference: ARM DUI 0318F + * + * To run this machine with QEMU, specify the following: + * qemu-system-arm -M realview-eb-mpcore -smp cpus=4 + */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "arm,realview-smp"; + + MP11_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <0>; + next-level-cache = <&L2>; + }; + + MP11_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <1>; + next-level-cache = <&L2>; + }; + + MP11_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <2>; + next-level-cache = <&L2>; + }; + + MP11_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,arm11mpcore"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; +}; + +&pmu { + interrupt-affinity = <&MP11_0>, <&MP11_1>, <&MP11_2>, <&MP11_3>; +}; diff --git a/arch/arm/boot/dts/arm-realview-eb-a9mp.dts b/arch/arm/boot/dts/arm-realview-eb-a9mp.dts new file mode 100644 index 000000000000..967684b3636c --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb-a9mp.dts @@ -0,0 +1,70 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include "arm-realview-eb-mp.dtsi" + +/ { + model = "ARM RealView EB Cortex A9 MPCore"; + + /* + * This is the Cortex A9 MPCore tile used with the + * RealView EB. + */ + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "arm,realview-smp"; + + A9_0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + }; + + A9_1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + A9_2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + A9_3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; +}; + +&pmu { + interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>; +}; diff --git a/arch/arm/boot/dts/arm-realview-eb-mp.dtsi b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi new file mode 100644 index 000000000000..7b8d90b7aeea --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb-mp.dtsi @@ -0,0 +1,225 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include "arm-realview-eb.dtsi" + +/* + * This is the common include file for all MPCore variants of the + * Evaluation Baseboard, i.e. ARM11MPCore, ARM11MPCore Revision B + * and Cortex-A9 MPCore. + */ +/ { + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-eb-soc", "simple-bus"; + regmap = <&syscon>; + ranges; + + /* Primary interrupt controller in the test chip */ + intc: interrupt-controller@1f000100 { + compatible = "arm,eb11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x1f001000 0x1000>, + <0x1f000100 0x100>; + }; + + /* Secondary interrupt controller on the FPGA */ + intc_second: interrupt-controller@10040000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10041000 0x1000>, + <0x10040000 0x100>; + interrupt-parent = <&intc>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + }; + + L2: l2-cache { + compatible = "arm,l220-cache"; + reg = <0x1f002000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, + <0 30 IRQ_TYPE_LEVEL_HIGH>, + <0 31 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s), probably for safety + * since th outer sync operation can cause the + * cache to hang unless disabled. + */ + cache-size = <1048576>; // 1MB + cache-sets = <4096>; + cache-line-size = <32>; + arm,shared-override; + arm,parity-enable; + arm,outer-sync-disable; + }; + + scu: scu@1f000000 { + compatible = "arm,arm11mp-scu"; + reg = <0x1f000000 0x100>; + }; + + twd_timer: timer@1f000600 { + compatible = "arm,arm11mp-twd-timer"; + reg = <0x1f000600 0x20>; + interrupt-parent = <&intc>; + interrupts = <1 13 0xf04>; + }; + + twd_wdog: watchdog@1f000620 { + compatible = "arm,arm11mp-twd-wdt"; + reg = <0x1f000620 0x20>; + interrupt-parent = <&intc>; + interrupts = <1 14 0xf04>; + }; + + /* PMU with one IRQ line per core */ + pmu: pmu@0 { + compatible = "arm,arm11mpcore-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>, + <0 19 IRQ_TYPE_LEVEL_HIGH>, + <0 20 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +}; + +/* + * This adapts all the peripherals to the interrupt routing + * to the GIC on the core tile. + */ + +ðernet { + interrupt-parent = <&intc>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usb { + interrupt-parent = <&intc>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; +}; + +&aaci { + interrupt-parent = <&intc>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmc { + interrupt-parent = <&intc>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi0 { + interrupt-parent = <&intc>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi1 { + interrupt-parent = <&intc>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&charlcd { + interrupt-parent = <&intc>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial0 { + interrupt-parent = <&intc>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial1 { + interrupt-parent = <&intc>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer01 { + interrupt-parent = <&intc>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer23 { + interrupt-parent = <&intc>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; +}; + +&rtc { + interrupt-parent = <&intc>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +/* + * On revision A, these peripherals does not have their IRQ lines + * routed to the core tile, but they can be reached on the secondary + * GIC. + */ +&gpio0 { + interrupt-parent = <&intc_second>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio1 { + interrupt-parent = <&intc_second>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio2 { + interrupt-parent = <&intc_second>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial2 { + interrupt-parent = <&intc_second>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&serial3 { + interrupt-parent = <&intc_second>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&ssp { + interrupt-parent = <&intc_second>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; + +&wdog { + interrupt-parent = <&intc_second>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/arm-realview-eb.dts b/arch/arm/boot/dts/arm-realview-eb.dts new file mode 100644 index 000000000000..15431077f00c --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb.dts @@ -0,0 +1,166 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include "arm-realview-eb.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard"; + compatible = "arm,realview-eb"; + arm,hbi = <0x140>; + + /* + * This is the core tile with the CPU and GIC etc for the + * ARM926EJ-S, ARM1136, ARM1176 that does not have L2 cache + * or PMU. + * + * To run this machine with QEMU, specify the following: + * qemu-system-arm -M realview-eb + * Unless specified, QEMU will emulate an ARM926EJ-S core tile. + * Switches -cpu arm1136 or -cpu arm1176 emulates the other + * core tiles. + */ + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-eb-soc", "simple-bus"; + regmap = <&syscon>; + ranges; + + intc: interrupt-controller@10040000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10041000 0x1000>, + <0x10040000 0x100>; + }; + }; +}; + +/* + * This adapts all the peripherals to the interrupt routing + * to the GIC on the core tile. + */ + +ðernet { + interrupt-parent = <&intc>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usb { + interrupt-parent = <&intc>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +}; + +&aaci { + interrupt-parent = <&intc>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmc { + interrupt-parent = <&intc>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi0 { + interrupt-parent = <&intc>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi1 { + interrupt-parent = <&intc>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +}; + +&charlcd { + interrupt-parent = <&intc>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial0 { + interrupt-parent = <&intc>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial1 { + interrupt-parent = <&intc>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial2 { + interrupt-parent = <&intc>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial3 { + interrupt-parent = <&intc>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&ssp { + interrupt-parent = <&intc>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog { + interrupt-parent = <&intc>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer01 { + interrupt-parent = <&intc>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer23 { + interrupt-parent = <&intc>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio0 { + interrupt-parent = <&intc>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio1 { + interrupt-parent = <&intc>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio2 { + interrupt-parent = <&intc>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&rtc { + interrupt-parent = <&intc>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +}; + +&clcd { + interrupt-parent = <&intc>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi new file mode 100644 index 000000000000..1c6a040218e3 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -0,0 +1,453 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include "skeleton.dtsi" + +/ { + compatible = "arm,realview-eb"; + + chosen { }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c; + }; + + memory { + /* 128 MiB memory @ 0x0 */ + reg = <0x00000000 0x08000000>; + }; + + /* The voltage to the MMC card is hardwired at 3.3V */ + vmmc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + veth: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "veth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + mclk: mclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + kmiclk: kmiclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + sspclk: sspclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + uartclk: uartclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + wdogclk: wdogclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* FIXME: this actually hangs off the PLL clocks */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + flash0@40000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x40000000 0x04000000>; + bank-width = <4>; + }; + + flash1@44000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x44000000 0x04000000>; + bank-width = <4>; + }; + + /* SMSC 9118 ethernet with PHY and EEPROM */ + ethernet: ethernet@4e000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <0x4e000000 0x10000>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&veth>; + vddvario-supply = <&veth>; + }; + + usb: usb@4f000000 { + compatible = "nxp,usb-isp1761"; + reg = <0x4f000000 0x20000>; + port1-otg; + }; + + /* These peripherals are inside the FPGA */ + fpga { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + syscon: syscon@10000000 { + compatible = "arm,realview-eb-syscon", "syscon", "simple-mfd"; + reg = <0x10000000 0x1000>; + + led@08.0 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@08.1 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@08.2 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@08.3 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x08>; + label = "versatile:3"; + default-state = "off"; + }; + led@08.4 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x10>; + label = "versatile:4"; + default-state = "off"; + }; + led@08.5 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x20>; + label = "versatile:5"; + default-state = "off"; + }; + led@08.6 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x40>; + label = "versatile:6"; + default-state = "off"; + }; + led@08.7 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x80>; + label = "versatile:7"; + default-state = "off"; + }; + oscclk0: osc0@0c { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x0C>; + clocks = <&xtal24mhz>; + }; + oscclk1: osc1@10 { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x10>; + clocks = <&xtal24mhz>; + }; + oscclk2: osc2@14 { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x14>; + clocks = <&xtal24mhz>; + }; + oscclk3: osc3@18 { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x18>; + clocks = <&xtal24mhz>; + }; + oscclk4: osc4@1c { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x1c>; + clocks = <&xtal24mhz>; + }; + }; + + i2c: i2c@10002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10002000 0x1000>; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + }; + + aaci: aaci@10004000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x10004000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + mmc: mmcsd@10005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x10005000 0x1000>; + + /* Due to frequent FIFO overruns, use just 500 kHz */ + max-frequency = <500000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + clocks = <&mclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + vmmc-supply = <&vmmc>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + + kmi0: kmi@10006000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10006000 0x1000>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi1: kmi@10007000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10007000 0x1000>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + charlcd: fpga_charlcd: charlcd@10008000 { + compatible = "arm,versatile-lcd"; + reg = <0x10008000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + serial0: serial@10009000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x10009000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial1: serial@1000a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000a000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial2: serial@1000b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000b000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial3: serial@1000c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000c000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + ssp: ssp@1000d000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1000d000 0x1000>; + clocks = <&sspclk>, <&pclk>; + clock-names = "SSPCLK", "apb_pclk"; + }; + + wdog: watchdog@10010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x10010000 0x1000>; + clocks = <&wdogclk>, <&pclk>; + clock-names = "wdogclk", "apb_pclk"; + status = "disabled"; + }; + + timer01: timer@10011000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10011000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer23: timer@10012000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10012000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + gpio0: gpio@10013000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10013000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@10014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10014000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@10015000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10015000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + rtc: rtc@10017000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10017000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + clcd: clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupt-names = "combined"; + clocks = <&oscclk0>, <&pclk>; + clock-names = "clcdclk", "apb_pclk"; + + port { + clcd_pads: endpoint { + remote-endpoint = <&clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + clcd_panel: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + /* Standard 640x480 VGA timings */ + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <33>; + vfront-porch = <10>; + vsync-len = <2>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts index 652d85b28aaa..c789564f2803 100644 --- a/arch/arm/boot/dts/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -394,6 +394,46 @@ reg = <0x10200000 0x4000>; bank-width = <1>; }; + + clcd@10112000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10112000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupt-names = "combined"; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&oscclk0>, <&pclk>; + clock-names = "clcdclk", "apb_pclk"; + + port { + clcd_pads: endpoint { + remote-endpoint = <&clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + clcd_panel: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + /* Standard 640x480 VGA timings */ + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <33>; + vfront-porch = <10>; + vsync-len = <2>; + }; + }; + }; }; /* These peripherals are inside the FPGA rather than the DevChip */ diff --git a/arch/arm/boot/dts/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm-realview-pb11mp.dts index 63d6a051839f..3944765ac4b0 100644 --- a/arch/arm/boot/dts/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm-realview-pb11mp.dts @@ -627,16 +627,17 @@ }; }; + /* Standard 640x480 VGA timings */ panel-timing { - clock-frequency = <63500127>; - hactive = <1024>; - hback-porch = <152>; - hfront-porch = <48>; - hsync-len = <104>; - vactive = <768>; - vback-porch = <23>; - vfront-porch = <3>; - vsync-len = <4>; + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <33>; + vfront-porch = <10>; + vsync-len = <2>; }; }; }; diff --git a/arch/arm/boot/dts/arm-realview-pba8.dts b/arch/arm/boot/dts/arm-realview-pba8.dts new file mode 100644 index 000000000000..d3238c252b59 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-pba8.dts @@ -0,0 +1,178 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include "arm-realview-pbx.dtsi" + +/ { + model = "ARM RealView Platform Baseboard for Cortex-A8"; + compatible = "arm,realview-pba8"; + arm,hbi = <0x178>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "arm,realview-smp"; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a8"; + reg = <0>; + }; + }; + + pmu: pmu@0 { + compatible = "arm,cortex-a8-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + }; + + /* Primary GIC PL390 interrupt controller in the test chip */ + intc: interrupt-controller@1e000000 { + compatible = "arm,pl390"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x1e001000 0x1000>, + <0x1e000000 0x100>; + }; +}; + +ðernet { + interrupt-parent = <&intc>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usb { + interrupt-parent = <&intc>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +}; + +&soc { + compatible = "arm,realview-pba8-soc", "simple-bus"; +}; + +&syscon { + compatible = "arm,realview-pba8-syscon", "syscon", "simple-mfd"; +}; + +&serial0 { + interrupt-parent = <&intc>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial1 { + interrupt-parent = <&intc>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial2 { + interrupt-parent = <&intc>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial3 { + interrupt-parent = <&intc>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&ssp { + interrupt-parent = <&intc>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog0 { + interrupt-parent = <&intc>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog1 { + interrupt-parent = <&intc>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer01 { + interrupt-parent = <&intc>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer23 { + interrupt-parent = <&intc>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio0 { + interrupt-parent = <&intc>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio1 { + interrupt-parent = <&intc>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio2 { + interrupt-parent = <&intc>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&rtc { + interrupt-parent = <&intc>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer45 { + interrupt-parent = <&intc>; + interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer67 { + interrupt-parent = <&intc>; + interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; +}; + +&aaci { + interrupt-parent = <&intc>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmc { + interrupt-parent = <&intc>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi0 { + interrupt-parent = <&intc>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi1 { + interrupt-parent = <&intc>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +}; + +&clcd { + interrupt-parent = <&intc>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm/boot/dts/arm-realview-pbx-a9.dts b/arch/arm/boot/dts/arm-realview-pbx-a9.dts new file mode 100644 index 000000000000..db808f92dd79 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-pbx-a9.dts @@ -0,0 +1,229 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include "arm-realview-pbx.dtsi" + +/ { + /* + * This is the RealView Platform Baseboard Explore for Cortex-A9 + * (HBI0182 + HBI0183) as described in ARM DUI 0440B + */ + model = "ARM RealView Platform Baseboard Explore for Cortex-A9"; + arm,hbi = <0x182>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "arm,realview-smp"; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + }; + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x0>; + next-level-cache = <&L2>; + }; + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x1>; + next-level-cache = <&L2>; + }; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x1f002000 0x1000>; + cache-unified; + cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s). + */ + cache-size = <1048576>; // 1MB + cache-sets = <4096>; + cache-line-size = <32>; + arm,parity-disable; + arm,tag-latency = <1>; + arm,data-latency = <1 1>; + arm,dirty-latency = <1>; + }; + + scu: scu@1f000000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1f000000 0x100>; + }; + + twd_timer: timer@1f000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1f000600 0x20>; + interrupt-parent = <&intc>; + interrupts = <1 13 0xf04>; + }; + + twd_wdog: watchdog@1f000620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1f000620 0x20>; + interrupt-parent = <&intc>; + interrupts = <1 14 0xf04>; + }; + + pmu: pmu@0 { + compatible = "arm,cortex-a9-pmu"; + interrupt-parent = <&intc>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>, + <0 45 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&CPU0>, <&CPU1>; + }; + + /* Primary GIC PL390 interrupt controller in the test chip */ + intc: interrupt-controller@1f000000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x1f001000 0x1000>, + <0x1f000100 0x100>; + }; +}; + +ðernet { + interrupt-parent = <&intc>; + interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usb { + interrupt-parent = <&intc>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial0 { + interrupt-parent = <&intc>; + interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial1 { + interrupt-parent = <&intc>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial2 { + interrupt-parent = <&intc>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; +}; + +&serial3 { + interrupt-parent = <&intc>; + interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; +}; + +&ssp { + interrupt-parent = <&intc>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog0 { + interrupt-parent = <&intc>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; +}; + +&wdog1 { + interrupt-parent = <&intc>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer01 { + interrupt-parent = <&intc>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer23 { + interrupt-parent = <&intc>; + interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio0 { + interrupt-parent = <&intc>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio1 { + interrupt-parent = <&intc>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio2 { + interrupt-parent = <&intc>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; +}; + +&rtc { + interrupt-parent = <&intc>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer45 { + interrupt-parent = <&intc>; + interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; +}; + +&timer67 { + interrupt-parent = <&intc>; + interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; +}; + +&aaci { + interrupt-parent = <&intc>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; +}; + +&mmc { + interrupt-parent = <&intc>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>, + <0 18 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi0 { + interrupt-parent = <&intc>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; +}; + +&kmi1 { + interrupt-parent = <&intc>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; +}; + +&clcd { + interrupt-parent = <&intc>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm/boot/dts/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm-realview-pbx.dtsi new file mode 100644 index 000000000000..aeb49c4bd773 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-pbx.dtsi @@ -0,0 +1,542 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include "skeleton.dtsi" + +/ { + compatible = "arm,realview-pbx"; + + chosen { }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c; + }; + + memory { + /* 128 MiB memory @ 0x0 */ + reg = <0x00000000 0x08000000>; + }; + + /* The voltage to the MMC card is hardwired at 3.3V */ + vmmc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + veth: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "veth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + refclk32khz: refclk32khz { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + mclk: mclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + kmiclk: kmiclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + sspclk: sspclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + uartclk: uartclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + wdogclk: wdogclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* FIXME: this actually hangs off the PLL clocks */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + flash0@40000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x40000000 0x04000000>; + bank-width = <4>; + }; + + flash1@44000000 { + /* 2 * 32MiB NOR Flash memory */ + compatible = "arm,versatile-flash", "cfi-flash"; + reg = <0x44000000 0x04000000>; + bank-width = <4>; + }; + + /* SMSC 9118 ethernet with PHY and EEPROM */ + ethernet: ethernet@4e000000 { + compatible = "smsc,lan9118", "smsc,lan9115"; + reg = <0x4e000000 0x10000>; + phy-mode = "mii"; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&veth>; + vddvario-supply = <&veth>; + }; + + usb: usb@4f000000 { + compatible = "nxp,usb-isp1761"; + reg = <0x4f000000 0x20000>; + port1-otg; + }; + + soc: soc@0 { + compatible = "arm,realview-pbx-soc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + regmap = <&syscon>; + ranges; + + syscon: syscon@10000000 { + compatible = "arm,realview-pbx-syscon", "syscon", "simple-mfd"; + reg = <0x10000000 0x1000>; + + led@08.0 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@08.1 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@08.2 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@08.3 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x08>; + label = "versatile:3"; + default-state = "off"; + }; + led@08.4 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x10>; + label = "versatile:4"; + default-state = "off"; + }; + led@08.5 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x20>; + label = "versatile:5"; + default-state = "off"; + }; + led@08.6 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x40>; + label = "versatile:6"; + default-state = "off"; + }; + led@08.7 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x80>; + label = "versatile:7"; + default-state = "off"; + }; + oscclk0: osc0@0c { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x0C>; + clocks = <&xtal24mhz>; + }; + oscclk1: osc1@10 { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x10>; + clocks = <&xtal24mhz>; + }; + oscclk2: osc2@14 { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x14>; + clocks = <&xtal24mhz>; + }; + oscclk3: osc3@18 { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x18>; + clocks = <&xtal24mhz>; + }; + oscclk4: osc4@1c { + compatible = "arm,syscon-icst307"; + #clock-cells = <0>; + lock-offset = <0x20>; + vco-offset = <0x1c>; + clocks = <&xtal24mhz>; + }; + }; + + sp810_syscon0: sysctl@10001000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x10001000 0x1000>; + clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclk0", + "timerclk1", + "timerclk2", + "timerclk3"; + assigned-clocks = <&sp810_syscon0 0>, + <&sp810_syscon0 1>, + <&sp810_syscon0 2>, + <&sp810_syscon0 3>; + assigned-clock-parents = <&timclk>, + <&timclk>, + <&timclk>, + <&timclk>; + }; + + i2c: i2c@10002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "arm,versatile-i2c"; + reg = <0x10002000 0x1000>; + + rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; + }; + + serial0: serial@10009000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x10009000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial1: serial@1000a000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000a000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial2: serial@1000b000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000b000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + ssp: ssp@1000d000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1000d000 0x1000>; + clocks = <&sspclk>, <&pclk>; + clock-names = "SSPCLK", "apb_pclk"; + }; + + wdog0: watchdog@1000f000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x1000f000 0x1000>; + clocks = <&wdogclk>, <&pclk>; + clock-names = "wdogclk", "apb_pclk"; + status = "disabled"; + }; + + wdog1: watchdog@10010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x10010000 0x1000>; + clocks = <&wdogclk>, <&pclk>; + clock-names = "wdogclk", "apb_pclk"; + status = "disabled"; + }; + + timer01: timer@10011000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10011000 0x1000>; + clocks = <&sp810_syscon0 0>, + <&sp810_syscon0 1>, + <&pclk>; + clock-names = "timerclk0", + "timerclk1", + "apb_pclk"; + }; + + timer23: timer@10012000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10012000 0x1000>; + clocks = <&sp810_syscon0 2>, + <&sp810_syscon0 3>, + <&pclk>; + clock-names = "timerclk2", + "timerclk3", + "apb_pclk"; + }; + + gpio0: gpio@10013000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10013000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio1: gpio@10014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10014000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + gpio2: gpio@10015000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10015000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + /* DVI serial bus control is at 10016000 */ + + rtc: rtc@10017000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10017000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + timer45: timer@10018000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10018000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timerclk4", "timerclk5", "apb_pclk"; + }; + + timer67: timer@10019000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10019000 0x1000>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timerclk6", "timerclk7", "apb_pclk"; + }; + + sp810_syscon1: sysctl@1001a000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x1001a000 0x1000>; + clocks = <&refclk32khz>, <&timclk>, <&xtal24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclk4", + "timerclk5", + "timerclk6", + "timerclk7"; + assigned-clocks = <&sp810_syscon1 0>, + <&sp810_syscon1 1>, + <&sp810_syscon1 2>, + <&sp810_syscon1 3>; + assigned-clock-parents = <&timclk>, + <&timclk>, + <&timclk>, + <&timclk>; + }; + }; + + + /* These peripherals are inside the FPGA */ + fpga { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aaci: aaci@10004000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x10004000 0x1000>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + mmc: mmcsd@10005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x10005000 0x1000>; + + /* Due to frequent FIFO overruns, use just 500 kHz */ + max-frequency = <500000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + clocks = <&mclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + vmmc-supply = <&vmmc>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + + kmi0: kmi@10006000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10006000 0x1000>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi1: kmi@10007000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10007000 0x1000>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + serial3: serial@1000c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1000c000 0x1000>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + }; + + /* These peripherals are inside the NEC ISSP */ + issp { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + clcd: clcd@10020000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x10020000 0x1000>; + interrupt-names = "combined"; + clocks = <&oscclk4>, <&pclk>; + clock-names = "clcdclk", "apb_pclk"; + + port { + clcd_pads: endpoint { + remote-endpoint = <&clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + clcd_panel: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + /* Standard 640x480 VGA timings */ + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <33>; + vfront-porch = <10>; + vsync-len = <2>; + }; + }; + }; + }; +}; + diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 85d2c377c332..8450944b28e6 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -245,7 +245,7 @@ button@2 { label = "Factory Reset Button"; linux,code = <KEY_RESTART>; - gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; }; @@ -260,7 +260,7 @@ }; sata { - gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; default-state = "off"; }; }; @@ -313,7 +313,7 @@ &pinctrl { keys_pin: keys-pin { - marvell,pins = "mpp24", "mpp47"; + marvell,pins = "mpp24", "mpp29"; marvell,function = "gpio"; }; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index b89e6cf1271a..7a461541ce50 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -304,13 +304,13 @@ button@1 { label = "WPS"; linux,code = <KEY_WPS_BUTTON>; - gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; }; button@2 { label = "Factory Reset Button"; linux,code = <KEY_RESTART>; - gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/armv7-m.dtsi b/arch/arm/boot/dts/armv7-m.dtsi index b1ad7cf6ac02..16331aa79775 100644 --- a/arch/arm/boot/dts/armv7-m.dtsi +++ b/arch/arm/boot/dts/armv7-m.dtsi @@ -1,7 +1,7 @@ #include "skeleton.dtsi" / { - nvic: nv-interrupt-controller { + nvic: interrupt-controller@e000e100 { compatible = "arm,armv7m-nvic"; interrupt-controller; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 30430162b886..3fac4c4d0007 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -91,96 +91,32 @@ clock-frequency = <50000000>; }; - /* PLL1 is used by CPU and some peripherals */ - pll1_clk: pll1_clk@f8000000 { + eth_phy_ref_clk: eth_phy_ref_clk { #clock-cells = <0>; - compatible = "axis,artpec6-pll1-clock"; - reg = <0xf8000000 4>; - clocks = <&ext_clk>; - }; - - cpu_clk: cpu_clk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&pll1_clk>; - clock-output-names = "cpu_clk"; - }; - - cpu_clkdiv2: cpu_clkdiv2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&cpu_clk>; - }; - - cpu_clkdiv4: cpu_clkdiv4 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <4>; - clock-mult = <1>; - clocks = <&cpu_clk>; - }; - - apb_pclk: apb_pclk { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <8>; - clock-mult = <1>; - clocks = <&cpu_clk>; - clock-output-names = "apb_pclk"; + compatible = "fixed-clock"; + clock-frequency = <125000000>; }; - /* PLL2 is used by a number of peripherals, including UDL */ - pll2: pll2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <24>; + clkctrl: clkctrl@0xf8000000 { + #clock-cells = <1>; + compatible = "axis,artpec6-clkctrl"; + reg = <0xf8000000 0x48>; clocks = <&ext_clk>; + clock-names = "sys_refclk"; }; - /* PLL2DIV2 is used by the Fractional Clock Divider, for i2s */ - pll2div2: pll2div2 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <2>; - clock-mult = <1>; - clocks = <&pll2>; - }; - - pll2div12: pll2div12 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <12>; - clock-mult = <1>; - clocks = <&pll2>; - }; - - pll2div24: pll2div24 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <24>; - clock-mult = <1>; - clocks = <&pll2>; - clock-output-names = "uart_clk"; - }; - - gtimer@faf00200 { compatible = "arm,cortex-a9-global-timer"; reg = <0xfaf00200 0x20>; interrupts = <GIC_PPI 11 0xf01>; - clocks = <&cpu_clkdiv2>; + clocks = <&clkctrl 1>; }; timer@faf00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xfaf00600 0x20>; interrupts = <GIC_PPI 13 0xf04>; - clocks = <&cpu_clkdiv2>; + clocks = <&clkctrl 1>; status = "disabled"; }; @@ -220,7 +156,8 @@ ethernet: ethernet@f8010000 { clock-names = "phy_ref_clk", "apb_pclk"; - clocks = <&ext_clk>, <&apb_pclk>; + clocks = <ð_phy_ref_clk>, + <&clkctrl 4>; compatible = "snps,dwc-qos-ethernet-4.10"; interrupt-parent = <&intc>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; @@ -238,7 +175,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8036000 0x1000>; interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pll2div24>, <&apb_pclk>; + clocks = <&clkctrl 13>, + <&clkctrl 12>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; @@ -246,7 +184,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8037000 0x1000>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pll2div24>, <&apb_pclk>; + clocks = <&clkctrl 13>, + <&clkctrl 12>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; @@ -254,7 +193,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8038000 0x1000>; interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pll2div24>, <&apb_pclk>; + clocks = <&clkctrl 13>, + <&clkctrl 12>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; @@ -262,7 +202,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8039000 0x1000>; interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&pll2div24>, <&apb_pclk>; + clocks = <&clkctrl 13>, + <&clkctrl 12>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts new file mode 100644 index 000000000000..1b7a5ff0e533 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts @@ -0,0 +1,25 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + model = "AST2500 EVB"; + compatible = "aspeed,ast2500"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200 earlyprintk"; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&uart5 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts new file mode 100644 index 000000000000..cc5fcf2940bf --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts @@ -0,0 +1,25 @@ +/dts-v1/; + +#include "aspeed-g4.dtsi" + +/ { + model = "Palmetto BMC"; + compatible = "tyan,palmetto-bmc", "aspeed,ast2400"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,38400 earlyprintk"; + }; + + memory { + reg = <0x40000000 0x10000000>; + }; +}; + +&uart5 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi new file mode 100644 index 000000000000..22dee5937d5c --- /dev/null +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -0,0 +1,161 @@ +#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2400"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm926ej-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + clocks { + clk_clkin: clk_clkin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <48000000>; + }; + + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xffffffff 0x0007ffff>; + reg = <0x1e6c0080 0x80>; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_hpll: clk_hpll@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g4-hpll-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_clkin>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g4-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x8000>; // 32K + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registers only one + // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + }; + + wdt1: wdt@1e785000 { + compatible = "aspeed,wdt"; + reg = <0x1e785000 0x1c>; + interrupts = <27>; + }; + + wdt2: wdt@1e785020 { + compatible = "aspeed,wdt"; + reg = <0x1e785020 0x1c>; + interrupts = <27>; + clocks = <&clk_apb>; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + uart6: serial@1e787000 { + compatible = "ns16550a"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi new file mode 100644 index 000000000000..dd94d9361fda --- /dev/null +++ b/arch/arm/boot/dts/aspeed-g5.dtsi @@ -0,0 +1,170 @@ +#include "skeleton.dtsi" + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2500"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&vic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,arm1176jzf-s"; + device_type = "cpu"; + reg = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + vic: interrupt-controller@1e6c0080 { + compatible = "aspeed,ast2400-vic"; + interrupt-controller; + #interrupt-cells = <1>; + valid-sources = <0xfefff7ff 0x0807ffff>; + reg = <0x1e6c0080 0x80>; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clk_clkin: clk_clkin@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-clkin-clock"; + reg = <0x1e6e2070 0x04>; + }; + + clk_hpll: clk_hpll@1e6e2024 { + #clock-cells = <0>; + compatible = "aspeed,g5-hpll-clock"; + reg = <0x1e6e2024 0x4>; + clocks = <&clk_clkin>; + }; + + clk_ahb: clk_ahb@1e6e2070 { + #clock-cells = <0>; + compatible = "aspeed,g5-ahb-clock"; + reg = <0x1e6e2070 0x4>; + clocks = <&clk_hpll>; + }; + + clk_apb: clk_apb@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,g5-apb-clock"; + reg = <0x1e6e2008 0x4>; + clocks = <&clk_hpll>; + }; + + clk_uart: clk_uart@1e6e2008 { + #clock-cells = <0>; + compatible = "aspeed,uart-clock"; + reg = <0x1e6e202c 0x4>; + }; + + sram@1e720000 { + compatible = "mmio-sram"; + reg = <0x1e720000 0x9000>; // 36K + }; + + timer: timer@1e782000 { + compatible = "aspeed,ast2400-timer"; + reg = <0x1e782000 0x90>; + // The moxart_timer driver registers only one + // interrupt and assumes it's for timer 1 + //interrupts = <16 17 18 35 36 37 38 39>; + interrupts = <16>; + clocks = <&clk_apb>; + }; + + wdt1: wdt@1e785000 { + compatible = "aspeed,wdt"; + reg = <0x1e785000 0x1c>; + interrupts = <27>; + }; + + wdt2: wdt@1e785020 { + compatible = "aspeed,wdt"; + reg = <0x1e785020 0x1c>; + interrupts = <27>; + status = "disabled"; + }; + + wdt3: wdt@1e785040 { + compatible = "aspeed,wdt"; + reg = <0x1e785074 0x1c>; + status = "disabled"; + }; + + uart1: serial@1e783000 { + compatible = "ns16550a"; + reg = <0x1e783000 0x1000>; + reg-shift = <2>; + interrupts = <9>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@1e78d000 { + compatible = "ns16550a"; + reg = <0x1e78d000 0x1000>; + reg-shift = <2>; + interrupts = <32>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@1e78e000 { + compatible = "ns16550a"; + reg = <0x1e78e000 0x1000>; + reg-shift = <2>; + interrupts = <33>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart4: serial@1e78f000 { + compatible = "ns16550a"; + reg = <0x1e78f000 0x1000>; + reg-shift = <2>; + interrupts = <34>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@1e784000 { + compatible = "ns16550a"; + reg = <0x1e784000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + current-speed = <38400>; + no-loopback-test; + status = "disabled"; + }; + + uart6: serial@1e787000 { + compatible = "ns16550a"; + reg = <0x1e787000 0x1000>; + reg-shift = <2>; + interrupts = <10>; + clocks = <&clk_uart>; + no-loopback-test; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 21c780fab761..eb4f1ac96271 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -234,6 +234,15 @@ }; }; + shdwc@f8048010 { + atmel,shdwc-debouncer = <976>; + + input@0 { + reg = <0>; + atmel,wakeup-type = "low"; + }; + }; + watchdog@f8048040 { status = "okay"; }; diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts index 79aec55e1ebc..6a366ee952a8 100644 --- a/arch/arm/boot/dts/at91-vinco.dts +++ b/arch/arm/boot/dts/at91-vinco.dts @@ -118,7 +118,7 @@ ethernet-phy@1 { reg = <0x1>; - reset-gpios = <&pioE 8 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pioE 8 GPIO_ACTIVE_LOW>; interrupt-parent = <&pioB>; interrupts = <15 IRQ_TYPE_EDGE_FALLING>; }; @@ -162,7 +162,7 @@ reg = <0x1>; interrupt-parent = <&pioB>; interrupts = <31 IRQ_TYPE_EDGE_FALLING>; - reset-gpios = <&pioE 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pioE 6 GPIO_ACTIVE_LOW>; }; }; diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index af8b708ac312..8837b7e4292c 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -978,7 +978,7 @@ trng@fffcc000 { compatible = "atmel,at91sam9g45-trng"; - reg = <0xfffcc000 0x4000>; + reg = <0xfffcc000 0x100>; interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&trng_clk>; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 228614ffff44..35ff4e7a4aac 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -29,3 +29,7 @@ brcm,function = <BCM2835_FSEL_ALT0>; }; }; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index ddbbbbd42dda..306a84ee9898 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -22,3 +22,7 @@ brcm,function = <BCM2835_FSEL_ALT2>; }; }; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index ef5405025223..57d313b6afaf 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -29,3 +29,7 @@ brcm,function = <BCM2835_FSEL_ALT0>; }; }; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index 86f1f2f598a7..cf2774ec0834 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -22,3 +22,7 @@ brcm,function = <BCM2835_FSEL_ALT2>; }; }; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 4859e9d81b23..8b15f9c35643 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -16,3 +16,7 @@ &gpio { pinctrl-0 = <&gpioout &alt0 &alt3>; }; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index 76bdbcafab18..caf2707680c1 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -74,3 +74,12 @@ &usb { power-domains = <&power RPI_POWER_DOMAIN_USB>; }; + +&v3d { + power-domains = <&power RPI_POWER_DOMAIN_V3D>; +}; + +&hdmi { + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index b83b32639358..a78759e73710 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -3,6 +3,17 @@ / { compatible = "brcm,bcm2835"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,arm1176jzf-s"; + reg = <0x0>; + }; + }; + soc { ranges = <0x7e000000 0x20000000 0x02000000>; dma-ranges = <0x40000000 0x00000000 0x20000000>; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index ff946661bd13..c4743f42237b 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -33,3 +33,7 @@ brcm,function = <BCM2835_FSEL_ALT0>; }; }; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 8aaf193711bf..31cc2f2ef040 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -1,6 +1,7 @@ #include <dt-bindings/pinctrl/bcm2835.h> #include <dt-bindings/clock/bcm2835.h> #include <dt-bindings/clock/bcm2835-aux.h> +#include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi" /* This include file covers the common peripherals and configuration between @@ -153,6 +154,18 @@ status = "disabled"; }; + pixelvalve@7e206000 { + compatible = "brcm,bcm2835-pixelvalve0"; + reg = <0x7e206000 0x100>; + interrupts = <2 13>; /* pwa0 */ + }; + + pixelvalve@7e207000 { + compatible = "brcm,bcm2835-pixelvalve1"; + reg = <0x7e207000 0x100>; + interrupts = <2 14>; /* pwa1 */ + }; + aux: aux@0x7e215000 { compatible = "brcm,bcm2835-aux"; #clock-cells = <1>; @@ -206,6 +219,12 @@ status = "disabled"; }; + hvs@7e400000 { + compatible = "brcm,bcm2835-hvs"; + reg = <0x7e400000 0x6000>; + interrupts = <2 1>; + }; + i2c1: i2c@7e804000 { compatible = "brcm,bcm2835-i2c"; reg = <0x7e804000 0x1000>; @@ -226,11 +245,39 @@ status = "disabled"; }; + pixelvalve@7e807000 { + compatible = "brcm,bcm2835-pixelvalve2"; + reg = <0x7e807000 0x100>; + interrupts = <2 10>; /* pixelvalve */ + }; + + hdmi: hdmi@7e902000 { + compatible = "brcm,bcm2835-hdmi"; + reg = <0x7e902000 0x600>, + <0x7e808000 0x100>; + interrupts = <2 8>, <2 9>; + ddc = <&i2c2>; + clocks = <&clocks BCM2835_PLLH_PIX>, + <&clocks BCM2835_CLOCK_HSM>; + clock-names = "pixel", "hdmi"; + status = "disabled"; + }; + usb: usb@7e980000 { compatible = "brcm,bcm2835-usb"; reg = <0x7e980000 0x10000>; interrupts = <1 9>; }; + + v3d: v3d@7ec00000 { + compatible = "brcm,bcm2835-v3d"; + reg = <0x7ec00000 0x1000>; + interrupts = <1 10>; + }; + + vc4: gpu { + compatible = "brcm,bcm2835-vc4"; + }; }; clocks { diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts index 42dcdfb769b2..5087aa81efb1 100644 --- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -17,7 +17,7 @@ model = "Buffalo WZR-1750DHP (BCM4708)"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "console=ttyS0,115200 earlycon"; }; memory { @@ -139,3 +139,11 @@ &uart0 { status = "okay"; }; + +&usb2 { + vcc-gpio = <&chipcommon 9 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>; +}; diff --git a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts index f18e80e0b61d..1c7e53d60aa4 100644 --- a/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts +++ b/arch/arm/boot/dts/bcm4708-luxul-xwc-1000.dts @@ -17,7 +17,7 @@ model = "Luxul XWC-1000 (BCM4708)"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "console=ttyS0,115200 earlycon"; }; memory { @@ -59,3 +59,7 @@ &uart0 { status = "okay"; }; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index ca92bba6a8c5..1049ab108b32 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -17,24 +17,13 @@ model = "Netgear R6250 V1 (BCM4708)"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "console=ttyS0,115200 earlycon"; }; memory { reg = <0x00000000 0x08000000>; }; - axi@18000000 { - usb3@23000 { - reg = <0x00023000 0x1000>; - - #address-cells = <1>; - #size-cells = <1>; - - vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; - }; - }; - leds { compatible = "gpio-leds"; @@ -97,3 +86,7 @@ &uart0 { status = "okay"; }; + +&usb3 { + vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts index 64a5e8ab65e0..8b0c440b2e71 100644 --- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts +++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts @@ -17,7 +17,7 @@ model = "SmartRG SR400ac"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "console=ttyS0,115200 earlycon"; }; memory { @@ -122,3 +122,7 @@ &uart0 { status = "okay"; }; + +&spi_nor { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts index 38f0c00d1aca..a9c8defed4d3 100644 --- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -17,7 +17,7 @@ model = "Buffalo WZR-600DHP2 (BCM47081)"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "console=ttyS0,115200 earlycon"; }; memory { diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts index 2a92e8d5ab34..791d7225c733 100644 --- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts +++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts @@ -126,3 +126,8 @@ }; }; }; + + +&usb2 { + vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts index b52927c94e35..ca181516c28a 100644 --- a/arch/arm/boot/dts/bcm4709-netgear-r8000.dts +++ b/arch/arm/boot/dts/bcm4709-netgear-r8000.dts @@ -106,3 +106,11 @@ }; }; }; + +&usb2 { + vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +}; + +&usb3 { + vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts index 6c83538bc2d7..ace38efd2db3 100644 --- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts +++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts @@ -17,7 +17,7 @@ model = "D-Link DIR-885L"; chosen { - bootargs = "console=ttyS0,115200"; + bootargs = "console=ttyS0,115200 earlycon"; }; memory { @@ -109,3 +109,7 @@ status = "okay"; clock-frequency = <125000000>; }; + +&usb3 { + vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 65a1309bd6e2..7d4d29bf0ed3 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -18,6 +18,10 @@ / { interrupt-parent = <&gic>; + chosen { + stdout-path = &uart0; + }; + chipcommonA { compatible = "simple-bus"; ranges = <0x00000000 0x18000000 0x00001000>; @@ -207,6 +211,34 @@ gpio-controller; #gpio-cells = <2>; }; + + usb2: usb2@21000 { + reg = <0x00021000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + }; + + usb3: usb3@23000 { + reg = <0x00023000 0x1000>; + + #address-cells = <1>; + #size-cells = <1>; + }; + + spi@29000 { + reg = <0x00029000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + spi_nor: spi-nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + linux,part-probe = "ofpart", "bcm47xxpart"; + status = "disabled"; + }; + }; }; lcpll0: lcpll0@1800c100 { diff --git a/arch/arm/boot/dts/cros-adc-thermistors.dtsi b/arch/arm/boot/dts/cros-adc-thermistors.dtsi index acd4fe1833f2..ce7fca76b0d6 100644 --- a/arch/arm/boot/dts/cros-adc-thermistors.dtsi +++ b/arch/arm/boot/dts/cros-adc-thermistors.dtsi @@ -13,28 +13,28 @@ */ &adc { - ncp15wb473@3 { + thermistor3 { compatible = "murata,ncp15wb473"; pullup-uv = <1800000>; pullup-ohm = <47000>; pulldown-ohm = <0>; io-channels = <&adc 3>; }; - ncp15wb473@4 { + thermistor4 { compatible = "murata,ncp15wb473"; pullup-uv = <1800000>; pullup-ohm = <47000>; pulldown-ohm = <0>; io-channels = <&adc 4>; }; - ncp15wb473@5 { + thermistor5 { compatible = "murata,ncp15wb473"; pullup-uv = <1800000>; pullup-ohm = <47000>; pulldown-ohm = <0>; io-channels = <&adc 5>; }; - ncp15wb473@6 { + thermistor6 { compatible = "murata,ncp15wb473"; pullup-uv = <1800000>; pullup-ohm = <47000>; diff --git a/arch/arm/boot/dts/da850-enbw-cmc.dts b/arch/arm/boot/dts/da850-enbw-cmc.dts index 645549e14237..14dff3e188ed 100644 --- a/arch/arm/boot/dts/da850-enbw-cmc.dts +++ b/arch/arm/boot/dts/da850-enbw-cmc.dts @@ -16,14 +16,20 @@ compatible = "enbw,cmc", "ti,da850"; model = "EnBW CMC"; - soc { - serial0: serial@1c42000 { + soc@1c00000 { + serial0: serial@42000 { status = "okay"; }; - serial1: serial@1d0c000 { + serial1: serial@10c000 { status = "okay"; }; - serial2: serial@1d0d000 { + serial2: serial@10d000 { + status = "okay"; + }; + mdio: mdio@224000 { + status = "okay"; + }; + eth0: ethernet@220000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index ef061e9a2315..1a15db8e376b 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -14,8 +14,8 @@ compatible = "ti,da850-evm", "ti,da850"; model = "DA850/AM1808/OMAP-L138 EVM"; - soc { - pmx_core: pinmux@1c14120 { + soc@1c00000 { + pmx_core: pinmux@14120 { status = "okay"; mcasp0_pins: pinmux_mcasp0_pins { @@ -30,19 +30,19 @@ >; }; }; - serial0: serial@1c42000 { + serial0: serial@42000 { status = "okay"; }; - serial1: serial@1d0c000 { + serial1: serial@10c000 { status = "okay"; }; - serial2: serial@1d0d000 { + serial2: serial@10d000 { status = "okay"; }; - rtc0: rtc@1c23000 { + rtc0: rtc@23000 { status = "okay"; }; - i2c0: i2c@1c22000 { + i2c0: i2c@22000 { status = "okay"; clock-frequency = <100000>; pinctrl-names = "default"; @@ -66,17 +66,17 @@ }; }; - wdt: wdt@1c21000 { + wdt: wdt@21000 { status = "okay"; }; - mmc0: mmc@1c40000 { + mmc0: mmc@40000 { max-frequency = <50000000>; bus-width = <4>; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins>; }; - spi1: spi@1f0e000 { + spi1: spi@30e000 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi1_pins &spi1_cs0_pin>; @@ -116,18 +116,18 @@ }; }; }; - mdio: mdio@1e24000 { + mdio: mdio@224000 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mdio_pins>; bus_freq = <2200000>; }; - eth0: ethernet@1e20000 { + eth0: ethernet@220000 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mii_pins>; }; - gpio: gpio@1e26000 { + gpio: gpio@226000 { status = "okay"; }; }; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 226cda76e77c..25f0f8e6dde5 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -15,15 +15,15 @@ #address-cells = <1>; #size-cells = <1>; ranges; - intc: interrupt-controller { + intc: interrupt-controller@fffee000 { compatible = "ti,cp-intc"; interrupt-controller; #interrupt-cells = <1>; - ti,intc-size = <100>; + ti,intc-size = <101>; reg = <0xfffee000 0x2000>; }; }; - soc { + soc@1c00000 { compatible = "simple-bus"; model = "da850"; #address-cells = <1>; @@ -31,7 +31,7 @@ ranges = <0x0 0x01c00000 0x400000>; interrupt-parent = <&intc>; - pmx_core: pinmux@1c14120 { + pmx_core: pinmux@14120 { compatible = "pinctrl-single"; reg = <0x14120 0x50>; #address-cells = <1>; @@ -63,6 +63,12 @@ 0x10 0x00002200 0x0000ff00 >; }; + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,bits = < + /* I2C1_SDA, I2C1_SCL */ + 0x10 0x00440000 0x00ff0000 + >; + }; mmc0_pins: pinmux_mmc_pins { pinctrl-single,bits = < /* MMCSD0_DAT[3] MMCSD0_DAT[2] @@ -114,7 +120,19 @@ 0x4 0x00000004 0x0000000f >; }; - spi1_pins: pinmux_spi_pins { + spi0_pins: pinmux_spi0_pins { + pinctrl-single,bits = < + /* SIMO, SOMI, CLK */ + 0xc 0x00001101 0x0000ff0f + >; + }; + spi0_cs0_pin: pinmux_spi0_cs0 { + pinctrl-single,bits = < + /* CS0 */ + 0x10 0x00000010 0x000000f0 + >; + }; + spi1_pins: pinmux_spi1_pins { pinctrl-single,bits = < /* SIMO, SOMI, CLK */ 0x14 0x00110100 0x00ff0f00 @@ -150,7 +168,7 @@ }; }; - edma0: edma@01c00000 { + edma0: edma@0 { compatible = "ti,edma3-tpcc"; /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */ reg = <0x0 0x8000>; @@ -161,19 +179,19 @@ ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; }; - edma0_tptc0: tptc@01c08000 { + edma0_tptc0: tptc@8000 { compatible = "ti,edma3-tptc"; reg = <0x8000 0x400>; interrupts = <13>; interrupt-names = "edm3_tcerrint"; }; - edma0_tptc1: tptc@01c08400 { + edma0_tptc1: tptc@8400 { compatible = "ti,edma3-tptc"; reg = <0x8400 0x400>; interrupts = <32>; interrupt-names = "edm3_tcerrint"; }; - edma1: edma@01e30000 { + edma1: edma@230000 { compatible = "ti,edma3-tpcc"; /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */ reg = <0x230000 0x8000>; @@ -184,41 +202,41 @@ ti,tptcs = <&edma1_tptc0 7>; }; - edma1_tptc0: tptc@01e38000 { + edma1_tptc0: tptc@238000 { compatible = "ti,edma3-tptc"; reg = <0x238000 0x400>; interrupts = <95>; interrupt-names = "edm3_tcerrint"; }; - serial0: serial@1c42000 { + serial0: serial@42000 { compatible = "ns16550a"; reg = <0x42000 0x100>; reg-shift = <2>; interrupts = <25>; status = "disabled"; }; - serial1: serial@1d0c000 { + serial1: serial@10c000 { compatible = "ns16550a"; reg = <0x10c000 0x100>; reg-shift = <2>; interrupts = <53>; status = "disabled"; }; - serial2: serial@1d0d000 { + serial2: serial@10d000 { compatible = "ns16550a"; reg = <0x10d000 0x100>; reg-shift = <2>; interrupts = <61>; status = "disabled"; }; - rtc0: rtc@1c23000 { + rtc0: rtc@23000 { compatible = "ti,da830-rtc"; reg = <0x23000 0x1000>; interrupts = <19 19>; status = "disabled"; }; - i2c0: i2c@1c22000 { + i2c0: i2c@22000 { compatible = "ti,davinci-i2c"; reg = <0x22000 0x1000>; interrupts = <15>; @@ -226,12 +244,20 @@ #size-cells = <0>; status = "disabled"; }; - wdt: wdt@1c21000 { + i2c1: i2c@228000 { + compatible = "ti,davinci-i2c"; + reg = <0x228000 0x1000>; + interrupts = <51>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + wdt: wdt@21000 { compatible = "ti,davinci-wdt"; reg = <0x21000 0x1000>; status = "disabled"; }; - mmc0: mmc@1c40000 { + mmc0: mmc@40000 { compatible = "ti,da830-mmc"; reg = <0x40000 0x1000>; interrupts = <16>; @@ -239,7 +265,7 @@ dma-names = "rx", "tx"; status = "disabled"; }; - mmc1: mmc@1e1b000 { + mmc1: mmc@21b000 { compatible = "ti,da830-mmc"; reg = <0x21b000 0x1000>; interrupts = <72>; @@ -247,37 +273,47 @@ dma-names = "rx", "tx"; status = "disabled"; }; - ehrpwm0: ehrpwm@01f00000 { + ehrpwm0: pwm@300000 { compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; status = "disabled"; }; - ehrpwm1: ehrpwm@01f02000 { + ehrpwm1: pwm@302000 { compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; status = "disabled"; }; - ecap0: ecap@01f06000 { + ecap0: ecap@306000 { compatible = "ti,da850-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x306000 0x80>; status = "disabled"; }; - ecap1: ecap@01f07000 { + ecap1: ecap@307000 { compatible = "ti,da850-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x307000 0x80>; status = "disabled"; }; - ecap2: ecap@01f08000 { + ecap2: ecap@308000 { compatible = "ti,da850-ecap", "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x308000 0x80>; status = "disabled"; }; - spi1: spi@1f0e000 { + spi0: spi@41000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "ti,da830-spi"; + reg = <0x41000 0x1000>; + num-cs = <6>; + ti,davinci-spi-intr-line = <1>; + interrupts = <20>; + status = "disabled"; + }; + spi1: spi@30e000 { #address-cells = <1>; #size-cells = <0>; compatible = "ti,da830-spi"; @@ -289,13 +325,14 @@ dma-names = "rx", "tx"; status = "disabled"; }; - mdio: mdio@1e24000 { + mdio: mdio@224000 { compatible = "ti,davinci_mdio"; #address-cells = <1>; #size-cells = <0>; reg = <0x224000 0x1000>; + status = "disabled"; }; - eth0: ethernet@1e20000 { + eth0: ethernet@220000 { compatible = "ti,davinci-dm6467-emac"; reg = <0x220000 0x4000>; ti,davinci-ctrl-reg-offset = <0x3000>; @@ -308,10 +345,12 @@ 35 36 >; + status = "disabled"; }; - gpio: gpio@1e26000 { + gpio: gpio@226000 { compatible = "ti,dm6441-gpio"; gpio-controller; + #gpio-cells = <2>; reg = <0x226000 0x1000>; interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH @@ -323,7 +362,7 @@ status = "disabled"; }; - mcasp0: mcasp@01d00000 { + mcasp0: mcasp@100000 { compatible = "ti,da830-mcasp-audio"; reg = <0x100000 0x2000>, <0x102000 0x400000>; diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi index 792a64ee0df7..c4671af0a28d 100644 --- a/arch/arm/boot/dts/dm814x-clocks.dtsi +++ b/arch/arm/boot/dts/dm814x-clocks.dtsi @@ -156,7 +156,7 @@ }; &pllss_clocks { - timer1_fck: timer1_fck { + timer1_fck: timer1_fck@2e0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck @@ -165,7 +165,7 @@ reg = <0x2e0>; }; - timer2_fck: timer2_fck { + timer2_fck: timer2_fck@2e0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck @@ -192,7 +192,7 @@ clock-frequency = <125000000>; }; - sysclk18_ck: sysclk18_ck { + sysclk18_ck: sysclk18_ck@2f0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&rtcosc_ck>, <&rtcdivider_ck>; @@ -202,7 +202,7 @@ }; &scm_clocks { - devosc_ck: devosc_ck { + devosc_ck: devosc_ck@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_20000000_ck>, <&virt_19200000_ck>; @@ -259,7 +259,7 @@ clock-div = <1>; }; - mpu_clksrc_ck: mpu_clksrc_ck { + mpu_clksrc_ck: mpu_clksrc_ck@40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&devosc_ck>, <&rtcdivider_ck>; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 4a6ce8c8bf8f..d4537dc61497 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -568,6 +568,8 @@ #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; }; }; diff --git a/arch/arm/boot/dts/dm816x-clocks.dtsi b/arch/arm/boot/dts/dm816x-clocks.dtsi index 50d9d338fbe9..51865eb84a80 100644 --- a/arch/arm/boot/dts/dm816x-clocks.dtsi +++ b/arch/arm/boot/dts/dm816x-clocks.dtsi @@ -86,7 +86,7 @@ /* 0x48180000 */ &prcm_clocks { - clkout_pre_ck: clkout_pre_ck { + clkout_pre_ck: clkout_pre_ck@100 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 @@ -94,7 +94,7 @@ reg = <0x100>; }; - clkout_div_ck: clkout_div_ck { + clkout_div_ck: clkout_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&clkout_pre_ck>; @@ -103,7 +103,7 @@ reg = <0x100>; }; - clkout_ck: clkout_ck { + clkout_ck: clkout_ck@100 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkout_div_ck>; @@ -112,7 +112,7 @@ }; /* CM_DPLL clocks p1795 */ - sysclk1_ck: sysclk1_ck { + sysclk1_ck: sysclk1_ck@300 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&main_fapll 1>; @@ -120,7 +120,7 @@ reg = <0x0300>; }; - sysclk2_ck: sysclk2_ck { + sysclk2_ck: sysclk2_ck@304 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&main_fapll 2>; @@ -128,7 +128,7 @@ reg = <0x0304>; }; - sysclk3_ck: sysclk3_ck { + sysclk3_ck: sysclk3_ck@308 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&main_fapll 3>; @@ -136,7 +136,7 @@ reg = <0x0308>; }; - sysclk4_ck: sysclk4_ck { + sysclk4_ck: sysclk4_ck@30c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&main_fapll 4>; @@ -144,7 +144,7 @@ reg = <0x030c>; }; - sysclk5_ck: sysclk5_ck { + sysclk5_ck: sysclk5_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sysclk4_ck>; @@ -152,7 +152,7 @@ reg = <0x0310>; }; - sysclk6_ck: sysclk6_ck { + sysclk6_ck: sysclk6_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&main_fapll 4>; @@ -160,7 +160,7 @@ reg = <0x0314>; }; - sysclk10_ck: sysclk10_ck { + sysclk10_ck: sysclk10_ck@324 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&ddr_fapll 2>; @@ -168,7 +168,7 @@ reg = <0x0324>; }; - sysclk24_ck: sysclk24_ck { + sysclk24_ck: sysclk24_ck@3b4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&main_fapll 5>; @@ -176,7 +176,7 @@ reg = <0x03b4>; }; - mpu_ck: mpu_ck { + mpu_ck: mpu_ck@15dc { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sysclk2_ck>; @@ -184,7 +184,7 @@ reg = <0x15dc>; }; - audio_pll_a_ck: audio_pll_a_ck { + audio_pll_a_ck: audio_pll_a_ck@35c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&audio_fapll 1>; @@ -192,56 +192,56 @@ reg = <0x035c>; }; - sysclk18_ck: sysclk18_ck { + sysclk18_ck: sysclk18_ck@378 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; reg = <0x0378>; }; - timer1_fck: timer1_fck { + timer1_fck: timer1_fck@390 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; reg = <0x0390>; }; - timer2_fck: timer2_fck { + timer2_fck: timer2_fck@394 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; reg = <0x0394>; }; - timer3_fck: timer3_fck { + timer3_fck: timer3_fck@398 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; reg = <0x0398>; }; - timer4_fck: timer4_fck { + timer4_fck: timer4_fck@39c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; reg = <0x039c>; }; - timer5_fck: timer5_fck { + timer5_fck: timer5_fck@3a0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; reg = <0x03a0>; }; - timer6_fck: timer6_fck { + timer6_fck: timer6_fck@3a4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; reg = <0x03a4>; }; - timer7_fck: timer7_fck { + timer7_fck: timer7_fck@3a8 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index d9309a016117..44e39c743b53 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -185,6 +185,8 @@ gpmc,num-waitpins = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; i2c1: i2c@48028000 { diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index d9b87236019d..bafcfac067ec 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -33,6 +33,7 @@ evm_3v3_sw: fixedregulator-evm_3v3_sw { compatible = "regulator-fixed"; regulator-name = "evm_3v3_sw"; + vin-supply = <&sysen1>; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; @@ -64,10 +65,11 @@ regulator-always-on; regulator-boot-on; enable-active-high; + vin-supply = <&sysen2>; gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; }; - sound0: sound@0 { + sound0: sound0 { compatible = "simple-audio-card"; simple-audio-card,name = "DRA7xx-EVM"; simple-audio-card,widgets = @@ -224,21 +226,6 @@ >; }; - qspi1_pins: pinmux_qspi1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x344c, PIN_INPUT | MUX_MODE1) /* gpmc_a3.qspi1_cs2 */ - DRA7XX_CORE_IOPAD(0x3450, PIN_INPUT | MUX_MODE1) /* gpmc_a4.qspi1_cs3 */ - DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ - DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ - DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ - DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ - DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ - DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ - DRA7XX_CORE_IOPAD(0x34b8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ - DRA7XX_CORE_IOPAD(0x34bc, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs3.qspi1_cs1 */ - >; - }; - usb1_pins: pinmux_usb1_pins { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ @@ -254,8 +241,9 @@ nand_flash_x16: nand_flash_x16 { /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch * So NAND flash requires following switch settings: - * SW5.9 (GPMC_WPN) = LOW - * SW5.1 (NAND_BOOTn) = HIGH */ + * SW5.1 (NAND_BOOTn) = ON (LOW) + * SW5.9 (GPMC_WPN) = OFF (HIGH) + */ pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ @@ -428,7 +416,7 @@ /* VDD_DSPEVE */ regulator-name = "smps45"; regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1150000>; + regulator-max-microvolt = <1250000>; regulator-always-on; regulator-boot-on; }; @@ -446,7 +434,7 @@ /* CORE_VDD */ regulator-name = "smps7"; regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1060000>; + regulator-max-microvolt = <1150000>; regulator-always-on; regulator-boot-on; }; @@ -523,12 +511,37 @@ regulator-max-microvolt = <3300000>; regulator-boot-on; }; + + /* REGEN1 is unused */ + + regen2: regen2 { + /* Needed for PMIC internal resources */ + regulator-name = "regen2"; + regulator-boot-on; + regulator-always-on; + }; + + /* REGEN3 is unused */ + + sysen1: sysen1 { + /* PMIC_REGEN_3V3 */ + regulator-name = "sysen1"; + regulator-boot-on; + regulator-always-on; + }; + + sysen2: sysen2 { + /* PMIC_REGEN_DDR */ + regulator-name = "sysen2"; + regulator-boot-on; + regulator-always-on; + }; }; }; }; pcf_lcd: gpio@20 { - compatible = "nxp,pcf8575"; + compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; @@ -539,7 +552,7 @@ }; pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575"; + compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x21>; lines-initial-states = <0x1408>; gpio-controller; @@ -573,7 +586,7 @@ clock-frequency = <400000>; pcf_hdmi: gpio@26 { - compatible = "nxp,pcf8575"; + compatible = "ti,pcf8575", "nxp,pcf8575"; reg = <0x26>; gpio-controller; #gpio-cells = <2>; @@ -650,18 +663,14 @@ &qspi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_pins>; - spi-max-frequency = <48000000>; + spi-max-frequency = <64000000>; m25p80@0 { compatible = "s25fl256s1"; - spi-max-frequency = <48000000>; + spi-max-frequency = <64000000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; #address-cells = <1>; #size-cells = <1>; @@ -748,6 +757,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <16>; @@ -904,6 +914,8 @@ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1 2 0 0 >; + tx-num-evt = <32>; + rx-num-evt = <32>; }; &mailbox5 { diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 13ac88279427..e0074014385a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -123,7 +123,7 @@ #size-cells = <1>; ranges = <0 0x0 0x1400>; - pbias_regulator: pbias_regulator { + pbias_regulator: pbias_regulator@e00 { compatible = "ti,pbias-dra7", "ti,pbias-omap"; reg = <0xe00 0x4>; syscon = <&scm_conf>; @@ -161,6 +161,24 @@ compatible = "syscon"; reg = <0x1c24 0x0024>; }; + + sdma_xbar: dma-router@b78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0xb78 0xfc>; + #dma-cells = <1>; + dma-requests = <205>; + ti,dma-safe-map = <0>; + dma-masters = <&sdma>; + }; + + edma_xbar: dma-router@c78 { + compatible = "ti,dra7-dma-crossbar"; + reg = <0xc78 0x7c>; + #dma-cells = <2>; + dma-requests = <204>; + ti,dma-safe-map = <0>; + dma-masters = <&edma>; + }; }; cm_core_aon: cm_core_aon@5000 { @@ -315,13 +333,43 @@ dma-requests = <127>; }; - sdma_xbar: dma-router@4a002b78 { - compatible = "ti,dra7-dma-crossbar"; - reg = <0x4a002b78 0xfc>; - #dma-cells = <1>; - dma-requests = <205>; - ti,dma-safe-map = <0>; - dma-masters = <&sdma>; + edma: edma@43300000 { + compatible = "ti,edma3-tpcc"; + ti,hwmods = "tpcc"; + reg = <0x43300000 0x100000>; + reg-names = "edma3_cc"; + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_ccint", "emda3_mperr", + "edma3_ccerrint"; + dma-requests = <64>; + #dma-cells = <2>; + + ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; + + /* + * memcpy is disabled, can be enabled with: + * ti,edma-memcpy-channels = <20 21>; + * for example. Note that these channels need to be + * masked in the xbar as well. + */ + }; + + edma_tptc0: tptc@43400000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc0"; + reg = <0x43400000 0x100000>; + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_tcerrint"; + }; + + edma_tptc1: tptc@43500000 { + compatible = "ti,edma3-tptc"; + ti,hwmods = "tptc1"; + reg = <0x43500000 0x100000>; + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma3_tcerrint"; }; gpio1: gpio@4ae10000 { @@ -773,12 +821,20 @@ ti,hwmods = "timer11"; }; + timer12: timer@4ae20000 { + compatible = "ti,omap5430-timer"; + reg = <0x4ae20000 0x80>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "timer12"; + ti,timer-alwon; + ti,timer-secure; + }; + timer13: timer@48828000 { compatible = "ti,omap5430-timer"; reg = <0x48828000 0x80>; interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer13"; - status = "disabled"; }; timer14: timer@4882a000 { @@ -786,7 +842,6 @@ reg = <0x4882a000 0x80>; interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer14"; - status = "disabled"; }; timer15: timer@4882c000 { @@ -794,7 +849,6 @@ reg = <0x4882c000 0x80>; interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer15"; - status = "disabled"; }; timer16: timer@4882e000 { @@ -802,7 +856,6 @@ reg = <0x4882e000 0x80>; interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "timer16"; - status = "disabled"; }; wdt2: wdt@4ae14000 { @@ -1404,6 +1457,8 @@ #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; status = "disabled"; }; @@ -1418,21 +1473,136 @@ status = "disabled"; }; + mcasp1: mcasp@48460000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp1"; + reg = <0x48460000 0x2000>, + <0x45800000 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>, + <&mcasp1_ahclkr_mux>; + clock-names = "fck", "ahclkx", "ahclkr"; + status = "disabled"; + }; + + mcasp2: mcasp@48464000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp2"; + reg = <0x48464000 0x2000>, + <0x45c00000 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>, + <&mcasp2_ahclkr_mux>; + clock-names = "fck", "ahclkx", "ahclkr"; + status = "disabled"; + }; + mcasp3: mcasp@48468000 { compatible = "ti,dra7-mcasp-audio"; ti,hwmods = "mcasp3"; - reg = <0x48468000 0x2000>; - reg-names = "mpu"; + reg = <0x48468000 0x2000>, + <0x46000000 0x1000>; + reg-names = "mpu","dat"; interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "tx", "rx"; - dmas = <&sdma_xbar 133>, <&sdma_xbar 132>; + dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; dma-names = "tx", "rx"; clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>; clock-names = "fck", "ahclkx"; status = "disabled"; }; + mcasp4: mcasp@4846c000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp4"; + reg = <0x4846c000 0x2000>, + <0x48436000 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + + mcasp5: mcasp@48470000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp5"; + reg = <0x48470000 0x2000>, + <0x4843a000 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + + mcasp6: mcasp@48474000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp6"; + reg = <0x48474000 0x2000>, + <0x4844c000 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + + mcasp7: mcasp@48478000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp7"; + reg = <0x48478000 0x2000>, + <0x48450000 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + + mcasp8: mcasp@4847c000 { + compatible = "ti,dra7-mcasp-audio"; + ti,hwmods = "mcasp8"; + reg = <0x4847c000 0x2000>, + <0x48454000 0x1000>; + reg-names = "mpu","dat"; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tx", "rx"; + dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; + dma-names = "tx", "rx"; + clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>; + clock-names = "fck", "ahclkx"; + status = "disabled"; + }; + crossbar_mpu: crossbar@4a002a48 { compatible = "ti,irq-crossbar"; reg = <0x4a002a48 0x130>; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi new file mode 100644 index 000000000000..093538ea5b5f --- /dev/null +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -0,0 +1,817 @@ +/* + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra72x.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clk/ti-dra7-atl.h> + +/ { + compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; + + aliases { + display0 = &hdmi0; + }; + + evm_3v3: fixedregulator-evm_3v3 { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + aic_dvdd: fixedregulator-aic_dvdd { + /* TPS77018DBVT */ + compatible = "regulator-fixed"; + regulator-name = "aic_dvdd"; + vin-supply = <&evm_3v3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + evm_3v3_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb1: extcon_usb1 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; + }; + + extcon_usb2: extcon_usb2 { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + pinctrl-names = "default"; + pinctrl-0 = <&tpd12s015_pins>; + + gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ + <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + sound0: sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "DRA7xx-EVM"; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Out", + "Microphone", "Mic Jack", + "Line", "Line In"; + simple-audio-card,routing = + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE1L", "Line In", + "LINE1R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + sound0_master: simple-audio-card,cpu { + sound-dai = <&mcasp3>; + system-clock-frequency = <5644800>; + }; + + simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + clocks = <&atl_clkin2_ck>; + }; + }; +}; + +&dra7_pmx_core { + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + >; + }; + + i2c5_pins: pinmux_i2c5_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ + DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ + >; + }; + + i2c5_pins: pinmux_i2c5_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ + DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ + >; + }; + + nand_default: nand_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ + DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ + DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ + DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ + DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ + DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ + DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ + DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ + DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ + DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ + DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ + DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ + DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ + DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ + DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ + DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ + DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ + DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ + DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ + DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ + DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ + DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ + >; + }; + + usb2_pins: pinmux_usb2_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ + >; + }; + + tps65917_pins_default: tps65917_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ + >; + }; + + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + dcan1_pins_default: dcan1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ + DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1_pins_sleep { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ + DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ + >; + }; + + hdmi_pins: pinmux_hdmi_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ + DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ + >; + }; + + tpd12s015_pins: pinmux_tpd12s015_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ + >; + }; + + atl_pins: pinmux_atl_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ + DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ + >; + }; + + mcasp3_pins: pinmux_mcasp3_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ + DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ + DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ + DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ + >; + }; + + mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15) + >; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + tps65917: tps65917@58 { + compatible = "ti,tps65917"; + reg = <0x58>; + + pinctrl-names = "default"; + pinctrl-0 = <&tps65917_pins_default>; + + interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ + interrupt-controller; + #interrupt-cells = <2>; + + ti,system-power-controller; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + tps65917_regulators: regulators { + smps1_reg: smps1 { + /* VDD_MPU */ + regulator-name = "smps1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps2_reg: smps2 { + /* VDD_CORE */ + regulator-name = "smps2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + smps3_reg: smps3 { + /* VDD_GPU IVA DSPEVE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDDS1V8 */ + regulator-name = "smps4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDD_DDR */ + regulator-name = "smps5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-allow-bypass; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; + }; + + pcf_gpio_21: gpio@21 { + compatible = "ti,pcf8575", "nxp,pcf8575"; + reg = <0x21>; + lines-initial-states = <0x1408>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + tlv320aic3106: tlv320aic3106@19 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x19>; + adc-settle-ms = <40>; + ai3x-micbias-vg = <1>; /* 2.0V */ + status = "okay"; + + /* Regulators */ + AVDD-supply = <&evm_3v3>; + IOVDD-supply = <&evm_3v3>; + DRVDD-supply = <&evm_3v3>; + DVDD-supply = <&aic_dvdd>; + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + + pcf_hdmi: pcf8575@26 { + compatible = "ti,pcf8575", "nxp,pcf8575"; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + /* + * initial state is used here to keep the mdio interface + * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and + * VIN2_S0 driven high otherwise Ethernet stops working + * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 + */ + lines-initial-states = <0x0f2b>; + + p1 { + /* vin6_sel_s0: high: VIN6, low: audio */ + gpio-hog; + gpios = <1 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "vin6_sel_s0"; + }; + }; +}; + +&uart1 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3e0>; +}; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_default>; + ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + /* To use NAND, DIP switch SW5 must be set like so: + * SW5.1 (NAND_SELn) = ON (LOW) + * SW5.9 (GPMC_WPN) = OFF (HIGH) + */ + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <80>; + gpmc,cs-wr-off-ns = <80>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <60>; + gpmc,adv-wr-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <50>; + gpmc,oe-on-ns = <4>; + gpmc,oe-off-ns = <40>; + gpmc,access-ns = <40>; + gpmc,wr-access-ns = <80>; + gpmc,rd-cycle-ns = <80>; + gpmc,wr-cycle-ns = <80>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x000020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000c0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001c0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x001e0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x0f600000>; + }; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldo4_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldo4_reg>; +}; + +&omap_dwc3_1 { + extcon = <&extcon_usb1>; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb1 { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; + +&usb2 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pins>; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + vmmc-supply = <&evm_3v3_sd>; + vmmc_aux-supply = <&ldo1_reg>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is a viable alternative + */ + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; + max-frequency = <192000000>; +}; + +&mmc2 { + /* SW5-3 in ON position */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&evm_3v3>; + bus-width = <8>; + ti,non-removable; + max-frequency = <192000000>; +}; + +&dra7_pmx_core { + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 2 */ + DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ + DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ + DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ + DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ + DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ + DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ + DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ + DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ + DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ + DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ + DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ + DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ + >; + + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 2 */ + DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ + DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) + DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) + >; + }; +}; + +&mac { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; + +&dcan1 { + status = "ok"; + pinctrl-names = "default", "sleep", "active"; + pinctrl-0 = <&dcan1_pins_sleep>; + pinctrl-1 = <&dcan1_pins_sleep>; + pinctrl-2 = <&dcan1_pins_default>; +}; + +&qspi { + status = "okay"; + + spi-max-frequency = <64000000>; + m25p80@0 { + compatible = "s25fl256s1"; + spi-max-frequency = <64000000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000010000>; + }; + partition@1 { + label = "QSPI.SPL.backup1"; + reg = <0x00010000 0x00010000>; + }; + partition@2 { + label = "QSPI.SPL.backup2"; + reg = <0x00020000 0x00010000>; + }; + partition@3 { + label = "QSPI.SPL.backup3"; + reg = <0x00030000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@5 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@6 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@7 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@8 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@9 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldo5_reg>; +}; + +&hdmi { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&atl { + pinctrl-names = "default"; + pinctrl-0 = <&atl_pins>; + + assigned-clocks = <&abe_dpll_sys_clk_mux>, + <&atl_gfclk_mux>, + <&dpll_abe_ck>, + <&dpll_abe_m2x2_ck>, + <&atl_clkin2_ck>; + assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; + assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; + + status = "okay"; + + atl2 { + bws = <DRA7_ATL_WS_MCASP2_FSX>; + aws = <DRA7_ATL_WS_MCASP3_FSX>; + }; +}; + +&mcasp3 { + #sound-dai-cells = <0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mcasp3_pins>; + pinctrl-1 = <&mcasp3_sleep_pins>; + + assigned-clocks = <&mcasp3_ahclkx_mux>; + assigned-clock-parents = <&atl_clkin2_ck>; + + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts new file mode 100644 index 000000000000..f9cfd3bb4dc2 --- /dev/null +++ b/arch/arm/boot/dts/dra72-evm-revc.dts @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include "dra72-evm-common.dtsi" +#include <dt-bindings/net/ti-dp83867.h> + +/ { + model = "TI DRA722 Rev C EVM"; + + memory { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ + }; +}; + +&tps65917_regulators { + ldo2_reg: ldo2 { + /* LDO2_OUT --> VDDA_1V8_PHY2 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&hdmi { + vdda-supply = <&ldo2_reg>; +}; + +&pcf_gpio_21 { + interrupt-parent = <&gpio3>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; +}; + +&mac { + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_LOW>, + <&pcf_hdmi 9 GPIO_ACTIVE_LOW>, /* P11 */ + <&pcf_hdmi 10 GPIO_ACTIVE_LOW>; /* P12 */ + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rgmii-id"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + dp83867_0: ethernet-phy@2 { + reg = <2>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + }; + + dp83867_1: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + }; +}; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 6affe2d137da..cc1d32ca4a8a 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -1,694 +1,40 @@ /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/dts-v1/; - -#include "dra72x.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/clk/ti-dra7-atl.h> - +#include "dra72-evm-common.dtsi" / { model = "TI DRA722"; - compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; memory { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ }; +}; - aliases { - display0 = &hdmi0; - }; - - evm_3v3: fixedregulator-evm_3v3 { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - /* TPS77018DBVT */ - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd"; - vin-supply = <&evm_3v3>; +&tps65917_regulators { + ldo2_reg: ldo2 { + /* LDO2_OUT --> TP1017 (UNUSED) */ + regulator-name = "ldo2"; regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - evm_3v3_sd: fixedregulator-sd { - compatible = "regulator-fixed"; - regulator-name = "evm_3v3_sd"; - regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb1: extcon_usb1 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; - }; - - extcon_usb2: extcon_usb2 { - compatible = "linux,extcon-usb-gpio"; - id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - - gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ - <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - sound0: sound@0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "DRA7xx-EVM"; - simple-audio-card,widgets = - "Headphone", "Headphone Jack", - "Line", "Line Out", - "Microphone", "Mic Jack", - "Line", "Line In"; - simple-audio-card,routing = - "Headphone Jack", "HPLOUT", - "Headphone Jack", "HPROUT", - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC3L", "Mic Jack", - "MIC3R", "Mic Jack", - "Mic Jack", "Mic Bias", - "LINE1L", "Line In", - "LINE1R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - sound0_master: simple-audio-card,cpu { - sound-dai = <&mcasp3>; - system-clock-frequency = <5644800>; - }; - - simple-audio-card,codec { - sound-dai = <&tlv320aic3106>; - clocks = <&atl_clkin2_ck>; - }; - }; -}; - -&dra7_pmx_core { - i2c1_pins: pinmux_i2c1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - i2c5_pins: pinmux_i2c5_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36b4, PIN_INPUT | MUX_MODE10) /* mcasp1_axr0.i2c5_sda */ - DRA7XX_CORE_IOPAD(0x36b8, PIN_INPUT | MUX_MODE10) /* mcasp1_axr1.i2c5_scl */ - >; - }; - - nand_default: nand_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ - DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ - DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ - DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ - DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ - DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ - DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ - DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ - DRA7XX_CORE_IOPAD(0x3420, PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ - DRA7XX_CORE_IOPAD(0x3424, PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ - DRA7XX_CORE_IOPAD(0x3428, PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ - DRA7XX_CORE_IOPAD(0x342c, PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ - DRA7XX_CORE_IOPAD(0x3430, PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ - DRA7XX_CORE_IOPAD(0x3434, PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ - DRA7XX_CORE_IOPAD(0x3438, PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ - DRA7XX_CORE_IOPAD(0x343c, PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ - DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ - DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ - DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ - DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ - DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ - DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - usb2_pins: pinmux_usb2_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3684, PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ - >; - }; - - tps65917_pins_default: tps65917_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ - >; - }; - - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; - - dcan1_pins_default: dcan1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ - DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ - >; - }; - - dcan1_pins_sleep: dcan1_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ - DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ - >; - }; - - qspi1_pins: pinmux_qspi1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3474, PIN_OUTPUT | MUX_MODE1) /* gpmc_a13.qspi1_rtclk */ - DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MUX_MODE1) /* gpmc_a14.qspi1_d3 */ - DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MUX_MODE1) /* gpmc_a15.qspi1_d2 */ - DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */ - DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MUX_MODE1) /* gpmc_a17.qspi1_d0 */ - DRA7XX_CORE_IOPAD(0x3488, PIN_OUTPUT | MUX_MODE1) /* qpmc_a18.qspi1_sclk */ - DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MUX_MODE1) /* gpmc_cs2.qspi1_cs0 */ - >; - }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ - >; - }; - - atl_pins: pinmux_atl_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3698, PIN_OUTPUT | MUX_MODE5) /* xref_clk1.atl_clk1 */ - DRA7XX_CORE_IOPAD(0x369c, PIN_OUTPUT | MUX_MODE5) /* xref_clk2.atl_clk2 */ - >; - }; - - mcasp3_pins: pinmux_mcasp3_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1 */ - >; - }; - - mcasp3_sleep_pins: pinmux_mcasp3_sleep_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT_PULLDOWN | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE15) - >; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - - tps65917: tps65917@58 { - compatible = "ti,tps65917"; - reg = <0x58>; - - pinctrl-names = "default"; - pinctrl-0 = <&tps65917_pins_default>; - - interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ - interrupt-controller; - #interrupt-cells = <2>; - - ti,system-power-controller; - - tps65917_pmic { - compatible = "ti,tps65917-pmic"; - - regulators { - smps1_reg: smps1 { - /* VDD_MPU */ - regulator-name = "smps1"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps2_reg: smps2 { - /* VDD_CORE */ - regulator-name = "smps2"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1060000>; - regulator-boot-on; - regulator-always-on; - }; - - smps3_reg: smps3 { - /* VDD_GPU IVA DSPEVE */ - regulator-name = "smps3"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1250000>; - regulator-boot-on; - regulator-always-on; - }; - - smps4_reg: smps4 { - /* VDDS1V8 */ - regulator-name = "smps4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - smps5_reg: smps5 { - /* VDD_DDR */ - regulator-name = "smps5"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo1_reg: ldo1 { - /* LDO1_OUT --> SDIO */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-bypass; - }; - - ldo2_reg: ldo2 { - /* LDO2_OUT --> TP1017 (UNUSED) */ - regulator-name = "ldo2"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-allow-bypass; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHY */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo5_reg: ldo5 { - /* VDDA_1V8_PLL */ - regulator-name = "ldo5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldo4"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - }; - }; - - tps65917_power_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps65917>; - interrupts = <1 IRQ_TYPE_NONE>; - wakeup-source; - ti,palmas-long-press-seconds = <6>; - }; - }; - - pcf_gpio_21: gpio@21 { - compatible = "ti,pcf8575"; - reg = <0x21>; - lines-initial-states = <0x1408>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&gpio6>; - interrupts = <11 IRQ_TYPE_EDGE_FALLING>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - tlv320aic3106: tlv320aic3106@19 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3106"; - reg = <0x19>; - adc-settle-ms = <40>; - ai3x-micbias-vg = <1>; /* 2.0V */ - status = "okay"; - - /* Regulators */ - AVDD-supply = <&evm_3v3>; - IOVDD-supply = <&evm_3v3>; - DRVDD-supply = <&evm_3v3>; - DVDD-supply = <&aic_dvdd>; + regulator-allow-bypass; }; }; -&i2c5 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - clock-frequency = <400000>; - - pcf_hdmi: pcf8575@26 { - compatible = "nxp,pcf8575"; - reg = <0x26>; - gpio-controller; - #gpio-cells = <2>; - /* - * initial state is used here to keep the mdio interface - * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and - * VIN2_S0 driven high otherwise Ethernet stops working - * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 - */ - lines-initial-states = <0x0f2b>; - - p1 { - /* vin6_sel_s0: high: VIN6, low: audio */ - gpio-hog; - gpios = <1 GPIO_ACTIVE_HIGH>; - output-low; - line-name = "vin6_sel_s0"; - }; - }; -}; - -&uart1 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3e0>; -}; - -&elm { - status = "okay"; -}; - -&gpmc { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_default>; - ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ - nand@0,0 { - /* To use NAND, DIP switch SW5 must be set like so: - * SW5.1 (NAND_SELn) = ON (LOW) - * SW5.9 (GPMC_WPN) = OFF (HIGH) - */ - compatible = "ti,omap2-nand"; - reg = <0 0 4>; /* device IO registers */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - ti,nand-ecc-opt = "bch8"; - ti,elm-id = <&elm>; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <80>; - gpmc,cs-wr-off-ns = <80>; - gpmc,adv-on-ns = <0>; - gpmc,adv-rd-off-ns = <60>; - gpmc,adv-wr-off-ns = <60>; - gpmc,we-on-ns = <10>; - gpmc,we-off-ns = <50>; - gpmc,oe-on-ns = <4>; - gpmc,oe-off-ns = <40>; - gpmc,access-ns = <40>; - gpmc,wr-access-ns = <80>; - gpmc,rd-cycle-ns = <80>; - gpmc,wr-cycle-ns = <80>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-data-mux-bus-ns = <0>; - /* MTD partition table */ - /* All SPL-* partitions are sized to minimal length - * which can be independently programmable. For - * NAND flash this is equal to size of erase-block */ - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "NAND.SPL"; - reg = <0x00000000 0x000020000>; - }; - partition@1 { - label = "NAND.SPL.backup1"; - reg = <0x00020000 0x00020000>; - }; - partition@2 { - label = "NAND.SPL.backup2"; - reg = <0x00040000 0x00020000>; - }; - partition@3 { - label = "NAND.SPL.backup3"; - reg = <0x00060000 0x00020000>; - }; - partition@4 { - label = "NAND.u-boot-spl-os"; - reg = <0x00080000 0x00040000>; - }; - partition@5 { - label = "NAND.u-boot"; - reg = <0x000c0000 0x00100000>; - }; - partition@6 { - label = "NAND.u-boot-env"; - reg = <0x001c0000 0x00020000>; - }; - partition@7 { - label = "NAND.u-boot-env.backup1"; - reg = <0x001e0000 0x00020000>; - }; - partition@8 { - label = "NAND.kernel"; - reg = <0x00200000 0x00800000>; - }; - partition@9 { - label = "NAND.file-system"; - reg = <0x00a00000 0x0f600000>; - }; - }; -}; - -&usb2_phy1 { - phy-supply = <&ldo4_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldo4_reg>; -}; - -&omap_dwc3_1 { - extcon = <&extcon_usb1>; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb1 { - dr_mode = "peripheral"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; -}; - -&usb2 { - dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb2_pins>; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - vmmc-supply = <&evm_3v3_sd>; - vmmc_aux-supply = <&ldo1_reg>; - bus-width = <4>; - /* - * SDCD signal is not being used here - using the fact that GPIO mode - * is a viable alternative - */ - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; - max-frequency = <192000000>; -}; - -&mmc2 { - /* SW5-3 in ON position */ - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; - - vmmc-supply = <&evm_3v3>; - bus-width = <8>; - ti,non-removable; - max-frequency = <192000000>; +&hdmi { + vdda-supply = <&ldo3_reg>; }; -&dra7_pmx_core { - cpsw_default: cpsw_default { - pinctrl-single,pins = < - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ - >; - - }; - - cpsw_sleep: cpsw_sleep { - pinctrl-single,pins = < - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, MUX_MODE15) - >; - }; - - davinci_mdio_default: davinci_mdio_default { - pinctrl-single,pins = < - /* MDIO */ - DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ - DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ - >; - }; - - davinci_mdio_sleep: davinci_mdio_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x363c, MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3640, MUX_MODE15) - >; - }; +&pcf_gpio_21 { + interrupt-parent = <&gpio6>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; }; &mac { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_default>; - pinctrl-1 = <&cpsw_sleep>; slaves = <1>; mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; }; @@ -697,158 +43,3 @@ phy_id = <&davinci_mdio>, <3>; phy-mode = "rgmii"; }; - -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_default>; - pinctrl-1 = <&davinci_mdio_sleep>; -}; - -&dcan1 { - status = "ok"; - pinctrl-names = "default", "sleep", "active"; - pinctrl-0 = <&dcan1_pins_sleep>; - pinctrl-1 = <&dcan1_pins_sleep>; - pinctrl-2 = <&dcan1_pins_default>; -}; - -&qspi { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi1_pins>; - - spi-max-frequency = <48000000>; - m25p80@0 { - compatible = "s25fl256s1"; - spi-max-frequency = <48000000>; - reg = <0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; - #address-cells = <1>; - #size-cells = <1>; - - /* MTD partition table. - * The ROM checks the first four physical blocks - * for a valid file to boot and the flash here is - * 64KiB block size. - */ - partition@0 { - label = "QSPI.SPL"; - reg = <0x00000000 0x000010000>; - }; - partition@1 { - label = "QSPI.SPL.backup1"; - reg = <0x00010000 0x00010000>; - }; - partition@2 { - label = "QSPI.SPL.backup2"; - reg = <0x00020000 0x00010000>; - }; - partition@3 { - label = "QSPI.SPL.backup3"; - reg = <0x00030000 0x00010000>; - }; - partition@4 { - label = "QSPI.u-boot"; - reg = <0x00040000 0x00100000>; - }; - partition@5 { - label = "QSPI.u-boot-spl-os"; - reg = <0x00140000 0x00080000>; - }; - partition@6 { - label = "QSPI.u-boot-env"; - reg = <0x001c0000 0x00010000>; - }; - partition@7 { - label = "QSPI.u-boot-env.backup1"; - reg = <0x001d0000 0x0010000>; - }; - partition@8 { - label = "QSPI.kernel"; - reg = <0x001e0000 0x0800000>; - }; - partition@9 { - label = "QSPI.file-system"; - reg = <0x009e0000 0x01620000>; - }; - }; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&ldo5_reg>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo3_reg>; - - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&atl { - pinctrl-names = "default"; - pinctrl-0 = <&atl_pins>; - - assigned-clocks = <&abe_dpll_sys_clk_mux>, - <&atl_gfclk_mux>, - <&dpll_abe_ck>, - <&dpll_abe_m2x2_ck>, - <&atl_clkin2_ck>; - assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; - assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; - - status = "okay"; - - atl2 { - bws = <DRA7_ATL_WS_MCASP2_FSX>; - aws = <DRA7_ATL_WS_MCASP3_FSX>; - }; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins>; - pinctrl-1 = <&mcasp3_sleep_pins>; - - assigned-clocks = <&mcasp3_ahclkx_mux>; - assigned-clock-parents = <&atl_clkin2_ck>; - - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializer */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; -}; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index ef2164a99d0f..8378b44ee567 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -196,7 +196,7 @@ clock-frequency = <0>; }; - dpll_abe_ck: dpll_abe_ck { + dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; @@ -209,7 +209,7 @@ clocks = <&dpll_abe_ck>; }; - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; @@ -220,7 +220,7 @@ ti,invert-autoidle-bit; }; - abe_clk: abe_clk { + abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; @@ -229,7 +229,7 @@ ti,index-power-of-two; }; - dpll_abe_m2_ck: dpll_abe_m2_ck { + dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_ck>; @@ -240,7 +240,7 @@ ti,invert-autoidle-bit; }; - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; @@ -251,7 +251,7 @@ ti,invert-autoidle-bit; }; - dpll_core_byp_mux: dpll_core_byp_mux { + dpll_core_byp_mux: dpll_core_byp_mux@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; @@ -259,7 +259,7 @@ reg = <0x012c>; }; - dpll_core_ck: dpll_core_ck { + dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; clocks = <&sys_clkin1>, <&dpll_core_byp_mux>; @@ -272,7 +272,7 @@ clocks = <&dpll_core_ck>; }; - dpll_core_h12x2_ck: dpll_core_h12x2_ck { + dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -291,14 +291,14 @@ clock-div = <1>; }; - dpll_mpu_ck: dpll_mpu_ck { + dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck { + dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; @@ -325,7 +325,7 @@ clock-div = <1>; }; - dpll_dsp_byp_mux: dpll_dsp_byp_mux { + dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>; @@ -333,14 +333,14 @@ reg = <0x0240>; }; - dpll_dsp_ck: dpll_dsp_ck { + dpll_dsp_ck: dpll_dsp_ck@234 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>; reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>; }; - dpll_dsp_m2_ck: dpll_dsp_m2_ck { + dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_ck>; @@ -359,7 +359,7 @@ clock-div = <1>; }; - dpll_iva_byp_mux: dpll_iva_byp_mux { + dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>; @@ -367,14 +367,14 @@ reg = <0x01ac>; }; - dpll_iva_ck: dpll_iva_ck { + dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>; reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>; }; - dpll_iva_m2_ck: dpll_iva_m2_ck { + dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_ck>; @@ -393,7 +393,7 @@ clock-div = <1>; }; - dpll_gpu_byp_mux: dpll_gpu_byp_mux { + dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; @@ -401,14 +401,14 @@ reg = <0x02e4>; }; - dpll_gpu_ck: dpll_gpu_ck { + dpll_gpu_ck: dpll_gpu_ck@2d8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>; reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>; }; - dpll_gpu_m2_ck: dpll_gpu_m2_ck { + dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gpu_ck>; @@ -419,7 +419,7 @@ ti,invert-autoidle-bit; }; - dpll_core_m2_ck: dpll_core_m2_ck { + dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_ck>; @@ -438,7 +438,7 @@ clock-div = <1>; }; - dpll_ddr_byp_mux: dpll_ddr_byp_mux { + dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; @@ -446,14 +446,14 @@ reg = <0x021c>; }; - dpll_ddr_ck: dpll_ddr_ck { + dpll_ddr_ck: dpll_ddr_ck@210 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>; reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>; }; - dpll_ddr_m2_ck: dpll_ddr_m2_ck { + dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_ck>; @@ -464,7 +464,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_byp_mux: dpll_gmac_byp_mux { + dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>; @@ -472,14 +472,14 @@ reg = <0x02b4>; }; - dpll_gmac_ck: dpll_gmac_ck { + dpll_gmac_ck: dpll_gmac_ck@2a8 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>; reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>; }; - dpll_gmac_m2_ck: dpll_gmac_m2_ck { + dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_ck>; @@ -538,7 +538,7 @@ clock-div = <1>; }; - dpll_eve_byp_mux: dpll_eve_byp_mux { + dpll_eve_byp_mux: dpll_eve_byp_mux@290 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>; @@ -546,14 +546,14 @@ reg = <0x0290>; }; - dpll_eve_ck: dpll_eve_ck { + dpll_eve_ck: dpll_eve_ck@284 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>; reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>; }; - dpll_eve_m2_ck: dpll_eve_m2_ck { + dpll_eve_m2_ck: dpll_eve_m2_ck@294 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_eve_ck>; @@ -572,7 +572,7 @@ clock-div = <1>; }; - dpll_core_h13x2_ck: dpll_core_h13x2_ck { + dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -583,7 +583,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h14x2_ck: dpll_core_h14x2_ck { + dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -594,7 +594,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h22x2_ck: dpll_core_h22x2_ck { + dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -605,7 +605,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h23x2_ck: dpll_core_h23x2_ck { + dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -616,7 +616,7 @@ ti,invert-autoidle-bit; }; - dpll_core_h24x2_ck: dpll_core_h24x2_ck { + dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -633,7 +633,7 @@ clocks = <&dpll_ddr_ck>; }; - dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck { + dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_x2_ck>; @@ -650,7 +650,7 @@ clocks = <&dpll_dsp_ck>; }; - dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck { + dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_x2_ck>; @@ -667,7 +667,7 @@ clocks = <&dpll_gmac_ck>; }; - dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck { + dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; @@ -678,7 +678,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck { + dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; @@ -689,7 +689,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck { + dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; @@ -700,7 +700,7 @@ ti,invert-autoidle-bit; }; - dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck { + dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_x2_ck>; @@ -735,7 +735,7 @@ clock-div = <1>; }; - l3_iclk_div: l3_iclk_div { + l3_iclk_div: l3_iclk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; ti,max-div = <2>; @@ -785,7 +785,7 @@ clock-div = <1>; }; - ipu1_gfclk_mux: ipu1_gfclk_mux { + ipu1_gfclk_mux: ipu1_gfclk_mux@520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>; @@ -793,7 +793,7 @@ reg = <0x0520>; }; - mcasp1_ahclkr_mux: mcasp1_ahclkr_mux { + mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -801,7 +801,7 @@ reg = <0x0550>; }; - mcasp1_ahclkx_mux: mcasp1_ahclkx_mux { + mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -809,7 +809,7 @@ reg = <0x0550>; }; - mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux { + mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; @@ -817,7 +817,7 @@ reg = <0x0550>; }; - timer5_gfclk_mux: timer5_gfclk_mux { + timer5_gfclk_mux: timer5_gfclk_mux@558 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; @@ -825,7 +825,7 @@ reg = <0x0558>; }; - timer6_gfclk_mux: timer6_gfclk_mux { + timer6_gfclk_mux: timer6_gfclk_mux@560 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; @@ -833,7 +833,7 @@ reg = <0x0560>; }; - timer7_gfclk_mux: timer7_gfclk_mux { + timer7_gfclk_mux: timer7_gfclk_mux@568 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; @@ -841,7 +841,7 @@ reg = <0x0568>; }; - timer8_gfclk_mux: timer8_gfclk_mux { + timer8_gfclk_mux: timer8_gfclk_mux@570 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>; @@ -849,7 +849,7 @@ reg = <0x0570>; }; - uart6_gfclk_mux: uart6_gfclk_mux { + uart6_gfclk_mux: uart6_gfclk_mux@580 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -864,7 +864,7 @@ }; }; &prm_clocks { - sys_clkin1: sys_clkin1 { + sys_clkin1: sys_clkin1@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; @@ -872,28 +872,28 @@ ti,index-starts-at-one; }; - abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux { + abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0118>; }; - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { + abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x0114>; }; - abe_dpll_clk_mux: abe_dpll_clk_mux { + abe_dpll_clk_mux: abe_dpll_clk_mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>; reg = <0x010c>; }; - abe_24m_fclk: abe_24m_fclk { + abe_24m_fclk: abe_24m_fclk@11c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; @@ -901,7 +901,7 @@ ti,dividers = <8>, <16>; }; - aess_fclk: aess_fclk { + aess_fclk: aess_fclk@178 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&abe_clk>; @@ -909,7 +909,7 @@ ti,max-div = <2>; }; - abe_giclk_div: abe_giclk_div { + abe_giclk_div: abe_giclk_div@174 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&aess_fclk>; @@ -917,7 +917,7 @@ ti,max-div = <2>; }; - abe_lp_clk_div: abe_lp_clk_div { + abe_lp_clk_div: abe_lp_clk_div@1d8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; @@ -925,7 +925,7 @@ ti,dividers = <16>, <32>; }; - abe_sys_clk_div: abe_sys_clk_div { + abe_sys_clk_div: abe_sys_clk_div@120 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; @@ -933,14 +933,14 @@ ti,max-div = <2>; }; - adc_gfclk_mux: adc_gfclk_mux { + adc_gfclk_mux: adc_gfclk_mux@1dc { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>; reg = <0x01dc>; }; - sys_clk1_dclk_div: sys_clk1_dclk_div { + sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; @@ -949,7 +949,7 @@ ti,index-power-of-two; }; - sys_clk2_dclk_div: sys_clk2_dclk_div { + sys_clk2_dclk_div: sys_clk2_dclk_div@1cc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin2>; @@ -958,7 +958,7 @@ ti,index-power-of-two; }; - per_abe_x1_dclk_div: per_abe_x1_dclk_div { + per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2_ck>; @@ -967,7 +967,7 @@ ti,index-power-of-two; }; - dsp_gclk_div: dsp_gclk_div { + dsp_gclk_div: dsp_gclk_div@18c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_dsp_m2_ck>; @@ -976,7 +976,7 @@ ti,index-power-of-two; }; - gpu_dclk: gpu_dclk { + gpu_dclk: gpu_dclk@1a0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gpu_m2_ck>; @@ -985,7 +985,7 @@ ti,index-power-of-two; }; - emif_phy_dclk_div: emif_phy_dclk_div { + emif_phy_dclk_div: emif_phy_dclk_div@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_ddr_m2_ck>; @@ -994,7 +994,7 @@ ti,index-power-of-two; }; - gmac_250m_dclk_div: gmac_250m_dclk_div { + gmac_250m_dclk_div: gmac_250m_dclk_div@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_m2_ck>; @@ -1003,7 +1003,7 @@ ti,index-power-of-two; }; - l3init_480m_dclk_div: l3init_480m_dclk_div { + l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>; @@ -1012,7 +1012,7 @@ ti,index-power-of-two; }; - usb_otg_dclk_div: usb_otg_dclk_div { + usb_otg_dclk_div: usb_otg_dclk_div@184 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&usb_otg_clkin_ck>; @@ -1021,7 +1021,7 @@ ti,index-power-of-two; }; - sata_dclk_div: sata_dclk_div { + sata_dclk_div: sata_dclk_div@1c0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; @@ -1030,7 +1030,7 @@ ti,index-power-of-two; }; - pcie2_dclk_div: pcie2_dclk_div { + pcie2_dclk_div: pcie2_dclk_div@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_m2_ck>; @@ -1039,7 +1039,7 @@ ti,index-power-of-two; }; - pcie_dclk_div: pcie_dclk_div { + pcie_dclk_div: pcie_dclk_div@1b4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&apll_pcie_m2_ck>; @@ -1048,7 +1048,7 @@ ti,index-power-of-two; }; - emu_dclk_div: emu_dclk_div { + emu_dclk_div: emu_dclk_div@194 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; @@ -1057,7 +1057,7 @@ ti,index-power-of-two; }; - secure_32k_dclk_div: secure_32k_dclk_div { + secure_32k_dclk_div: secure_32k_dclk_div@1c4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&secure_32k_clk_src_ck>; @@ -1066,21 +1066,21 @@ ti,index-power-of-two; }; - clkoutmux0_clk_mux: clkoutmux0_clk_mux { + clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x0158>; }; - clkoutmux1_clk_mux: clkoutmux1_clk_mux { + clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; reg = <0x015c>; }; - clkoutmux2_clk_mux: clkoutmux2_clk_mux { + clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>; @@ -1095,21 +1095,21 @@ clock-div = <2>; }; - eve_clk: eve_clk { + eve_clk: eve_clk@180 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>; reg = <0x0180>; }; - hdmi_dpll_clk_mux: hdmi_dpll_clk_mux { + hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0164>; }; - mlb_clk: mlb_clk { + mlb_clk: mlb_clk@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mlb_clkin_ck>; @@ -1118,7 +1118,7 @@ ti,index-power-of-two; }; - mlbp_clk: mlbp_clk { + mlbp_clk: mlbp_clk@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mlbp_clkin_ck>; @@ -1127,7 +1127,7 @@ ti,index-power-of-two; }; - per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div { + per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2_ck>; @@ -1136,7 +1136,7 @@ ti,index-power-of-two; }; - timer_sys_clk_div: timer_sys_clk_div { + timer_sys_clk_div: timer_sys_clk_div@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin1>; @@ -1144,28 +1144,28 @@ ti,max-div = <2>; }; - video1_dpll_clk_mux: video1_dpll_clk_mux { + video1_dpll_clk_mux: video1_dpll_clk_mux@168 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x0168>; }; - video2_dpll_clk_mux: video2_dpll_clk_mux { + video2_dpll_clk_mux: video2_dpll_clk_mux@16c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; reg = <0x016c>; }; - wkupaon_iclk_mux: wkupaon_iclk_mux { + wkupaon_iclk_mux: wkupaon_iclk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&abe_lp_clk_div>; reg = <0x0108>; }; - gpio1_dbclk: gpio1_dbclk { + gpio1_dbclk: gpio1_dbclk@1838 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1173,7 +1173,7 @@ reg = <0x1838>; }; - dcan1_sys_clk_mux: dcan1_sys_clk_mux { + dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; @@ -1181,7 +1181,7 @@ reg = <0x1888>; }; - timer1_gfclk_mux: timer1_gfclk_mux { + timer1_gfclk_mux: timer1_gfclk_mux@1840 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -1189,7 +1189,7 @@ reg = <0x1840>; }; - uart10_gfclk_mux: uart10_gfclk_mux { + uart10_gfclk_mux: uart10_gfclk_mux@1880 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -1198,14 +1198,14 @@ }; }; &cm_core_clocks { - dpll_pcie_ref_ck: dpll_pcie_ref_ck { + dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&sys_clkin1>; reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>; }; - dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck { + dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_ck>; @@ -1224,7 +1224,7 @@ ti,bit-shift = <7>; }; - apll_pcie_ck: apll_pcie_ck { + apll_pcie_ck: apll_pcie_ck@21c { #clock-cells = <0>; compatible = "ti,dra7-apll-clock"; clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>; @@ -1313,7 +1313,7 @@ clock-div = <1>; }; - dpll_per_byp_mux: dpll_per_byp_mux { + dpll_per_byp_mux: dpll_per_byp_mux@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>; @@ -1321,14 +1321,14 @@ reg = <0x014c>; }; - dpll_per_ck: dpll_per_ck { + dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin1>, <&dpll_per_byp_mux>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; - dpll_per_m2_ck: dpll_per_m2_ck { + dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; @@ -1347,7 +1347,7 @@ clock-div = <1>; }; - dpll_usb_byp_mux: dpll_usb_byp_mux { + dpll_usb_byp_mux: dpll_usb_byp_mux@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>; @@ -1355,14 +1355,14 @@ reg = <0x018c>; }; - dpll_usb_ck: dpll_usb_ck { + dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; - dpll_usb_m2_ck: dpll_usb_m2_ck { + dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_ck>; @@ -1373,7 +1373,7 @@ ti,invert-autoidle-bit; }; - dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck { + dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_pcie_ref_ck>; @@ -1390,7 +1390,7 @@ clocks = <&dpll_per_ck>; }; - dpll_per_h11x2_ck: dpll_per_h11x2_ck { + dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -1401,7 +1401,7 @@ ti,invert-autoidle-bit; }; - dpll_per_h12x2_ck: dpll_per_h12x2_ck { + dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -1412,7 +1412,7 @@ ti,invert-autoidle-bit; }; - dpll_per_h13x2_ck: dpll_per_h13x2_ck { + dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -1423,7 +1423,7 @@ ti,invert-autoidle-bit; }; - dpll_per_h14x2_ck: dpll_per_h14x2_ck { + dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -1434,7 +1434,7 @@ ti,invert-autoidle-bit; }; - dpll_per_m2x2_ck: dpll_per_m2x2_ck { + dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -1493,7 +1493,7 @@ clock-div = <2>; }; - l3init_60m_fclk: l3init_60m_fclk { + l3init_60m_fclk: l3init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>; @@ -1501,7 +1501,7 @@ ti,dividers = <1>, <8>; }; - clkout2_clk: clkout2_clk { + clkout2_clk: clkout2_clk@6b0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&clkoutmux2_clk_mux>; @@ -1509,7 +1509,7 @@ reg = <0x06b0>; }; - l3init_960m_gfclk: l3init_960m_gfclk { + l3init_960m_gfclk: l3init_960m_gfclk@6c0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_clkdcoldo>; @@ -1517,7 +1517,7 @@ reg = <0x06c0>; }; - dss_32khz_clk: dss_32khz_clk { + dss_32khz_clk: dss_32khz_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1525,7 +1525,7 @@ reg = <0x1120>; }; - dss_48mhz_clk: dss_48mhz_clk { + dss_48mhz_clk: dss_48mhz_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_48m_fclk>; @@ -1533,7 +1533,7 @@ reg = <0x1120>; }; - dss_dss_clk: dss_dss_clk { + dss_dss_clk: dss_dss_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_h12x2_ck>; @@ -1542,7 +1542,7 @@ ti,set-rate-parent; }; - dss_hdmi_clk: dss_hdmi_clk { + dss_hdmi_clk: dss_hdmi_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&hdmi_dpll_clk_mux>; @@ -1550,7 +1550,7 @@ reg = <0x1120>; }; - dss_video1_clk: dss_video1_clk { + dss_video1_clk: dss_video1_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&video1_dpll_clk_mux>; @@ -1558,7 +1558,7 @@ reg = <0x1120>; }; - dss_video2_clk: dss_video2_clk { + dss_video2_clk: dss_video2_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&video2_dpll_clk_mux>; @@ -1566,7 +1566,7 @@ reg = <0x1120>; }; - gpio2_dbclk: gpio2_dbclk { + gpio2_dbclk: gpio2_dbclk@1760 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1574,7 +1574,7 @@ reg = <0x1760>; }; - gpio3_dbclk: gpio3_dbclk { + gpio3_dbclk: gpio3_dbclk@1768 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1582,7 +1582,7 @@ reg = <0x1768>; }; - gpio4_dbclk: gpio4_dbclk { + gpio4_dbclk: gpio4_dbclk@1770 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1590,7 +1590,7 @@ reg = <0x1770>; }; - gpio5_dbclk: gpio5_dbclk { + gpio5_dbclk: gpio5_dbclk@1778 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1598,7 +1598,7 @@ reg = <0x1778>; }; - gpio6_dbclk: gpio6_dbclk { + gpio6_dbclk: gpio6_dbclk@1780 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1606,7 +1606,7 @@ reg = <0x1780>; }; - gpio7_dbclk: gpio7_dbclk { + gpio7_dbclk: gpio7_dbclk@1810 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1614,7 +1614,7 @@ reg = <0x1810>; }; - gpio8_dbclk: gpio8_dbclk { + gpio8_dbclk: gpio8_dbclk@1818 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1622,7 +1622,7 @@ reg = <0x1818>; }; - mmc1_clk32k: mmc1_clk32k { + mmc1_clk32k: mmc1_clk32k@1328 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1630,7 +1630,7 @@ reg = <0x1328>; }; - mmc2_clk32k: mmc2_clk32k { + mmc2_clk32k: mmc2_clk32k@1330 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1638,7 +1638,7 @@ reg = <0x1330>; }; - mmc3_clk32k: mmc3_clk32k { + mmc3_clk32k: mmc3_clk32k@1820 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1646,7 +1646,7 @@ reg = <0x1820>; }; - mmc4_clk32k: mmc4_clk32k { + mmc4_clk32k: mmc4_clk32k@1828 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1654,7 +1654,7 @@ reg = <0x1828>; }; - sata_ref_clk: sata_ref_clk { + sata_ref_clk: sata_ref_clk@1388 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_clkin1>; @@ -1662,7 +1662,7 @@ reg = <0x1388>; }; - usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m { + usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_960m_gfclk>; @@ -1670,7 +1670,7 @@ reg = <0x13f0>; }; - usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m { + usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_960m_gfclk>; @@ -1678,7 +1678,7 @@ reg = <0x1340>; }; - usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k { + usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1686,7 +1686,7 @@ reg = <0x0640>; }; - usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k { + usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1694,7 +1694,7 @@ reg = <0x0688>; }; - usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k { + usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1702,7 +1702,7 @@ reg = <0x0698>; }; - atl_dpll_clk_mux: atl_dpll_clk_mux { + atl_dpll_clk_mux: atl_dpll_clk_mux@c00 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>; @@ -1710,7 +1710,7 @@ reg = <0x0c00>; }; - atl_gfclk_mux: atl_gfclk_mux { + atl_gfclk_mux: atl_gfclk_mux@c00 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>; @@ -1718,7 +1718,7 @@ reg = <0x0c00>; }; - gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div { + gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@13d0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_gmac_m2_ck>; @@ -1727,7 +1727,7 @@ ti,dividers = <2>; }; - gmac_rft_clk_mux: gmac_rft_clk_mux { + gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>; @@ -1735,7 +1735,7 @@ reg = <0x13d0>; }; - gpu_core_gclk_mux: gpu_core_gclk_mux { + gpu_core_gclk_mux: gpu_core_gclk_mux@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; @@ -1743,7 +1743,7 @@ reg = <0x1220>; }; - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { + gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>; @@ -1751,7 +1751,7 @@ reg = <0x1220>; }; - l3instr_ts_gclk_div: l3instr_ts_gclk_div { + l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&wkupaon_iclk_mux>; @@ -1760,7 +1760,7 @@ ti,dividers = <8>, <16>, <32>; }; - mcasp2_ahclkr_mux: mcasp2_ahclkr_mux { + mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -1768,7 +1768,7 @@ reg = <0x1860>; }; - mcasp2_ahclkx_mux: mcasp2_ahclkx_mux { + mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -1776,7 +1776,7 @@ reg = <0x1860>; }; - mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux { + mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; @@ -1784,7 +1784,7 @@ reg = <0x1860>; }; - mcasp3_ahclkx_mux: mcasp3_ahclkx_mux { + mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -1792,7 +1792,7 @@ reg = <0x1868>; }; - mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux { + mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; @@ -1800,7 +1800,7 @@ reg = <0x1868>; }; - mcasp4_ahclkx_mux: mcasp4_ahclkx_mux { + mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -1808,7 +1808,7 @@ reg = <0x1898>; }; - mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux { + mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; @@ -1816,7 +1816,7 @@ reg = <0x1898>; }; - mcasp5_ahclkx_mux: mcasp5_ahclkx_mux { + mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -1824,7 +1824,7 @@ reg = <0x1878>; }; - mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux { + mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; @@ -1832,7 +1832,7 @@ reg = <0x1878>; }; - mcasp6_ahclkx_mux: mcasp6_ahclkx_mux { + mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -1840,7 +1840,7 @@ reg = <0x1904>; }; - mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux { + mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; @@ -1848,7 +1848,7 @@ reg = <0x1904>; }; - mcasp7_ahclkx_mux: mcasp7_ahclkx_mux { + mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -1856,7 +1856,7 @@ reg = <0x1908>; }; - mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux { + mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; @@ -1864,7 +1864,7 @@ reg = <0x1908>; }; - mcasp8_ahclk_mux: mcasp8_ahclk_mux { + mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>; @@ -1872,7 +1872,7 @@ reg = <0x1890>; }; - mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux { + mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>; @@ -1880,7 +1880,7 @@ reg = <0x1890>; }; - mmc1_fclk_mux: mmc1_fclk_mux { + mmc1_fclk_mux: mmc1_fclk_mux@1328 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; @@ -1888,7 +1888,7 @@ reg = <0x1328>; }; - mmc1_fclk_div: mmc1_fclk_div { + mmc1_fclk_div: mmc1_fclk_div@1328 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc1_fclk_mux>; @@ -1898,7 +1898,7 @@ ti,index-power-of-two; }; - mmc2_fclk_mux: mmc2_fclk_mux { + mmc2_fclk_mux: mmc2_fclk_mux@1330 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; @@ -1906,7 +1906,7 @@ reg = <0x1330>; }; - mmc2_fclk_div: mmc2_fclk_div { + mmc2_fclk_div: mmc2_fclk_div@1330 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc2_fclk_mux>; @@ -1916,7 +1916,7 @@ ti,index-power-of-two; }; - mmc3_gfclk_mux: mmc3_gfclk_mux { + mmc3_gfclk_mux: mmc3_gfclk_mux@1820 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -1924,7 +1924,7 @@ reg = <0x1820>; }; - mmc3_gfclk_div: mmc3_gfclk_div { + mmc3_gfclk_div: mmc3_gfclk_div@1820 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc3_gfclk_mux>; @@ -1934,7 +1934,7 @@ ti,index-power-of-two; }; - mmc4_gfclk_mux: mmc4_gfclk_mux { + mmc4_gfclk_mux: mmc4_gfclk_mux@1828 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -1942,7 +1942,7 @@ reg = <0x1828>; }; - mmc4_gfclk_div: mmc4_gfclk_div { + mmc4_gfclk_div: mmc4_gfclk_div@1828 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc4_gfclk_mux>; @@ -1952,7 +1952,7 @@ ti,index-power-of-two; }; - qspi_gfclk_mux: qspi_gfclk_mux { + qspi_gfclk_mux: qspi_gfclk_mux@1838 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>; @@ -1960,7 +1960,7 @@ reg = <0x1838>; }; - qspi_gfclk_div: qspi_gfclk_div { + qspi_gfclk_div: qspi_gfclk_div@1838 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&qspi_gfclk_mux>; @@ -1970,7 +1970,7 @@ ti,index-power-of-two; }; - timer10_gfclk_mux: timer10_gfclk_mux { + timer10_gfclk_mux: timer10_gfclk_mux@1728 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -1978,7 +1978,7 @@ reg = <0x1728>; }; - timer11_gfclk_mux: timer11_gfclk_mux { + timer11_gfclk_mux: timer11_gfclk_mux@1730 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -1986,7 +1986,7 @@ reg = <0x1730>; }; - timer13_gfclk_mux: timer13_gfclk_mux { + timer13_gfclk_mux: timer13_gfclk_mux@17c8 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -1994,7 +1994,7 @@ reg = <0x17c8>; }; - timer14_gfclk_mux: timer14_gfclk_mux { + timer14_gfclk_mux: timer14_gfclk_mux@17d0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -2002,7 +2002,7 @@ reg = <0x17d0>; }; - timer15_gfclk_mux: timer15_gfclk_mux { + timer15_gfclk_mux: timer15_gfclk_mux@17d8 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -2010,7 +2010,7 @@ reg = <0x17d8>; }; - timer16_gfclk_mux: timer16_gfclk_mux { + timer16_gfclk_mux: timer16_gfclk_mux@1830 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -2018,7 +2018,7 @@ reg = <0x1830>; }; - timer2_gfclk_mux: timer2_gfclk_mux { + timer2_gfclk_mux: timer2_gfclk_mux@1738 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -2026,7 +2026,7 @@ reg = <0x1738>; }; - timer3_gfclk_mux: timer3_gfclk_mux { + timer3_gfclk_mux: timer3_gfclk_mux@1740 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -2034,7 +2034,7 @@ reg = <0x1740>; }; - timer4_gfclk_mux: timer4_gfclk_mux { + timer4_gfclk_mux: timer4_gfclk_mux@1748 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -2042,7 +2042,7 @@ reg = <0x1748>; }; - timer9_gfclk_mux: timer9_gfclk_mux { + timer9_gfclk_mux: timer9_gfclk_mux@1750 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>; @@ -2050,7 +2050,7 @@ reg = <0x1750>; }; - uart1_gfclk_mux: uart1_gfclk_mux { + uart1_gfclk_mux: uart1_gfclk_mux@1840 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -2058,7 +2058,7 @@ reg = <0x1840>; }; - uart2_gfclk_mux: uart2_gfclk_mux { + uart2_gfclk_mux: uart2_gfclk_mux@1848 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -2066,7 +2066,7 @@ reg = <0x1848>; }; - uart3_gfclk_mux: uart3_gfclk_mux { + uart3_gfclk_mux: uart3_gfclk_mux@1850 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -2074,7 +2074,7 @@ reg = <0x1850>; }; - uart4_gfclk_mux: uart4_gfclk_mux { + uart4_gfclk_mux: uart4_gfclk_mux@1858 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -2082,7 +2082,7 @@ reg = <0x1858>; }; - uart5_gfclk_mux: uart5_gfclk_mux { + uart5_gfclk_mux: uart5_gfclk_mux@1870 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -2090,7 +2090,7 @@ reg = <0x1870>; }; - uart7_gfclk_mux: uart7_gfclk_mux { + uart7_gfclk_mux: uart7_gfclk_mux@18d0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -2098,7 +2098,7 @@ reg = <0x18d0>; }; - uart8_gfclk_mux: uart8_gfclk_mux { + uart8_gfclk_mux: uart8_gfclk_mux@18e0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -2106,7 +2106,7 @@ reg = <0x18e0>; }; - uart9_gfclk_mux: uart9_gfclk_mux { + uart9_gfclk_mux: uart9_gfclk_mux@18e8 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>; @@ -2114,7 +2114,7 @@ reg = <0x18e8>; }; - vip1_gclk_mux: vip1_gclk_mux { + vip1_gclk_mux: vip1_gclk_mux@1020 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; @@ -2122,7 +2122,7 @@ reg = <0x1020>; }; - vip2_gclk_mux: vip2_gclk_mux { + vip2_gclk_mux: vip2_gclk_mux@1028 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; @@ -2130,7 +2130,7 @@ reg = <0x1028>; }; - vip3_gclk_mux: vip3_gclk_mux { + vip3_gclk_mux: vip3_gclk_mux@1030 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>; @@ -2147,7 +2147,7 @@ }; &scm_conf_clocks { - dss_deshdcp_clk: dss_deshdcp_clk { + dss_deshdcp_clk: dss_deshdcp_clk@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3_iclk_div>; @@ -2155,7 +2155,7 @@ reg = <0x558>; }; - ehrpwm0_tbclk: ehrpwm0_tbclk { + ehrpwm0_tbclk: ehrpwm0_tbclk@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_root_clk_div>; @@ -2163,7 +2163,7 @@ reg = <0x0558>; }; - ehrpwm1_tbclk: ehrpwm1_tbclk { + ehrpwm1_tbclk: ehrpwm1_tbclk@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_root_clk_div>; @@ -2171,7 +2171,7 @@ reg = <0x0558>; }; - ehrpwm2_tbclk: ehrpwm2_tbclk { + ehrpwm2_tbclk: ehrpwm2_tbclk@558 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_root_clk_div>; diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 8c24975e8f9d..a35b851e1cd7 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -105,8 +105,8 @@ &pfc { uart1_pins: serial@e1030000 { - renesas,groups = "uart1_ctrl", "uart1_data"; - renesas,function = "uart1"; + groups = "uart1_ctrl", "uart1_data"; + function = "uart1"; }; }; diff --git a/arch/arm/boot/dts/exynos3250-artik5-eval.dts b/arch/arm/boot/dts/exynos3250-artik5-eval.dts new file mode 100644 index 000000000000..be4d6aa379f3 --- /dev/null +++ b/arch/arm/boot/dts/exynos3250-artik5-eval.dts @@ -0,0 +1,43 @@ +/* + * Samsung's Exynos3250 based ARTIK5 evaluation board device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's ARTIK5 evaluation board + * which is based on Samsung Exynos3250 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include "exynos3250-artik5.dtsi" + +/ { + model = "Samsung ARTIK5 evaluation board"; + compatible = "samsung,artik5-eval", "samsung,artik5", + "samsung,exynos3250", "samsung,exynos3"; +}; + +&mshc_2 { + num-slots = <1>; + cap-sd-highspeed; + disable-wp; + vqmmc-supply = <&ldo3_reg>; + card-detect-delay = <200>; + clock-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_cmd &sd2_clk &sd2_cd &sd2_bus1 &sd2_bus4>; + bus-width = <4>; + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi new file mode 100644 index 000000000000..130e946f1414 --- /dev/null +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -0,0 +1,334 @@ +/* + * Samsung's Exynos3250 based ARTIK5 module device tree source + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's ARTIK5 module which is based on + * Samsung Exynos3250 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "exynos3250.dtsi" +#include <dt-bindings/clock/samsung,s2mps11.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "samsung,artik5", "samsung,exynos3250", "samsung,exynos3"; + + chosen { + stdout-path = &serial_2; + }; + + memory { + reg = <0x40000000 0x1ff00000>; + }; + + firmware@0205f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0205f000 0x1000>; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + cooling-maps { + map0 { + /* Corresponds to 500MHz */ + cooling-device = <&cpu0 5 5>; + }; + map1 { + /* Corresponds to 200MHz */ + cooling-device = <&cpu0 8 8>; + }; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo7_reg>; + assigned-clocks = <&cmu CLK_SCLK_TSADC>; + assigned-clock-rates = <6000000>; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&i2c_0 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + s2mps14_pmic@66 { + compatible = "samsung,s2mps14-pmic"; + interrupt-parent = <&gpx3>; + interrupts = <5 IRQ_TYPE_NONE>; + reg = <0x66>; + + s2mps14_osc: clocks { + compatible = "samsung,s2mps14-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps14_ap", "unused", + "s2mps14_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + /* VDD_ALIVE15x */ + regulator-name = "VLDO1_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + /* VDDQM176 ~ VDDQM185 */ + regulator-name = "VLDO2_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + /* + * VDD1_E106 ~ VDD1_E111 + * DVDD_RTC_AP, DVDD_MMC2_AP + */ + regulator-name = "VLDO3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + /* AVDD_PLL1120 ~ AVDD_PLL11201 */ + regulator-name = "VLDO4_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + /* VDDI_PLL_ISO141 ~ VDDI_PLL_ISO142 */ + regulator-name = "VLDO5_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + /* VDD_USB, VDD10_HSIC */ + regulator-name = "VLDO6_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + /* + * VDD18P, AVDD18_TS, AVDD18_HSIC, AVDD_PLL2, + * AVDD_ADC, AVDD_ABB_0, M4S_VDD18 + */ + regulator-name = "VLDO7_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + /* AVDD33_UOTG */ + regulator-name = "VLDO8_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + /* VDDQ_E86 ~ VDDQ_E105*/ + regulator-name = "VLDO9_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "VLDO10_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo11_reg: LDO11 { + /* VDD74 ~ VDD75 */ + regulator-name = "VLDO11_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + ldo12_reg: LDO12 { + /* VDD72 ~ VDD73 */ + regulator-name = "VLDO12_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + samsung,ext-control-gpios = <&gpk0 2 GPIO_ACTIVE_HIGH>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VLDO13_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo14_reg: LDO14 { + regulator-name = "VLDO14_2.7V"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "VLDO_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "VLDO16_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo17_reg: LDO17 { + regulator-name = "VLDO17_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo18_reg: LDO18 { + /* DVDD_MMC2_AP */ + regulator-name = "VLDO18_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "VLDO19_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "VLDO20_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + regulator-name = "VLDO21_1.25V"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + + ldo22_reg: LDO22 { + regulator-name = "VLDO22_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo23_reg: LDO23 { + /* Xi2c3_SDA/SCL, Xi2c7_SDA/SCL, WLAN_SDIO */ + regulator-name = "VLDO23_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo24_reg: LDO24 { + regulator-name = "VLDO24_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "VLDO25_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + buck1_reg: BUCK1 { + /* VDD_MIF */ + regulator-name = "VBUCK1_1.0V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + /* VDD_CPU */ + regulator-name = "VBUCK2_1.2V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + buck3_reg: BUCK3 { + /* VDD_G3D */ + regulator-name = "VBUCK3_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VBUCK4_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "VBUCK5_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + }; + }; +}; + +&mshc_0 { + num-slots = <1>; + non-removable; + cap-mmc-highspeed; + card-detect-delay = <200>; + vmmc-supply = <&ldo12_reg>; + clock-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + status = "okay"; +}; + +&rtc { + clocks = <&cmu CLK_RTC>, <&s2mps14_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&tmu { + status = "okay"; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 9e2840b59ae8..267f81adb42f 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -558,7 +558,17 @@ &pinctrl_1 { pinctrl-names = "default"; - pinctrl-0 = <&sleep1>; + pinctrl-0 = <&initial1 &sleep1>; + + initial1: initial-state { + PIN_IN(gpk2-0, DOWN, LV1); + PIN_IN(gpk2-1, DOWN, LV1); + PIN_IN(gpk2-2, DOWN, LV1); + PIN_IN(gpk2-3, DOWN, LV1); + PIN_IN(gpk2-4, DOWN, LV1); + PIN_IN(gpk2-5, DOWN, LV1); + PIN_IN(gpk2-6, DOWN, LV1); + }; sleep1: sleep-state { PIN_SLP(gpe0-0, PREV, NONE); diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index 5ab81c39e2c9..40ea7de44933 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -16,11 +16,49 @@ #define PIN_PULL_DOWN 1 #define PIN_PULL_UP 3 +#define PIN_DRV_LV1 0 +#define PIN_DRV_LV2 2 +#define PIN_DRV_LV3 1 +#define PIN_DRV_LV4 3 + #define PIN_PDN_OUT0 0 #define PIN_PDN_OUT1 1 #define PIN_PDN_INPUT 2 #define PIN_PDN_PREV 3 +#define PIN_IN(_pin, _pull, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <0>; \ + samsung,pin-pud = <PIN_PULL_ ##_pull>; \ + samsung,pin-drv = <PIN_DRV_ ##_drv>; \ + } + +#define PIN_OUT(_pin, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <1>; \ + samsung,pin-pud = <0>; \ + samsung,pin-drv = <PIN_DRV_ ##_drv>; \ + } + +#define PIN_OUT_SET(_pin, _val, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <1>; \ + samsung,pin-pud = <0>; \ + samsung,pin-drv = <PIN_DRV_ ##_drv>; \ + samsung,pin-val = <_val>; \ + } + +#define PIN_CFG(_pin, _sel, _pull, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <_sel>; \ + samsung,pin-pud = <PIN_PULL_ ##_pull>; \ + samsung,pin-drv = <PIN_DRV_ ##_drv>; \ + } + #define PIN_SLP(_pin, _mode, _pull) \ _pin { \ samsung,pins = #_pin; \ @@ -120,6 +158,13 @@ samsung,pin-drv = <0>; }; + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <3>; @@ -445,6 +490,41 @@ samsung,pin-drv = <3>; }; + sd2_clk: sd2-clk { + samsung,pins = "gpk2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpk2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpk2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpk2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + cam_port_b_io: cam-port-b-io { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 1f102f3a1ab1..31eb09bae0a2 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -681,7 +681,21 @@ &pinctrl_0 { pinctrl-names = "default"; - pinctrl-0 = <&sleep0>; + pinctrl-0 = <&initial0 &sleep0>; + + initial0: initial-state { + PIN_IN(gpa1-4, DOWN, LV1); + PIN_IN(gpa1-5, DOWN, LV1); + + PIN_IN(gpc0-0, DOWN, LV1); + PIN_IN(gpc0-1, DOWN, LV1); + PIN_IN(gpc0-2, DOWN, LV1); + PIN_IN(gpc0-3, DOWN, LV1); + PIN_IN(gpc0-4, DOWN, LV1); + + PIN_IN(gpd0-0, DOWN, LV1); + PIN_IN(gpd0-1, DOWN, LV1); + }; sleep0: sleep-state { PIN_SLP(gpa0-0, INPUT, DOWN); @@ -735,7 +749,60 @@ &pinctrl_1 { pinctrl-names = "default"; - pinctrl-0 = <&sleep1>; + pinctrl-0 = <&initial1 &sleep1>; + + initial1: initial-state { + PIN_IN(gpe0-6, DOWN, LV1); + PIN_IN(gpe0-7, DOWN, LV1); + + PIN_IN(gpe1-0, DOWN, LV1); + PIN_IN(gpe1-3, DOWN, LV1); + PIN_IN(gpe1-4, DOWN, LV1); + PIN_IN(gpe1-5, DOWN, LV1); + PIN_IN(gpe1-6, DOWN, LV1); + + PIN_IN(gpk2-0, DOWN, LV1); + PIN_IN(gpk2-1, DOWN, LV1); + PIN_IN(gpk2-2, DOWN, LV1); + PIN_IN(gpk2-3, DOWN, LV1); + PIN_IN(gpk2-4, DOWN, LV1); + PIN_IN(gpk2-5, DOWN, LV1); + PIN_IN(gpk2-6, DOWN, LV1); + + PIN_IN(gpm0-0, DOWN, LV1); + PIN_IN(gpm0-1, DOWN, LV1); + PIN_IN(gpm0-2, DOWN, LV1); + PIN_IN(gpm0-3, DOWN, LV1); + PIN_IN(gpm0-4, DOWN, LV1); + PIN_IN(gpm0-5, DOWN, LV1); + PIN_IN(gpm0-6, DOWN, LV1); + PIN_IN(gpm0-7, DOWN, LV1); + + PIN_IN(gpm1-0, DOWN, LV1); + PIN_IN(gpm1-1, DOWN, LV1); + PIN_IN(gpm1-2, DOWN, LV1); + PIN_IN(gpm1-3, DOWN, LV1); + PIN_IN(gpm1-4, DOWN, LV1); + PIN_IN(gpm1-5, DOWN, LV1); + PIN_IN(gpm1-6, DOWN, LV1); + + PIN_IN(gpm2-0, DOWN, LV1); + PIN_IN(gpm2-1, DOWN, LV1); + + PIN_IN(gpm3-0, DOWN, LV1); + PIN_IN(gpm3-1, DOWN, LV1); + PIN_IN(gpm3-2, DOWN, LV1); + PIN_IN(gpm3-3, DOWN, LV1); + PIN_IN(gpm3-4, DOWN, LV1); + + PIN_IN(gpm4-1, DOWN, LV1); + PIN_IN(gpm4-2, DOWN, LV1); + PIN_IN(gpm4-3, DOWN, LV1); + PIN_IN(gpm4-4, DOWN, LV1); + PIN_IN(gpm4-5, DOWN, LV1); + PIN_IN(gpm4-6, DOWN, LV1); + PIN_IN(gpm4-7, DOWN, LV1); + }; sleep1: sleep-state { PIN_SLP(gpe0-0, PREV, NONE); diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 137f9015d4e8..094782b207ee 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -31,6 +31,7 @@ pinctrl1 = &pinctrl_1; mshc0 = &mshc_0; mshc1 = &mshc_1; + mshc2 = &mshc_2; spi0 = &spi_0; spi1 = &spi_1; i2c0 = &i2c_0; @@ -43,6 +44,7 @@ i2c7 = &i2c_7; serial0 = &serial_0; serial1 = &serial_1; + serial2 = &serial_2; }; cpus { @@ -153,7 +155,7 @@ interrupt-parent = <&gic>; }; - mipi_phy: video-phy@10020710 { + mipi_phy: video-phy { compatible = "samsung,s5pv210-mipi-video-phy"; #phy-cells = <1>; syscon = <&pmu_system_controller>; @@ -357,6 +359,18 @@ status = "disabled"; }; + mshc_2: mshc@12530000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12530000 0x1000>; + interrupts = <0 144 0>; + clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + exynos_usbphy: exynos-usbphy@125B0000 { compatible = "samsung,exynos3250-usb2-phy"; reg = <0x125B0000 0x100>; @@ -452,6 +466,17 @@ status = "disabled"; }; + serial_2: serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 111 0>; + clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_data>; + status = "disabled"; + }; + i2c_0: i2c@13860000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index c679b3cc3c48..ca8f3e3cf2f3 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -77,12 +77,12 @@ reg = <0x10000000 0x100>; }; - sromc@12570000 { - compatible = "samsung,exynos-srom"; + memory-controller@12570000 { + compatible = "samsung,exynos4210-srom"; reg = <0x12570000 0x14>; }; - mipi_phy: video-phy@10020710 { + mipi_phy: video-phy { compatible = "samsung,s5pv210-mipi-video-phy"; #phy-cells = <1>; syscon = <&pmu_system_controller>; @@ -743,6 +743,18 @@ status = "disabled"; }; + hdmicec: cec@100B0000 { + compatible = "samsung,s5p-cec"; + reg = <0x100B0000 0x200>; + interrupts = <0 114 0>; + clocks = <&clock CLK_HDMI_CEC>; + clock-names = "hdmicec"; + samsung,syscon-phandle = <&pmu_system_controller>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "disabled"; + }; + mixer: mixer@12C10000 { compatible = "samsung,exynos4210-mixer"; interrupts = <0 91 0>; @@ -969,11 +981,18 @@ #iommu-cells = <0>; }; + sss: sss@10830000 { + compatible = "samsung,exynos4210-secss"; + reg = <0x10830000 0x300>; + interrupts = <0 112 0>; + clocks = <&clock CLK_SSS>; + clock-names = "secss"; + }; + prng: rng@10830400 { compatible = "samsung,exynos4-rng"; reg = <0x10830400 0x200>; clocks = <&clock CLK_SSS>; clock-names = "secss"; - status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index a7c212891674..9331c6252eff 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -820,6 +820,13 @@ samsung,pin-pud = <1>; samsung,pin-drv = <0>; }; + + hdmi_cec: hdmi-cec { + samsung,pins = "gpx3-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; pinctrl@03860000 { diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 5e5d3fecb04c..cab0f07d7d28 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -188,6 +188,10 @@ status = "okay"; }; +&hdmicec { + status = "okay"; +}; + &hsotg { dr_mode = "peripheral"; status = "okay"; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index ed017cc7b14f..5d1eaea3f778 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -146,13 +146,13 @@ reg = <0x66>; regulators { - esafeout1_reg: ESAFEOUT1@1 { + esafeout1_reg: ESAFEOUT1 { regulator-name = "ESAFEOUT1"; }; - esafeout2_reg: ESAFEOUT2@2 { + esafeout2_reg: ESAFEOUT2 { regulator-name = "ESAFEOUT2"; }; - charger_reg: CHARGER@0 { + charger_reg: CHARGER { regulator-name = "CHARGER"; regulator-min-microamp = <60000>; regulator-max-microamp = <2580000>; @@ -251,7 +251,7 @@ "SPK", "SPKOUTRP"; }; - thermistor-ap@0 { + thermistor-ap { compatible = "ntc,ncp15wb473"; pullup-uv = <1800000>; /* VCC_1.8V_AP */ pullup-ohm = <100000>; /* 100K */ @@ -259,7 +259,7 @@ io-channels = <&adc 1>; /* AP temperature */ }; - thermistor-battery@1 { + thermistor-battery { compatible = "ntc,ncp15wb473"; pullup-uv = <1800000>; /* VCC_1.8V_AP */ pullup-ohm = <100000>; /* 100K */ @@ -1234,10 +1234,6 @@ status = "okay"; }; -&prng { - status = "okay"; -}; - &rtc { status = "okay"; clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; @@ -1276,7 +1272,7 @@ cs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>; status = "okay"; - s5c73m3_spi: s5c73m3 { + s5c73m3_spi: s5c73m3@0 { compatible = "samsung,s5c73m3"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index bac25c672789..856b29254374 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -885,6 +885,13 @@ samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; + + hdmi_cec: hdmi-cec { + samsung,pins = "gpx3-6"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; pinctrl_2: pinctrl@03860000 { diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 84a23f962946..b7490ea0c75c 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -179,7 +179,7 @@ ranges; status = "disabled"; - pmu { + pmu@10020000 { reg = <0x10020000 0x3000>; }; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 92313cac035e..d5c0f18a4223 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -31,8 +31,8 @@ reg = <0x10000000 0x100>; }; - sromc@12250000 { - compatible = "samsung,exynos-srom"; + memory-controller@12250000 { + compatible = "samsung,exynos4210-srom"; reg = <0x12250000 0x14>; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 8b2acc74aa76..1e25152dc0f6 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -133,7 +133,7 @@ display-timings { native-mode = <&timing0>; - timing0: timing@0 { + timing0: timing { /* 2560x1600 DP panel */ clock-frequency = <50000>; hactive = <2560>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 0f5dcd418af8..0e2eb3f6b590 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -29,7 +29,7 @@ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; - vdd: fixed-regulator@0 { + vdd: fixed-regulator-vdd { compatible = "regulator-fixed"; regulator-name = "vdd-supply"; regulator-min-microvolt = <1800000>; @@ -37,7 +37,7 @@ regulator-always-on; }; - dbvdd: fixed-regulator@1 { + dbvdd: fixed-regulator-dbvdd { compatible = "regulator-fixed"; regulator-name = "dbvdd-supply"; regulator-min-microvolt = <3300000>; @@ -45,7 +45,7 @@ regulator-always-on; }; - spkvdd: fixed-regulator@2 { + spkvdd: fixed-regulator-spkvdd { compatible = "regulator-fixed"; regulator-name = "spkvdd-supply"; regulator-min-microvolt = <5000000>; @@ -93,7 +93,7 @@ display-timings { native-mode = <&timing0>; - timing0: timing@0 { + timing0: timing { /* 1280x800 */ clock-frequency = <50000>; hactive = <1280>; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index 95210ef6a6b5..c9889b1f530a 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -84,7 +84,7 @@ sbs,poll-retry-count = <1>; }; - cros_ec: embedded-controller { + cros_ec: embedded-controller@1e { compatible = "google,cros-ec-i2c"; reg = <0x1e>; interrupts = <6 IRQ_TYPE_NONE>; @@ -94,7 +94,7 @@ wakeup-source; }; - power-regulator { + power-regulator@48 { compatible = "ti,tps65090"; reg = <0x48>; @@ -244,7 +244,7 @@ samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>; ports { - port@0 { + port0 { dp_out: endpoint { remote-endpoint = <&bridge_in>; }; @@ -428,7 +428,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <378000>; - trackpad { + trackpad@67 { reg = <0x67>; compatible = "cypress,cyapa"; interrupts = <2 IRQ_TYPE_NONE>; @@ -487,13 +487,13 @@ edid-emulation = <5>; ports { - port@0 { + port0 { bridge_out: endpoint { remote-endpoint = <&panel_in>; }; }; - port@1 { + port1 { bridge_in: endpoint { remote-endpoint = <&dp_out>; }; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 0f500cb1eb2d..273d66282ebc 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -383,7 +383,7 @@ samsung,i2c-sda-delay = <100>; samsung,i2c-max-bus-freq = <66000>; - cros_ec: embedded-controller { + cros_ec: embedded-controller@1e { compatible = "google,cros-ec-i2c"; reg = <0x1e>; interrupts = <6 IRQ_TYPE_NONE>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index e653ae04015a..c7158b2fb213 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -596,7 +596,7 @@ pinctrl-0 = <&i2s2_bus>; }; - usb@12000000 { + usb_dwc3 { compatible = "samsung,exynos5250-dwusb3"; clocks = <&clock CLK_USB3>; clock-names = "usbdrd30"; @@ -604,7 +604,7 @@ #size-cells = <1>; ranges; - usbdrd_dwc3: dwc3 { + usbdrd_dwc3: dwc3@12000000 { compatible = "synopsys,dwc3"; reg = <0x12000000 0x10000>; interrupts = <0 72 0>; @@ -763,7 +763,7 @@ iommu = <&sysmmu_gsc3>; }; - hdmi: hdmi { + hdmi: hdmi@14530000 { compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; power-domains = <&pd_disp1>; @@ -776,7 +776,7 @@ samsung,syscon-phandle = <&pmu_system_controller>; }; - mixer { + mixer@14450000 { compatible = "samsung,exynos5250-mixer"; reg = <0x14450000 0x10000>; power-domains = <&pd_disp1>; @@ -787,7 +787,7 @@ iommus = <&sysmmu_tv>; }; - dp_phy: video-phy@10040720 { + dp_phy: video-phy { compatible = "samsung,exynos5250-dp-video-phy"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index a731fbe28ebc..0f6429e1b75c 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -97,7 +97,7 @@ smsc,irq-push-pull; smsc,force-internal-phy; - samsung,srom-page-mode = <1>; + samsung,srom-page-mode; samsung,srom-timing = <9 12 1 9 1 1>; }; }; diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index fa558674ac76..7a56aec2c5ba 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -102,8 +102,8 @@ reg = <0x10000000 0x100>; }; - sromc: sromc@12250000 { - compatible = "samsung,exynos-srom"; + sromc: memory-controller@12250000 { + compatible = "samsung,exynos4210-srom"; reg = <0x12250000 0x14>; #address-cells = <2>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index a103ce8c3985..60bc861d0f9d 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -75,13 +75,6 @@ s2mps11_pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; - s2mps11,buck2-ramp-delay = <12>; - s2mps11,buck34-ramp-delay = <12>; - s2mps11,buck16-ramp-delay = <12>; - s2mps11,buck6-ramp-enable = <1>; - s2mps11,buck2-ramp-enable = <1>; - s2mps11,buck3-ramp-enable = <1>; - s2mps11,buck4-ramp-enable = <1>; interrupt-parent = <&gpx3>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index e036e6467a7b..8811e170c2af 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -165,7 +165,7 @@ samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; ports { - port@0 { + port0 { dp_out: endpoint { remote-endpoint = <&bridge_in>; }; @@ -633,13 +633,13 @@ use-external-pwm; ports { - port@0 { + port0 { bridge_out: endpoint { remote-endpoint = <&panel_in>; }; }; - port@1 { + port1 { bridge_in: endpoint { remote-endpoint = <&dp_out>; }; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 0785fedf441e..9b77940c9201 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -111,7 +111,7 @@ display-timings { native-mode = <&timing0>; - timing0: timing@0 { + timing0: timing { clock-frequency = <50000>; hactive = <2560>; vactive = <1600>; @@ -142,13 +142,6 @@ s2mps11_pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; - s2mps11,buck2-ramp-delay = <12>; - s2mps11,buck34-ramp-delay = <12>; - s2mps11,buck16-ramp-delay = <12>; - s2mps11,buck6-ramp-enable = <1>; - s2mps11,buck2-ramp-enable = <1>; - s2mps11,buck3-ramp-enable = <1>; - s2mps11,buck4-ramp-enable = <1>; s2mps11_osc: clocks { #clock-cells = <1>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 7b99cb58d82d..4c8523471c65 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -551,13 +551,13 @@ clock-names = "timers"; }; - dp_phy: video-phy@10040728 { + dp_phy: dp-video-phy { compatible = "samsung,exynos5420-dp-video-phy"; samsung,pmu-syscon = <&pmu_system_controller>; #phy-cells = <0>; }; - mipi_phy: video-phy@10040714 { + mipi_phy: mipi-video-phy { compatible = "samsung,s5pv210-mipi-video-phy"; syscon = <&pmu_system_controller>; #phy-cells = <1>; @@ -913,7 +913,7 @@ clock-names = "secss"; }; - usbdrd3_0: usb@12000000 { + usbdrd3_0: usb3-0 { compatible = "samsung,exynos5250-dwusb3"; clocks = <&clock CLK_USBD300>; clock-names = "usbdrd30"; @@ -921,7 +921,7 @@ #size-cells = <1>; ranges; - usbdrd_dwc3_0: dwc3 { + usbdrd_dwc3_0: dwc3@12000000 { compatible = "snps,dwc3"; reg = <0x12000000 0x10000>; interrupts = <0 72 0>; @@ -939,7 +939,7 @@ #phy-cells = <1>; }; - usbdrd3_1: usb@12400000 { + usbdrd3_1: usb3-1 { compatible = "samsung,exynos5250-dwusb3"; clocks = <&clock CLK_USBD301>; clock-names = "usbdrd30"; @@ -947,7 +947,7 @@ #size-cells = <1>; ranges; - usbdrd_dwc3_1: dwc3 { + usbdrd_dwc3_1: dwc3@12400000 { compatible = "snps,dwc3"; reg = <0x12400000 0x10000>; interrupts = <0 73 0>; @@ -1199,6 +1199,7 @@ }; &fimd { + compatible = "samsung,exynos5420-fimd"; clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; power-domains = <&disp_pd>; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 1bd507bfa750..20fa7612080d 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -92,13 +92,6 @@ s2mps11_pmic@66 { compatible = "samsung,s2mps11-pmic"; reg = <0x66>; - s2mps11,buck2-ramp-delay = <12>; - s2mps11,buck34-ramp-delay = <12>; - s2mps11,buck16-ramp-delay = <12>; - s2mps11,buck6-ramp-enable = <1>; - s2mps11,buck2-ramp-enable = <1>; - s2mps11,buck3-ramp-enable = <1>; - s2mps11,buck4-ramp-enable = <1>; samsung,s2mps11-acokb-ground; interrupt-parent = <&gpx0>; @@ -121,10 +114,9 @@ }; ldo3_reg: LDO3 { - regulator-name = "vdd_ldo3"; + regulator-name = "vddq_mmc0"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; }; ldo5_reg: LDO5 { @@ -184,10 +176,9 @@ }; ldo13_reg: LDO13 { - regulator-name = "vdd_ldo13"; + regulator-name = "vddq_mmc2"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - regulator-always-on; }; ldo15_reg: LDO15 { @@ -211,11 +202,16 @@ regulator-always-on; }; + ldo18_reg: LDO18 { + regulator-name = "vdd_emmc_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + ldo19_reg: LDO19 { regulator-name = "vdd_sd"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - regulator-always-on; }; ldo24_reg: LDO24 { @@ -347,6 +343,8 @@ cap-mmc-highspeed; mmc-hs200-1_8v; mmc-hs400-1_8v; + vmmc-supply = <&ldo18_reg>; + vqmmc-supply = <&ldo3_reg>; }; &mmc_2 { @@ -359,6 +357,8 @@ pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; bus-width = <4>; cap-sd-highspeed; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; }; &pinctrl_0 { diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index b9342ec5b9cf..fd176819b4bf 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -132,7 +132,7 @@ clock-names = "spi", "spi_busclk0"; }; - pin_ctrl: pinctrl { + pin_ctrl: pinctrl@E0000 { compatible = "samsung,exynos5440-pinctrl"; reg = <0xE0000 0x1000>; interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, @@ -205,7 +205,7 @@ ranges; }; - rtc { + rtc@130000 { compatible = "samsung,s3c6410-rtc"; reg = <0x130000 0x1000>; interrupts = <0 17 0>, <0 16 0>; diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index 848ffa785b63..f96fa2df8f11 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -110,20 +110,20 @@ #define MX25_PAD_CS4__UART5_CTS 0x054 0x264 0x000 0x13 0x000 #define MX25_PAD_CS4__GPIO_3_20 0x054 0x264 0x000 0x15 0x000 -#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x10 0x000 +#define MX25_PAD_CS5__CS5 0x058 0x268 0x000 0x00 0x000 #define MX25_PAD_CS5__NF_CE2 0x058 0x268 0x000 0x01 0x000 -#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x13 0x000 -#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x15 0x000 +#define MX25_PAD_CS5__UART5_RTS 0x058 0x268 0x574 0x03 0x000 +#define MX25_PAD_CS5__GPIO_3_21 0x058 0x268 0x000 0x05 0x000 #define MX25_PAD_NF_CE0__NF_CE0 0x05c 0x26c 0x000 0x10 0x000 #define MX25_PAD_NF_CE0__GPIO_3_22 0x05c 0x26c 0x000 0x15 0x000 #define MX25_PAD_ECB__ECB 0x060 0x270 0x000 0x10 0x000 -#define MX25_PAD_ECB__UART5_TXD_MUX 0x060 0x270 0x000 0x13 0x000 +#define MX25_PAD_ECB__UART5_TXD 0x060 0x270 0x000 0x13 0x000 #define MX25_PAD_ECB__GPIO_3_23 0x060 0x270 0x000 0x15 0x000 #define MX25_PAD_LBA__LBA 0x064 0x274 0x000 0x10 0x000 -#define MX25_PAD_LBA__UART5_RXD_MUX 0x064 0x274 0x578 0x13 0x000 +#define MX25_PAD_LBA__UART5_RXD 0x064 0x274 0x578 0x13 0x000 #define MX25_PAD_LBA__GPIO_3_24 0x064 0x274 0x000 0x15 0x000 #define MX25_PAD_BCLK__BCLK 0x068 0x000 0x000 0x00 0x000 @@ -237,17 +237,21 @@ #define MX25_PAD_LD7__GPIO_1_21 0x0e4 0x2dc 0x000 0x15 0x000 #define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000 +#define MX25_PAD_LD8__UART4_RXD 0x0e8 0x2e0 0x570 0x12 0x000 #define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000 #define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000 #define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000 +#define MX25_PAD_LD9__UART4_TXD 0x0ec 0x2e4 0x000 0x12 0x000 #define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001 #define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000 -#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000 -#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x15 0x001 +#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x00 0x000 +#define MX25_PAD_LD10__UART4_RTS 0x0f0 0x2e8 0x56c 0x02 0x000 +#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x05 0x001 #define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000 +#define MX25_PAD_LD11__UART4_CTS 0x0f4 0x2ec 0x000 0x12 0x000 #define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001 #define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000 @@ -291,22 +295,22 @@ #define MX25_PAD_PWM__USBH2_OC 0x11c 0x314 0x580 0x16 0x001 #define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000 -#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001 +#define MX25_PAD_CSI_D2__UART5_RXD 0x120 0x318 0x578 0x11 0x001 #define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000 #define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000 #define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 #define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 -#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000 +#define MX25_PAD_CSI_D3__UART5_TXD 0x124 0x31c 0x000 0x11 0x000 #define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000 #define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 #define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 -#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000 -#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001 +#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x00 0x000 +#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x01 0x001 #define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000 -#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000 -#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 +#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x05 0x000 +#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x07 0x000 #define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 #define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x000 @@ -360,7 +364,7 @@ #define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000 #define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000 -#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x000 0x12 0x000 +#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x568 0x12 0x000 #define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000 #define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000 @@ -371,10 +375,10 @@ #define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000 #define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000 -#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000 -#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x11 0x001 -#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x12 0x000 -#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000 +#define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x00 0x000 +#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x01 0x001 +#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x02 0x000 +#define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x05 0x000 #define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000 #define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000 @@ -383,20 +387,24 @@ #define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000 #define MX25_PAD_CSPI1_RDY__GPIO_2_22 0x16c 0x364 0x000 0x15 0x000 -#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x10 0x000 -#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x15 0x000 +#define MX25_PAD_UART1_RXD__UART1_RXD 0x170 0x368 0x000 0x00 0x000 +#define MX25_PAD_UART1_RXD__UART2_DTR 0x170 0x368 0x000 0x03 0x000 +#define MX25_PAD_UART1_RXD__GPIO_4_22 0x170 0x368 0x000 0x05 0x000 -#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x10 0x000 -#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x15 0x000 +#define MX25_PAD_UART1_TXD__UART1_TXD 0x174 0x36c 0x000 0x00 0x000 +#define MX25_PAD_UART1_TXD__UART2_DSR 0x174 0x36c 0x000 0x03 0x000 +#define MX25_PAD_UART1_TXD__GPIO_4_23 0x174 0x36c 0x000 0x05 0x000 -#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000 -#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001 -#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x12 0x000 -#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000 +#define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x00 0x000 +#define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x01 0x001 +#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x02 0x000 +#define MX25_PAD_UART1_RTS__UART2_DCD 0x178 0x370 0x000 0x03 0x000 +#define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x05 0x000 -#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000 -#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x11 0x001 -#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x15 0x000 +#define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x00 0x000 +#define MX25_PAD_UART1_CTS__CSI_D1 0x17c 0x374 0x48c 0x01 0x001 +#define MX25_PAD_UART1_CTS__UART2_RI 0x17c 0x374 0x000 0x03 0x001 +#define MX25_PAD_UART1_CTS__GPIO_4_25 0x17c 0x374 0x000 0x05 0x000 #define MX25_PAD_UART2_RXD__UART2_RXD 0x180 0x378 0x000 0x10 0x000 #define MX25_PAD_UART2_RXD__GPIO_4_26 0x180 0x378 0x000 0x15 0x000 @@ -404,10 +412,10 @@ #define MX25_PAD_UART2_TXD__UART2_TXD 0x184 0x37c 0x000 0x10 0x000 #define MX25_PAD_UART2_TXD__GPIO_4_27 0x184 0x37c 0x000 0x15 0x000 -#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000 -#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002 -#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000 -#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 +#define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x00 0x000 +#define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x02 0x002 +#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x03 0x000 +#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x05 0x000 #define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000 #define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002 @@ -439,36 +447,42 @@ #define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x12 0x002 #define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000 -#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000 -#define MX25_PAD_KPP_ROW0__UART1_DTR 0x1a8 0x3a0 0x000 0x14 0x000 -#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x15 0x000 +#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x00 0x000 +#define MX25_PAD_KPP_ROW0__UART3_RXD 0x1a8 0x3a0 0x568 0x01 0x001 +#define MX25_PAD_KPP_ROW0__UART1_DTR 0x1a8 0x3a0 0x000 0x04 0x000 +#define MX25_PAD_KPP_ROW0__GPIO_2_29 0x1a8 0x3a0 0x000 0x05 0x000 -#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x10 0x000 -#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x15 0x000 +#define MX25_PAD_KPP_ROW1__KPP_ROW1 0x1ac 0x3a4 0x000 0x00 0x000 +#define MX25_PAD_KPP_ROW1__UART3_TXD 0x1ac 0x3a4 0x000 0x01 0x000 +#define MX25_PAD_KPP_ROW1__UART1_DSR 0x1ac 0x3a4 0x000 0x04 0x000 +#define MX25_PAD_KPP_ROW1__GPIO_2_30 0x1ac 0x3a4 0x000 0x05 0x000 -#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x10 0x000 -#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x13 0x002 -#define MX25_PAD_KPP_ROW2__UART1_DCD 0x1b0 0x3a8 0x000 0x14 0x000 -#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000 +#define MX25_PAD_KPP_ROW2__KPP_ROW2 0x1b0 0x3a8 0x000 0x00 0x000 +#define MX25_PAD_KPP_ROW2__UART3_RTS 0x1b0 0x3a8 0x000 0x01 0x000 +#define MX25_PAD_KPP_ROW2__CSI_D0 0x1b0 0x3a8 0x488 0x03 0x002 +#define MX25_PAD_KPP_ROW2__UART1_DCD 0x1b0 0x3a8 0x000 0x04 0x000 +#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x05 0x000 -#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000 -#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x13 0x002 -#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000 +#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x00 0x000 +#define MX25_PAD_KPP_ROW3__UART3_CTS 0x1b4 0x3ac 0x000 0x01 0x000 +#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x03 0x002 +#define MX25_PAD_KPP_ROW3__UART1_RI 0x1b4 0x3ac 0x000 0x04 0x000 +#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x05 0x000 #define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000 -#define MX25_PAD_KPP_COL0__UART4_RXD_MUX 0x1b8 0x3b0 0x570 0x11 0x001 +#define MX25_PAD_KPP_COL0__UART4_RXD 0x1b8 0x3b0 0x570 0x11 0x001 #define MX25_PAD_KPP_COL0__AUD5_TXD 0x1b8 0x3b0 0x000 0x12 0x000 #define MX25_PAD_KPP_COL0__GPIO_3_1 0x1b8 0x3b0 0x000 0x15 0x000 #define MX25_PAD_KPP_COL1__KPP_COL1 0x1bc 0x3b4 0x000 0x10 0x000 -#define MX25_PAD_KPP_COL1__UART4_TXD_MUX 0x1bc 0x3b4 0x000 0x11 0x000 +#define MX25_PAD_KPP_COL1__UART4_TXD 0x1bc 0x3b4 0x000 0x11 0x000 #define MX25_PAD_KPP_COL1__AUD5_RXD 0x1bc 0x3b4 0x000 0x12 0x000 #define MX25_PAD_KPP_COL1__GPIO_3_2 0x1bc 0x3b4 0x000 0x15 0x000 -#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x10 0x000 -#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x000 0x11 0x000 -#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x12 0x000 -#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x15 0x000 +#define MX25_PAD_KPP_COL2__KPP_COL2 0x1c0 0x3b8 0x000 0x00 0x000 +#define MX25_PAD_KPP_COL2__UART4_RTS 0x1c0 0x3b8 0x56c 0x01 0x001 +#define MX25_PAD_KPP_COL2__AUD5_TXC 0x1c0 0x3b8 0x000 0x02 0x000 +#define MX25_PAD_KPP_COL2__GPIO_3_3 0x1c0 0x3b8 0x000 0x05 0x000 #define MX25_PAD_KPP_COL3__KPP_COL3 0x1c4 0x3bc 0x000 0x10 0x000 #define MX25_PAD_KPP_COL3__UART4_CTS 0x1c4 0x3bc 0x000 0x11 0x000 @@ -557,9 +571,10 @@ #define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK 0x210 0x000 0x000 0x10 0x000 #define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 0x210 0x000 0x000 0x15 0x000 -#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000 -#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000 -#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000 +#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x00 0x000 +#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x04 0x000 +#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x05 0x000 +#define MX25_PAD_VSTBY_REQ__UART4_RTS 0x214 0x408 0x56c 0x06 0x002 #define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000 #define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000 @@ -567,6 +582,7 @@ #define MX25_PAD_POWER_FAIL__POWER_FAIL 0x21c 0x410 0x000 0x10 0x000 #define MX25_PAD_POWER_FAIL__AUD7_RXD 0x21c 0x410 0x478 0x14 0x001 #define MX25_PAD_POWER_FAIL__GPIO_3_19 0x21c 0x410 0x000 0x15 0x000 +#define MX25_PAD_POWER_FAIL__UART4_CTS 0x21c 0x410 0x000 0x16 0x000 #define MX25_PAD_CLKO__CLKO 0x220 0x414 0x000 0x10 0x000 #define MX25_PAD_CLKO__GPIO_2_21 0x220 0x414 0x000 0x15 0x000 diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi index 759cc56253dd..6cebaa6b8833 100644 --- a/arch/arm/boot/dts/imx28-m28.dtsi +++ b/arch/arm/boot/dts/imx28-m28.dtsi @@ -27,32 +27,6 @@ pinctrl-names = "default"; pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>; status = "okay"; - - partition@0 { - label = "bootloader"; - reg = <0x00000000 0x00300000>; - read-only; - }; - - partition@1 { - label = "environment"; - reg = <0x00300000 0x00080000>; - }; - - partition@2 { - label = "redundant-environment"; - reg = <0x00380000 0x00080000>; - }; - - partition@3 { - label = "kernel"; - reg = <0x00400000 0x00400000>; - }; - - partition@4 { - label = "filesystem"; - reg = <0x00800000 0x0f800000>; - }; }; }; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index f637ec900cc8..74aa151cdb45 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -434,6 +434,32 @@ fsl,pull-up = <MXS_PULL_ENABLE>; }; + mac0_pins_b: mac0@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_MDC__ENET0_MDC + MX28_PAD_ENET0_MDIO__ENET0_MDIO + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN + MX28_PAD_ENET0_RXD0__ENET0_RXD0 + MX28_PAD_ENET0_RXD1__ENET0_RXD1 + MX28_PAD_ENET0_RXD2__ENET0_RXD2 + MX28_PAD_ENET0_RXD3__ENET0_RXD3 + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN + MX28_PAD_ENET0_TXD0__ENET0_TXD0 + MX28_PAD_ENET0_TXD1__ENET0_TXD1 + MX28_PAD_ENET0_TXD2__ENET0_TXD2 + MX28_PAD_ENET0_TXD3__ENET0_TXD3 + MX28_PAD_ENET_CLK__CLKCTRL_ENET + MX28_PAD_ENET0_COL__ENET0_COL + MX28_PAD_ENET0_CRS__ENET0_CRS + MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK + MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + mac1_pins_a: mac1@0 { reg = <0>; fsl,pinmux-ids = < diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 5fdb222636a7..1ce7ae94e7ad 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -69,6 +69,14 @@ status = "disabled"; }; + kpp: kpp@43fa8000 { + compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; + reg = <0x43fa8000 0x4000>; + interrupts = <24>; + clocks = <&clks 46>; + status = "disabled"; + }; + uart4: serial@43fb0000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43fb0000 0x4000>; diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 14e1320d9f84..490b7b44f1e7 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -137,6 +137,14 @@ status = "disabled"; }; + kpp: kpp@43fa8000 { + compatible = "fsl,imx35-kpp", "fsl,imx21-kpp"; + reg = <0x43fa8000 0x4000>; + interrupts = <24>; + clocks = <&clks 56>; + status = "disabled"; + }; + iomuxc: iomuxc@43fac000 { compatible = "fsl,imx35-iomuxc"; reg = <0x43fac000 0x4000>; diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index 53f40885c530..dcee1e0f968f 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -84,6 +84,15 @@ regulator-max-microvolt = <5000000>; gpio = <&gpio1 2 0>; }; + + reg_usb_otg_vbus: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 0>; + }; }; sound { @@ -168,6 +177,12 @@ >; }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX53_PAD_GPIO_4__GPIO1_4 0x000b0 + >; + }; + led_pin_gpio: led_gpio@0 { fsl,pins = < MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000 @@ -351,6 +366,10 @@ }; &usbotg { - dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + vbus-supply = <®_usb_otg_vbus>; + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 5111f5170d53..bfbed52ce1bd 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -114,7 +114,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts index 913bb9a0466a..063fe7510da5 100644 --- a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts +++ b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts @@ -1,12 +1,42 @@ /* - * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8034.dts b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts new file mode 100644 index 000000000000..ff8f7b1c4282 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6s-8034.dts @@ -0,0 +1,237 @@ +/* + * Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6S-8034 Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; + + aliases { + display = &display; + ipu1 = &ipu1; + }; + + cpus { + /delete-node/ cpu@1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_pwr>; + enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_lcd1_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_2>; + interface-pix-fmt = "rgb24"; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + display-timings { + native-mode = <&vga>; + + vga: VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ds1339 { + status = "disabled"; +}; + +&pinctrl_usdhc1 { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ + >; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +®_lcd0_pwr { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6s-8035.dts b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts new file mode 100644 index 000000000000..f988950e9443 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6s-8035.dts @@ -0,0 +1,253 @@ +/* + * Copyright 2015-2016 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6S-8035 Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; + + aliases { + display = &display; + ipu1 = &ipu1; + }; + + cpus { + /delete-node/ cpu@1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_pwr>; + enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_lcd1_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_2>; + interface-pix-fmt = "rgb24"; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + display-timings { + native-mode = <&vga>; + + vga: VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +®_lcd0_pwr { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts index 5fe465c2814e..b7a72840b7f0 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts @@ -1,12 +1,42 @@ /* - * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-8033.dts b/arch/arm/boot/dts/imx6dl-tx6u-8033.dts new file mode 100644 index 000000000000..4d3204a56f46 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6u-8033.dts @@ -0,0 +1,248 @@ +/* + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-8033 Module"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; + + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_pwr>; + enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_lcd1_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_2>; + interface-pix-fmt = "rgb24"; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + display-timings { + native-mode = <&vga>; + + vga: VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +®_lcd0_pwr { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts index d35a5cdc3229..5e0c6bb49f37 100644 --- a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts +++ b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts @@ -1,12 +1,42 @@ /* - * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -81,16 +111,6 @@ }; }; -&iomuxc { - imx6dl-tx6u-811x { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; - }; -}; - &kpp { status = "disabled"; /* pad conflict with backlight1 PWM */ }; @@ -148,3 +168,11 @@ &pwm1 { status = "okay"; }; + +&iomuxc { + pinctrl_eeti: eetigrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts b/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts new file mode 100644 index 000000000000..b9a783f7160e --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-tx6u-81xx-mb7.dts @@ -0,0 +1,255 @@ +/* + * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6U-81xx Module on MB7 baseboard"; + compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl"; + + aliases { + display = &lvds0; + lvds0 = &lvds0; + lvds1 = &lvds1; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_lcd0_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_lcd1_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&i2c3 { + polytouch1: eeti@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eeti>; + interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; +}; + +&kpp { + status = "disabled"; /* pads partially clash with backlight1 PWM */ +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&lvds0_timing1>; + + lvds0_timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + lvds0_timing1: VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <31>; + vfront-porch = <12>; + hsync-len = <96>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + lvds0_timing2: nl12880bc20 { + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hfront-porch = <50>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <60>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + + lvds1: lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&lvds1_timing2>; + + lvds1_timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + lvds1_timing1: VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <31>; + vfront-porch = <12>; + hsync-len = <96>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + lvds1_timing2: nl12880bc20 { + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hfront-porch = <50>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <60>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_eeti: eetigrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index c13a73aa55ca..9a4c22c2dade 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -30,7 +30,7 @@ /* kHz uV */ 996000 1250000 792000 1175000 - 396000 1075000 + 396000 1150000 >; fsl,soc-operating-points = < /* ARM kHz SOC-PU uV */ diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 2cba82d0d859..8e3e1466cc6f 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -80,6 +80,47 @@ }; }; + lcd_display: display@di0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di0_disp1>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; @@ -169,6 +210,10 @@ }; }; +&ipu1_di0_disp1 { + remote-endpoint = <&lcd_display_in>; +}; + &ldb { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts index 3101be5bafa7..f0a2be5268e3 100644 --- a/arch/arm/boot/dts/imx6q-b450v3.dts +++ b/arch/arm/boot/dts/imx6q-b450v3.dts @@ -65,11 +65,14 @@ }; }; -&ldb { +&clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ldb { status = "okay"; lvds0: lvds-channel@0 { diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts index 823f55ccb60f..33cb71acadcc 100644 --- a/arch/arm/boot/dts/imx6q-b650v3.dts +++ b/arch/arm/boot/dts/imx6q-b650v3.dts @@ -65,11 +65,14 @@ }; }; -&ldb { +&clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PLL3_USB_OTG>; +}; + +&ldb { status = "okay"; lvds0: lvds-channel@0 { diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts index 984d00000403..167f7446722a 100644 --- a/arch/arm/boot/dts/imx6q-b850v3.dts +++ b/arch/arm/boot/dts/imx6q-b850v3.dts @@ -51,25 +51,20 @@ chosen { stdout-path = &uart3; }; +}; - panel-lvds0 { - compatible = "auo,b133htn01"; - backlight = <&backlight_lvds>; - ddc-i2c-bus = <&mux2_i2c2>; - - port { - panel_in_lvds0: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; +&clks { + assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>, + <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_PFD2_396M>; }; &ldb { - assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, - <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; fsl,dual-channel; status = "okay"; @@ -77,14 +72,6 @@ fsl,data-mapping = "spwg"; fsl,data-width = <24>; status = "okay"; - - port@4 { - reg = <4>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_in_lvds0>; - }; - }; }; }; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index 8f6e6035f3f7..f7e17e2004ac 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -323,6 +323,8 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + fsl,tx-swing-full = <103>; + fsl,tx-swing-low = <103>; status = "okay"; }; @@ -335,7 +337,7 @@ &pwm2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm2>; - status = "okay"; + status = "disabled"; }; &sata { @@ -390,7 +392,6 @@ pinctrl-0 = <&pinctrl_usdhc3 &pinctrl_usdhc3_reset>; bus-width = <8>; vmmc-supply = <&vdd_bperi>; - vqmmc-supply = <&vdd_bio>; non-removable; keep-power-in-suspend; status = "okay"; @@ -399,6 +400,7 @@ &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; }; &iomuxc { diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index a51834e1dd27..0511137d1e23 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -327,7 +327,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <&sw4_reg>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts new file mode 100644 index 000000000000..3f8013c85fb9 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-marsboard.dts @@ -0,0 +1,403 @@ +/* + * Copyright (C) 2016 Sergio Prado (sergio.prado@e-labworks.com) + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Embest MarS Board i.MX6Dual"; + compatible = "embest,imx6q-marsboard", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x40000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user1 { + label = "imx6:green:user1"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "heartbeat"; + }; + + user2 { + label = "imx6:green:user2"; + gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + fsl,spi-num-chipselects = <1>; + status = "okay"; + + m25p80@0 { + compatible = "microchip,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + non-removable; + status = "okay"; +}; + +&iomuxc { + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x000b1 /* CS0 */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 + /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 + /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 + /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + /* AR8035 pin strapping: MODE#0: pull down */ + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 + /* GPIO16 -> AR8035 25MHz */ + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + /* RGMII_nRST */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 + /* AR8035 interrupt */ + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* LED1 */ + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* LED2 */ + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* USB OTG POWER ENABLE */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* CD */ + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* WP */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17009 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10009 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17009 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17009 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17009 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17009 + MX6QDL_PAD_SD3_RST__SD3_RESET 0x17009 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 0da81bc2c68a..1926b1348a62 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -141,7 +141,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -159,7 +159,7 @@ status = "okay"; sgtl5000: sgtl5000@0a { - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; compatible = "fsl,sgtl5000"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts index b18fae10b2e3..65e95ae7509a 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts @@ -1,12 +1,42 @@ /* - * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts index b58ec9c966c8..20cd0e7b3e21 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1010.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1010.dts @@ -1,12 +1,42 @@ /* - * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts index 0bb9a9de62a9..9ed243b704ff 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts @@ -1,12 +1,42 @@ /* - * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -94,22 +124,6 @@ status = "disabled"; }; -&iomuxc { - imx6qdl-tx6 { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; - }; -}; - &ipu1_di0_disp0 { remote-endpoint = <&display0_in>; }; @@ -134,3 +148,17 @@ fsl,wp-controller; status = "okay"; }; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts index b96d80a35d39..347b531d3763 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1020.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1020.dts @@ -1,12 +1,42 @@ /* - * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -180,22 +210,6 @@ status = "disabled"; }; -&iomuxc { - imx6qdl-tx6 { - pinctrl_usdhc4: usdhc4grp { - fsl,pins = < - MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 - MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 - MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 - MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 - MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 - MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 - MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 - >; - }; - }; -}; - &ipu1_di0_disp0 { remote-endpoint = <&display0_in>; }; @@ -208,3 +222,17 @@ fsl,wp-controller; status = "okay"; }; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1036.dts b/arch/arm/boot/dts/imx6q-tx6q-1036.dts new file mode 100644 index 000000000000..7c152e32758c --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-1036.dts @@ -0,0 +1,252 @@ +/* + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1036 Module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; + + aliases { + display = &display; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_pwr>; + enable-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + power-supply = <®_lcd1_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + display: display@di0 { + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_2>; + interface-pix-fmt = "rgb24"; + status = "okay"; + + port { + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + display-timings { + native-mode = <&vga>; + + vga: VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ds1339 { + status = "disabled"; +}; + +&gpmi { + status = "disabled"; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&ipu2 { + status = "disabled"; +}; + +®_lcd0_pwr { + status = "disabled"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <4>; + non-removable; + no-1-8-v; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1 + MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-1110.dts b/arch/arm/boot/dts/imx6q-tx6q-1110.dts index 2792da93db1f..0433e220a931 100644 --- a/arch/arm/boot/dts/imx6q-tx6q-1110.dts +++ b/arch/arm/boot/dts/imx6q-tx6q-1110.dts @@ -1,12 +1,42 @@ /* - * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -81,16 +111,6 @@ }; }; -&iomuxc { - imx6q-tx6q-1110 { - pinctrl_eeti: eetigrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ - >; - }; - }; -}; - &kpp { status = "disabled"; /* pad conflict with backlight1 PWM */ }; @@ -152,3 +172,11 @@ &sata { status = "okay"; }; + +&iomuxc { + pinctrl_eeti: eetigrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts b/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts new file mode 100644 index 000000000000..d78b129d01ea --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tx6q-11x0-mb7.dts @@ -0,0 +1,264 @@ +/* + * Copyright 2016 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-tx6.dtsi" + +/ { + model = "Ka-Ro electronics TX6Q-1110/-1130 Module on MB7 baseboard"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; + + aliases { + display = &lvds0; + ipu1 = &ipu2; + lvds0 = &lvds0; + lvds1 = &lvds1; + }; + + backlight0: backlight0 { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_lcd0_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_lcd1_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; +}; + +&can1 { + status = "disabled"; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&i2c3 { + polytouch1: eeti@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eeti>; + interrupts-extended = <&gpio3 22 IRQ_TYPE_EDGE_FALLING>; + wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; +}; + +&ipu2 { + status = "disabled"; +}; + +&kpp { + status = "disabled"; /* pads partially clash with backlight1 PWM */ +}; + +&ldb { + status = "okay"; + + lvds0: lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&lvds0_timing1>; + + lvds0_timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + lvds0_timing1: VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <31>; + vfront-porch = <12>; + hsync-len = <96>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + lvds0_timing2: nl12880bc20 { + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hfront-porch = <50>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <60>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; + + lvds1: lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&lvds1_timing2>; + + lvds1_timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + lvds1_timing1: VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + vback-porch = <31>; + vfront-porch = <12>; + hsync-len = <96>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + lvds1_timing2: nl12880bc20 { + clock-frequency = <71000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <50>; + hfront-porch = <50>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <60>; + vsync-len = <13>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&iomuxc { + pinctrl_eeti: eetigrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index cd10c8de1904..c30c8368cae0 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -154,22 +154,22 @@ #size-cells = <0>; reg = <2>; - ipu2_di0_disp0: endpoint@0 { + ipu2_di0_disp0: disp0-endpoint { }; - ipu2_di0_hdmi: endpoint@1 { + ipu2_di0_hdmi: hdmi-endpoint { remote-endpoint = <&hdmi_mux_2>; }; - ipu2_di0_mipi: endpoint@2 { + ipu2_di0_mipi: mipi-endpoint { remote-endpoint = <&mipi_mux_2>; }; - ipu2_di0_lvds0: endpoint@3 { + ipu2_di0_lvds0: lvds0-endpoint { remote-endpoint = <&lvds0_mux_2>; }; - ipu2_di0_lvds1: endpoint@4 { + ipu2_di0_lvds1: lvds1-endpoint { remote-endpoint = <&lvds1_mux_2>; }; }; @@ -179,19 +179,19 @@ #size-cells = <0>; reg = <3>; - ipu2_di1_hdmi: endpoint@1 { + ipu2_di1_hdmi: hdmi-endpoint { remote-endpoint = <&hdmi_mux_3>; }; - ipu2_di1_mipi: endpoint@2 { + ipu2_di1_mipi: mipi-endpoint { remote-endpoint = <&mipi_mux_3>; }; - ipu2_di1_lvds0: endpoint@3 { + ipu2_di1_lvds0: lvds0-endpoint { remote-endpoint = <&lvds0_mux_3>; }; - ipu2_di1_lvds1: endpoint@4 { + ipu2_di1_lvds1: lvds1-endpoint { remote-endpoint = <&lvds1_mux_3>; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index b33e5a95a0f0..922b1dd06fda 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -324,7 +324,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi index a8f3500ee522..865c9a264a43 100644 --- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi @@ -213,7 +213,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 8dd74e98ffd6..7191b84770b9 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -244,7 +244,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_1p8v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index ec3fe7444e15..40d06b09deba 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -237,7 +237,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_1p8v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 367cc49eea0d..d6dbe2a88ee6 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -328,7 +328,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <&sw4_reg>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index 24d7d3f18464..e456b5cc1b03 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -269,7 +269,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sgtl5000>; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index dc74aa395ff5..657da6b6ccd2 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -402,7 +402,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index c6c590d1e940..73915db704a0 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -304,7 +304,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi index a50356243888..cacf5933707d 100644 --- a/arch/arm/boot/dts/imx6qdl-rex.dtsi +++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi @@ -126,7 +126,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_3p3v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index 0f1aca450fe6..c47fe6c79b36 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -290,7 +290,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 0b5c4de74485..5248e7bd2b06 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -115,7 +115,7 @@ mux-ext-port = <3>; }; - backlight { + backlight_lvds: backlight-lvds { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -133,6 +133,17 @@ default-state = "on"; }; }; + + panel { + compatible = "hannstar,hsd100pxn1"; + backlight = <&backlight_lvds>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; }; &audmux { @@ -509,18 +520,11 @@ fsl,data-width = <18>; status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index efd06b576f1d..39b85aef93e1 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -1,12 +1,42 @@ /* - * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de> + * Copyright 2014-2016 Lothar Waßmann <LW@KARO-electronics.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ #include <dt-bindings/gpio/gpio.h> @@ -37,6 +67,7 @@ clocks { #address-cells = <1>; #size-cells = <0>; + mclk: clock@0 { compatible = "fixed-clock"; reg = <0>; @@ -61,109 +92,95 @@ user_led: user { label = "Heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_led>; gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3v3_etn: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3V3_ETN"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_etnphy_power>; - gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_3v3_etn: regulator-3v3-etn { + compatible = "regulator-fixed"; + regulator-name = "3V3_ETN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy_power>; + gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_2v5: regulator@1 { - compatible = "regulator-fixed"; - reg = <1>; - regulator-name = "2V5"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; + reg_2v5: regulator-2v5 { + compatible = "regulator-fixed"; + regulator-name = "2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; - reg_3v3: regulator@2 { - compatible = "regulator-fixed"; - reg = <2>; - regulator-name = "3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; - reg_can_xcvr: regulator@3 { - compatible = "regulator-fixed"; - reg = <3>; - regulator-name = "CAN XCVR"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan_xcvr>; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-low; - }; + reg_can_xcvr: regulator-can-xcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_xcvr>; + gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + enable-active-low; + }; - reg_lcd0_pwr: regulator@4 { - compatible = "regulator-fixed"; - reg = <4>; - regulator-name = "LCD0 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd0_pwr>; - gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; + reg_lcd0_pwr: regulator-lcd0-pwr { + compatible = "regulator-fixed"; + regulator-name = "LCD0 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd0_pwr>; + gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; - reg_lcd1_pwr: regulator@5 { - compatible = "regulator-fixed"; - reg = <5>; - regulator-name = "LCD1 POWER"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd1_pwr>; - gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-boot-on; - regulator-always-on; - }; + reg_lcd1_pwr: regulator-lcd1-pwr { + compatible = "regulator-fixed"; + regulator-name = "LCD1 POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd1_pwr>; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; - reg_usbh1_vbus: regulator@6 { - compatible = "regulator-fixed"; - reg = <6>; - regulator-name = "usbh1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh1_vbus>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_usbotg_vbus: regulator@7 { - compatible = "regulator-fixed"; - reg = <7>; - regulator-name = "usbotg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg_vbus>; - gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; }; sound { @@ -209,7 +226,7 @@ &gpio2 30 GPIO_ACTIVE_HIGH &gpio3 19 GPIO_ACTIVE_HIGH >; - status = "okay"; + status = "disabled"; spidev0: spi@0 { compatible = "spidev"; @@ -234,8 +251,22 @@ clock-names = "ipg", "ahb", "ptp", "enet_out"; phy-mode = "rmii"; phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; + phy-handle = <&etnphy>; phy-supply = <®_3v3_etn>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + etnphy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_mdio>; + interrupts-extended = <&gpio7 1 IRQ_TYPE_EDGE_FALLING>; + }; + }; }; &gpmi { @@ -301,310 +332,318 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; - imx6qdl-tx6 { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ - MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ - MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ - >; - }; + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */ + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */ + >; + }; - pinctrl_audmux: audmuxgrp { - fsl,pins = < - MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */ - MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */ - MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */ - MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */ - >; - }; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */ + MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */ + MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */ + MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */ + >; + }; - pinctrl_disp0_1: disp0grp-1 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; + pinctrl_disp0_1: disp0grp-1 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; - pinctrl_disp0_2: disp0grp-2 { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 - >; - }; + pinctrl_disp0_2: disp0grp-2 { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0 - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0 - MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0 - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */ - >; - }; + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0 + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0 + MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */ + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */ + >; + }; - pinctrl_edt_ft5x06: edt-ft5x06grp { - fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ - >; - }; + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */ + >; + }; - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 - MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 - MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 - >; - }; + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0 + >; + }; - pinctrl_etnphy_power: etnphy-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ - >; - }; + pinctrl_enet_mdio: enet-mdiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + >; + }; - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 - MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 - >; - }; + pinctrl_etnphy_power: etnphy-pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */ + >; + }; - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 - >; - }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 + >; + }; - pinctrl_flexcan_xcvr: flexcan-xcvrgrp { - fsl,pins = < - MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */ - >; - }; + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 + >; + }; - pinctrl_gpmi_nand: gpminandgrp { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 - >; - }; + pinctrl_flexcan_xcvr: flexcan-xcvrgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */ + >; + }; - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1 + >; + }; - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; - pinctrl_kpp: kppgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 - MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1 - MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1 - MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1 - MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1 - MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1 - MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1 - MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; - pinctrl_lcd0_pwr: lcd0-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */ - >; - }; + pinctrl_kpp: kppgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1 + MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1 + MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1 + MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1 + MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1 + MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1 + MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1 + MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1 + >; + }; - pinctrl_lcd1_pwr: lcd1-pwrgrp { - fsl,pins = < - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */ - >; - }; + pinctrl_lcd0_pwr: lcd0-pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */ + >; + }; - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 - >; - }; + pinctrl_lcd1_pwr: lcd-pwrgrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */ + >; + }; - pinctrl_pwm2: pwm2grp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 - >; - }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; - pinctrl_tsc2007: tsc2007grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */ - >; - }; + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1 + >; + }; - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 - >; - }; + pinctrl_tsc2007: tsc2007grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */ + >; + }; - pinctrl_uart1_rtscts: uart1_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart1_rtscts: uart1_rtsctsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1 + >; + }; - pinctrl_uart2_rtscts: uart2_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 - MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 - >; - }; + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - >; - }; + pinctrl_uart2_rtscts: uart2_rtsctsgrp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + >; + }; - pinctrl_uart3_rtscts: uart3_rtsctsgrp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 - MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 - >; - }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; - pinctrl_usbh1_vbus: usbh1-vbusgrp { - fsl,pins = < - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */ - >; - }; + pinctrl_uart3_rtscts: uart3_rtsctsgrp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1 + >; + }; - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059 - >; - }; + pinctrl_usbh1_vbus: usbh1-vbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */ + >; + }; - pinctrl_usbotg_vbus: usbotg-vbusgrp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */ - >; - }; + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059 + >; + }; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 - MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ - >; - }; + pinctrl_usbotg_vbus: usbotg-vbusgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */ + >; + }; - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1 - MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */ - >; - }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1 + MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1 + MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */ + >; + }; + + pinctrl_user_led: user-ledgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */ + >; }; }; @@ -649,19 +688,22 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; + fsl,uart-has-rtscts; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; + fsl,uart-has-rtscts; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>; + fsl,uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index d3e54e40a017..3bee2f910067 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -10,14 +10,49 @@ */ / { + aliases { + backlight = &backlight; + panelchan = &panelchan; + panel7 = &panel7; + touchscreenp7 = &touchscreenp7; + }; + chosen { stdout-path = &uart2; }; + backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&gpio1 4 0>; + default-on; + status = "disabled"; + }; + memory { reg = <0x10000000 0x40000000>; }; + panel7: panel7 { + /* + * in reality it is a -20t (parallel) model, + * but with LVDS bridge chip attached, + * so it is equivalent to -19t model in drive + * characteristics + */ + compatible = "urt,umsh-8596md-19t"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + power-supply = <®_panel>; + backlight = <&backlight>; + status = "disabled"; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -33,6 +68,14 @@ startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */ gpio = <&gpio7 12 0>; }; + + reg_panel: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "lcd_panel"; + enable-active-high; + gpio = <&gpio1 2 0>; + }; }; sound { @@ -67,6 +110,24 @@ status = "okay"; }; +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + touchscreenp7: touchscreenp7@55 { + compatible = "sitronix,st1232"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreenp7>; + reg = <0x55>; + interrupt-parent = <&gpio1>; + interrupts = <13 8>; + gpios = <&gpio1 15 0>; + status = "disabled"; + }; +}; + &iomuxc { imx6q-udoo { pinctrl_enet: enetgrp { @@ -97,6 +158,27 @@ >; }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001f8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x70 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x70 + >; + }; + + pinctrl_touchscreenp7: touchscreenp7grp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x70 + MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 @@ -154,6 +236,20 @@ }; }; +&ldb { + status = "okay"; + + panelchan: lvds-channel@0 { + port@4 { + reg = <4>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; @@ -164,7 +260,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh>; vbus-supply = <®_usb_h1_vbus>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 9e096d811bed..8e7c40e114dd 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -85,7 +85,7 @@ codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index b42822aa14f2..ed613ebe0812 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -621,7 +621,7 @@ <0 54 IRQ_TYPE_LEVEL_HIGH>, <0 127 IRQ_TYPE_LEVEL_HIGH>; - regulator-1p1@110 { + regulator-1p1 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p1"; regulator-min-microvolt = <800000>; @@ -635,7 +635,7 @@ anatop-max-voltage = <1375000>; }; - regulator-3p0@120 { + regulator-3p0 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; regulator-min-microvolt = <2800000>; @@ -649,7 +649,7 @@ anatop-max-voltage = <3400000>; }; - regulator-2p5@130 { + regulator-2p5 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd2p5"; regulator-min-microvolt = <2000000>; @@ -663,7 +663,7 @@ anatop-max-voltage = <2750000>; }; - reg_arm: regulator-vddcore@140 { + reg_arm: regulator-vddcore { compatible = "fsl,anatop-regulator"; regulator-name = "vddarm"; regulator-min-microvolt = <725000>; @@ -680,7 +680,7 @@ anatop-max-voltage = <1450000>; }; - reg_pu: regulator-vddpu@140 { + reg_pu: regulator-vddpu { compatible = "fsl,anatop-regulator"; regulator-name = "vddpu"; regulator-min-microvolt = <725000>; @@ -697,7 +697,7 @@ anatop-max-voltage = <1450000>; }; - reg_soc: regulator-vddsoc@140 { + reg_soc: regulator-vddsoc { compatible = "fsl,anatop-regulator"; regulator-name = "vddsoc"; regulator-min-microvolt = <725000>; @@ -1230,22 +1230,22 @@ #size-cells = <0>; reg = <2>; - ipu1_di0_disp0: endpoint@0 { + ipu1_di0_disp0: disp0-endpoint { }; - ipu1_di0_hdmi: endpoint@1 { + ipu1_di0_hdmi: hdmi-endpoint { remote-endpoint = <&hdmi_mux_0>; }; - ipu1_di0_mipi: endpoint@2 { + ipu1_di0_mipi: mipi-endpoint { remote-endpoint = <&mipi_mux_0>; }; - ipu1_di0_lvds0: endpoint@3 { + ipu1_di0_lvds0: lvds0-endpoint { remote-endpoint = <&lvds0_mux_0>; }; - ipu1_di0_lvds1: endpoint@4 { + ipu1_di0_lvds1: lvds1-endpoint { remote-endpoint = <&lvds1_mux_0>; }; }; @@ -1255,22 +1255,22 @@ #size-cells = <0>; reg = <3>; - ipu1_di0_disp1: endpoint@0 { + ipu1_di0_disp1: disp1-endpoint { }; - ipu1_di1_hdmi: endpoint@1 { + ipu1_di1_hdmi: hdmi-endpoint { remote-endpoint = <&hdmi_mux_1>; }; - ipu1_di1_mipi: endpoint@2 { + ipu1_di1_mipi: mipi-endpoint { remote-endpoint = <&mipi_mux_1>; }; - ipu1_di1_lvds0: endpoint@3 { + ipu1_di1_lvds0: lvds0-endpoint { remote-endpoint = <&lvds0_mux_1>; }; - ipu1_di1_lvds1: endpoint@4 { + ipu1_di1_lvds1: lvds1-endpoint { remote-endpoint = <&lvds1_mux_1>; }; }; diff --git a/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts new file mode 100644 index 000000000000..a39b86036581 --- /dev/null +++ b/arch/arm/boot/dts/imx6qp-nitrogen6_max.dts @@ -0,0 +1,59 @@ +/* + * Copyright 2016 Boundary Devices, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6qp.dtsi" +#include "imx6qdl-nitrogen6_max.dtsi" + +/ { + model = "Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX Board"; + compatible = "boundary,imx6qp-nitrogen6_max", "fsl,imx6qp"; +}; + +&pcie { + status = "disabled"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts new file mode 100644 index 000000000000..ba62348d8284 --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts @@ -0,0 +1,709 @@ +/* + * Copyright (C) 2016 Boundary Devices, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board"; + compatible = "boundary,imx6sx-nitrogen6sx", "fsl,imx6sx"; + + aliases { + fb_lcd = &lcdif1; + t_lcd = &t_lcd; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + backlight-lvds { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + power-supply = <®_3p3v>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can1_3v3: regulator-can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: regulator-can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 24 GPIO_ACTIVE_LOW>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_wlan: regulator-wlan { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wlan>; + compatible = "regulator-fixed"; + clocks = <&clks IMX6SX_CLK_CKO>; + clock-names = "slow"; + regulator-name = "wlan-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <70000>; + gpio = <&gpio7 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6sx-nitrogen6sx-sgtl5000"; + cpu-dai = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <5>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + flash: m25p80@0 { + compatible = "microchip,sst25vf016b"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x0 0xc0000>; + read-only; + }; + + partition@c0000 { + label = "env"; + reg = <0xc0000 0x2000>; + read-only; + }; + + partition@c2000 { + label = "Kernel"; + reg = <0xc2000 0x11e000>; + }; + + partition@1e0000 { + label = "M4"; + reg = <0x1e0000 0x20000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + phy-supply = <®_3p3v>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@4 { + reg = <4>; + }; + + ethphy2: ethernet-phy@5 { + reg = <5>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rgmii"; + phy-handle = <ðphy2>; + phy-supply = <®_3p3v>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clks IMX6SX_CLK_CKO2>; + VDDA-supply = <®_1p8v>; + VDDIO-supply = <®_1p8v>; + VDDD-supply = <®_1p8v>; + assigned-clocks = <&clks IMX6SX_CLK_CKO2_SEL>, + <&clks IMX6SX_CLK_CKO2>; + assigned-clock-parents = <&clks IMX6SX_CLK_OSC>; + assigned-clock-rates = <0>, <24000000>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif1>; + lcd-supply = <®_3p3v>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&t_lcd>; + t_lcd: t_lcd_default { + clock-frequency = <74160000>; + hactive = <1280>; + vactive = <720>; + hback-porch = <220>; + hfront-porch = <110>; + vback-porch = <20>; + vfront-porch = <5>; + hsync-len = <40>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + dr_mode = "host"; + disable-over-current; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + non-removable; + keep-power-in-suspend; + vmmc-supply = <®_wlan>; + cap-power-off-card; + cap-sdio-irq; + status = "okay"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio7>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + }; + + wlcore: wlcore@2 { + compatible = "ti,wl1271"; + reg = <2>; + interrupt-parent = <&gpio7>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + ref-clock-frequency = <38400000>; + }; +}; + +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_50mhz>; + pinctrl-1 = <&pinctrl_usdhc4_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_200mhz>; + bus-width = <8>; + non-removable; + vmmc-supply = <®_1p8v>; + keep-power-in-suspend; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x1b0b0 + MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x1b0b0 + MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x1b0b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 + MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 + MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x0b0b1 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x1b0b0 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x1b0b0 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x30b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x30b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x30b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x30b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x30b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x30b1 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0xb0b0 + MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0xb0b0 + MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0xb0b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x30b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x30b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x30b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x30b1 + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x30b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x30b1 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0xb0b0 + MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0xb0b0 + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0xb0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x0b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x1b0b0 + MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x1b0b0 + MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x1b0b0 + MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x1b0b0 + MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x1b0b0 + MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x1b0b0 + MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x000b0 + MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x1b0b0 + /* Test points */ + MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x1b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_lcdif1: lcdif1grp { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0xb0b0 + MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0xb0b0 + MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0xb0b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_reg_wlan: reg-wlangrp { + fsl,pins = < + MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x1b0b0 + MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x000b0 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x000b0 + MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x1b0b0 + MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0xb0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x1b0b1 + MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x1b0b1 + MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x1b0b0 + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x170b1 + >; + }; + + pinctrl_usbotg1_vbus: usbotg1-vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x1b0b0 + >; + }; + + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0xb0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x1b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17071 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17071 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17071 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17071 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17071 + >; + }; + + pinctrl_usdhc4_50mhz: usdhc4-50mhzgrp { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 + >; + }; + + pinctrl_usdhc4_100mhz: usdhc4-100mhzgrp { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_200mhz: usdhc4-200mhzgrp { + fsl,pins = < + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb-sai.dts b/arch/arm/boot/dts/imx6sx-sdb-sai.dts new file mode 100644 index 000000000000..0155450d680e --- /dev/null +++ b/arch/arm/boot/dts/imx6sx-sdb-sai.dts @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2016 NXP Semiconductors + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "imx6sx-sdb.dts" + +/ { + sound { + audio-cpu = <&sai1>; + }; +}; + +&audmux { + /* pin conflict with sai */ + status = "disabled"; +}; + +&sai1 { + status = "okay"; +}; + +&sdma { + gpr = <&gpr>; + /* SDMA event remap for SAI1 */ + fsl,sdma-event-remap = <0 15 1>, <0 16 1>; +}; + +&ssi2 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index 0ad164ab5729..5bb8fd57e7f5 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -18,12 +18,14 @@ 996000 1250000 792000 1175000 396000 1175000 + 198000 1175000 >; fsl,soc-operating-points = < /* ARM kHz SOC uV */ 996000 1250000 792000 1175000 396000 1175000 + 198000 1175000 >; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi index f1d37306e8bf..e5eafe4d9a70 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi @@ -254,6 +254,12 @@ status = "okay"; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "disabled"; +}; + &ssi2 { status = "okay"; }; @@ -468,6 +474,16 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130b0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130b0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120b0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130b0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index a5f76025a0ce..6a993bfda248 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -63,12 +63,14 @@ 996000 1250000 792000 1175000 396000 1075000 + 198000 975000 >; fsl,soc-operating-points = < /* ARM kHz SOC uV */ 996000 1175000 792000 1175000 396000 1175000 + 198000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX6SX_CLK_ARM>, @@ -970,8 +972,7 @@ <&clks 0>, <&clks 0>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; - dmas = <&sdma 31 23 0>, <&sdma 32 23 0>; - dma-source = <&gpr 0 15 0 16>; + dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; status = "disabled"; }; @@ -990,8 +991,7 @@ <&clks 0>, <&clks 0>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; - dmas = <&sdma 33 23 0>, <&sdma 34 23 0>; - dma-source = <&gpr 0 17 0 18>; + dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts index 720728001d3c..668a72997590 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts @@ -36,6 +36,45 @@ enable-active-high; }; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "mx6ul-wm8960"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Speaker", "SPK_LP", + "Speaker", "SPK_LN", + "Speaker", "SPK_RP", + "Speaker", "SPK_RN", + "LINPUT1", "Mic Jack", + "LINPUT3", "Mic Jack", + "RINPUT1", "Mic Jack", + "RINPUT2", "Mic Jack"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clks IMX6UL_CLK_SAI2>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; }; &cpu0 { @@ -43,6 +82,20 @@ soc-supply = <®_soc>; }; +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: wm8960@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8960"; + reg = <0x1a>; + wlf,shared-lrclk; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -86,6 +139,16 @@ }; }; +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + status = "okay"; +}; + &snvs_poweroff { status = "okay"; }; @@ -272,6 +335,17 @@ >; }; + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts new file mode 100644 index 000000000000..8ce1fec36e86 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -0,0 +1,516 @@ +/* + * Copyright 2015 Technexion Ltd. + * + * Author: Wig Cheng <wig.cheng@technexion.com> + * Richard Hu <richard.hu@technexion.com> + * Tapani Utriainen <tapani@technexion.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6ul.dtsi" + +/ { + model = "Technexion Pico i.MX6UL Board"; + compatible = "technexion,imx6ul-pico-hobbit", "fsl,imx6ul"; + + memory { + reg = <0x80000000 0x10000000>; + }; + + chosen { + stdout-path = &uart6; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 6 0>; + }; + + sound { + compatible = "fsl,imx-audio-sgtl5000"; + model = "imx6ul-sgtl5000"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + audio-routing = + "LINE_IN", "Line In Jack", + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + }; + + sys_mclk: clock-sys-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + leds { + compatible = "gpio-leds"; + + hobbitled { + label = "hobbitled"; + gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + phy-reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + phy-reset-duration = <11>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + max-speed = <100>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW 0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + /* VDD_ARM_SOC_IN*/ + sw1b_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* DRAM */ + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + /* DRAM */ + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec: sgtl5000@0a { + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&sys_mclk>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c3 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <33200000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <210>; + hback-porch = <46>; + hsync-len = <1>; + vback-porch = <22>; + vfront-porch = <23>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + status = "okay"; +}; + +&pwm8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm8>; + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc2 { /* Wifi SDIO */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x800 + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x79 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x4001b8b0 + MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* LCD reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm7: pwm7grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x110b0 + >; + }; + + pinctrl_pwm8: pwm8grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x110b0 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b0 + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b0 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts b/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts new file mode 100644 index 000000000000..8c2f3df79b47 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tx6ul-0010.dts @@ -0,0 +1,53 @@ +/* + * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-tx6ul.dtsi" + +/ { + model = "Ka-Ro electronics TXUL-0010 Module"; + compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; + + aliases { + /delete-property/ mmc1; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts b/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts new file mode 100644 index 000000000000..d82698e7d50f --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tx6ul-0011.dts @@ -0,0 +1,68 @@ +/* + * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-tx6ul.dtsi" + +/ { + model = "Ka-Ro electronics TXUL-0011 Module"; + compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; + + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc1; + }; +}; + +&gpmi { + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + no-1-8-v; + non-removable; + fsl,wp-controller; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts new file mode 100644 index 000000000000..d25899b71575 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts @@ -0,0 +1,271 @@ +/* + * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6ul.dtsi" +#include "imx6ul-tx6ul.dtsi" + +/ { + model = "Ka-Ro electronics TXUL-0010 Module on TXUL Mainboard"; + compatible = "karo,imx6ul-tx6ul", "fsl,imx6ul"; + + aliases { + lcdif_24bit_pins_a = &pinctrl_disp0_3; + mmc0 = &usdhc1; + /delete-property/ mmc1; + serial2 = &uart3; + serial4 = &uart5; + }; + /delete-node/ sound; +}; + +&can1 { + xceiver-supply = <®_3v3>; +}; + +&can2 { + xceiver-supply = <®_3v3>; +}; + +&ds1339 { + status = "disabled"; +}; + +&fec1 { + pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>; + /delete-node/ mdio; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + phy-supply = <®_3v3_etn>; + phy-handle = <&etnphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + etnphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy0_int>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpio5 5 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + + etnphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy1_int>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpio4 27 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + }; +}; + +&i2c_gpio { + status = "disabled"; +}; + +&i2c2 { + /delete-node/ codec@0a; + /delete-node/ touchscreen@48; + + rtc: mcp7940x@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; + +&kpp { + status = "disabled"; +}; + +&lcdif { + pinctrl-0 = <&pinctrl_disp0_3>; +}; + +®_usbotg_vbus{ + status = "disabled"; +}; + +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1>; + non-removable; + /delete-property/ cd-gpios; + cap-sdio-irq; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + /delete-property/ fsl,uart-has-rtscts; +}; + +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + /delete-property/ fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "disabled"; /* conflicts with LCDIF */ +}; + +&iomuxc { + hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x0b0b0 /* WLAN_RESET */ + >; + }; + + pinctrl_disp0_3: disp0grp-3 { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 + /* LCD_DATA08..09 not wired */ + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 + /* LCD_DATA16..17 not wired */ + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 + >; + }; + + pinctrl_enet2_mdio: enet2-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x0b0b0 + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x0b0b0 + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x0b0b0 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0b0b0 + MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi new file mode 100644 index 000000000000..437e9aad5920 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -0,0 +1,973 @@ +/* + * Copyright 2015 Lothar Waßmann <LW@KARO-electronics.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + aliases { + can0 = &can2; + can1 = &can1; + display = &display; + i2c0 = &i2c2; + i2c1 = &i2c_gpio; + i2c2 = &i2c1; + i2c3 = &i2c3; + i2c4 = &i2c4; + lcdif_23bit_pins_a = &pinctrl_disp0_1; + lcdif_24bit_pins_a = &pinctrl_disp0_2; + pwm0 = &pwm5; + reg_can_xcvr = ®_can_xcvr; + serial2 = &uart5; + serial4 = &uart3; + spi0 = &ecspi2; + spi1 = &spi_gpio; + stk5led = &user_led; + usbh1 = &usbotg2; + usbotg = &usbotg1; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0 0>; /* will be filled by U-Boot */ + }; + + clocks { + mclk: mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_rst>; + enable-gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>; + pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>; + power-supply = <®_lcd_pwr>; + /* + * a poor man's way to create a 1:1 relationship between + * the PWM value and the actual duty cycle + */ + brightness-levels = < 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100>; + default-brightness-level = <50>; + }; + + i2c_gpio: i2c-gpio { + compatible = "i2c-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_gpio>; + gpios = < + &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */ + &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */ + >; + clock-frequency = <400000>; + status = "okay"; + + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + status = "disabled"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led: user { + label = "Heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3v3_etn: regulator-3v3etn { + compatible = "regulator-fixed"; + regulator-name = "3V3_ETN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy_power>; + gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_2v5: regulator-2v5 { + compatible = "regulator-fixed"; + regulator-name = "2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_can_xcvr: regulator-canxcvr { + compatible = "regulator-fixed"; + regulator-name = "CAN XCVR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan_xcvr>; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + enable-active-low; + }; + + reg_lcd_pwr: regulator-lcdpwr { + compatible = "regulator-fixed"; + regulator-name = "LCD POWER"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwr>; + gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator-usbh1vbus { + compatible = "regulator-fixed"; + regulator-name = "usbh1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>; + gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usbotg_vbus: regulator-usbotgvbus { + compatible = "regulator-fixed"; + regulator-name = "usbotg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + spi_gpio: spi-gpio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi_gpio>; + gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>; + gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; + num-chipselects = <2>; + cs-gpios = < + &gpio1 29 GPIO_ACTIVE_HIGH + &gpio1 10 GPIO_ACTIVE_HIGH + >; + status = "disabled"; + + spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <660000>; + }; + + spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <660000>; + }; + }; + + sound { + compatible = "karo,imx6ul-tx6ul-sgtl5000", + "simple-audio-card"; + simple-audio-card,name = "imx6ul-tx6ul-sgtl5000-audio"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + + cpu_dai: simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + codec_dai: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_xcvr>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + fsl,spi-num-chipselects = <2>; + cs-gpios = < + &gpio1 29 GPIO_ACTIVE_HIGH + &gpio1 10 GPIO_ACTIVE_HIGH + >; + status = "disabled"; + + spidev0: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <60000000>; + }; + + spidev1: spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <60000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; + phy-supply = <®_3v3_etn>; + phy-handle = <&etnphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + etnphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy0_int>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + + etnphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_etnphy1_int>; + interrupt-parent = <&gpio4>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + status = "okay"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + phy-supply = <®_3v3_etn>; + phy-handle = <&etnphy1>; + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + fsl,no-blockmark-swap; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <400000>; + status = "okay"; + + sgtl5000: codec@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + VDDA-supply = <®_2v5>; + VDDIO-supply = <®_3v3>; + clocks = <&mclk>; + }; + + polytouch: polytouch@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; + wakeup-source; + }; + + touchscreen: touchscreen@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_NONE>; + gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + ti,x-plate-ohms = <660>; + wakeup-source; + }; +}; + +&kpp { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_kpp>; + /* sample keymap */ + /* row/col 0..3 are mapped to KPP row/col 4..7 */ + linux,keymap = < + MATRIX_KEY(4, 4, KEY_POWER) + MATRIX_KEY(4, 5, KEY_KP0) + MATRIX_KEY(4, 6, KEY_KP1) + MATRIX_KEY(4, 7, KEY_KP2) + MATRIX_KEY(5, 4, KEY_KP3) + MATRIX_KEY(5, 5, KEY_KP4) + MATRIX_KEY(5, 6, KEY_KP5) + MATRIX_KEY(5, 7, KEY_KP6) + MATRIX_KEY(6, 4, KEY_KP7) + MATRIX_KEY(6, 5, KEY_KP8) + MATRIX_KEY(6, 6, KEY_KP9) + >; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_disp0_1>; + lcd-supply = <®_lcd_pwr>; + display = <&display>; + status = "okay"; + + display: display@di0 { + bits-per-pixel = <32>; + bus-width = <24>; + status = "okay"; + + display-timings { + VGA { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hsync-len = <96>; + hfront-porch = <16>; + vback-porch = <31>; + vsync-len = <2>; + vfront-porch = <12>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ETV570 { + clock-frequency = <25200000>; + hactive = <640>; + vactive = <480>; + hback-porch = <114>; + hsync-len = <30>; + hfront-porch = <16>; + vback-porch = <32>; + vsync-len = <3>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0350 { + clock-frequency = <6413760>; + hactive = <320>; + vactive = <240>; + hback-porch = <34>; + hsync-len = <34>; + hfront-porch = <20>; + vback-porch = <15>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0430 { + clock-frequency = <9009000>; + hactive = <480>; + vactive = <272>; + hback-porch = <2>; + hsync-len = <41>; + hfront-porch = <2>; + vback-porch = <2>; + vsync-len = <10>; + vfront-porch = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + + ET0500 { + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ET0700 { /* same as ET0500 */ + clock-frequency = <33264000>; + hactive = <800>; + vactive = <480>; + hback-porch = <88>; + hsync-len = <128>; + hfront-porch = <40>; + vback-porch = <33>; + vsync-len = <2>; + vfront-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + ETQ570 { + clock-frequency = <6596040>; + hactive = <320>; + vactive = <240>; + hback-porch = <38>; + hsync-len = <30>; + hfront-porch = <30>; + vback-porch = <16>; + vsync-len = <3>; + vfront-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + #pwm-cells = <3>; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usbotg_vbus>; + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_usdhc1_cd>; + bus-width = <4>; + no-1-8-v; + cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + fsl,wp-controller; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */ + >; + }; + + pinctrl_disp0_1: disp0grp-1 { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ + /* PAD DISP0_DAT0 is used for the Flexcan transceiver control on STK5-v5 */ + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 + >; + }; + + pinctrl_disp0_2: disp0grp-2 { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ + MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */ + MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */ + MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */ + >; + }; + + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */ + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */ + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */ + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x000b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x000b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x000b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x000b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x000b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x000b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x000b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x400000b1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x000b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x000b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x000b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x000b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x000b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x000b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x000b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x400000b1 + >; + }; + + pinctrl_enet1_mdio: enet1-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + >; + }; + + pinctrl_etnphy_power: etnphy-pwrgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */ + >; + }; + + pinctrl_etnphy0_int: etnphy-intgrp-0 { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */ + >; + }; + + pinctrl_etnphy0_rst: etnphy-rstgrp-0 { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */ + >; + }; + + pinctrl_etnphy1_int: etnphy-intgrp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x0b0b0 /* ETN PHY INT */ + >; + }; + + pinctrl_etnphy1_rst: etnphy-rstgrp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0b0b0 /* ETN PHY RESET */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0 + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0 + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0 + >; + }; + + pinctrl_flexcan_xcvr: flexcan-xcvrgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */ + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_i2c_gpio: i2c-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */ + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1 + MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_kpp: kppgrp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0 + >; + }; + + pinctrl_lcd_pwr: lcd-pwrgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */ + >; + }; + + pinctrl_lcd_rst: lcd-rstgrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0 /* LCD Reset */ + >; + }; + + pinctrl_pwm5: pwm5grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */ + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */ + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */ + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */ + >; + }; + + pinctrl_spi_gpio: spi-gpiogrp { + fsl,pins = < + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */ + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */ + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */ + >; + }; + + pinctrl_tsc2007: tsc2007grp { + fsl,pins = < + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart1_rtscts: uart1-rtsctsgrp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0 + MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart2_rtscts: uart2-rtsctsgrp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0 + MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0 + >; + }; + + pinctrl_uart5_rtscts: uart5-rtsctsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0 + >; + }; + + pinctrl_usbh1_oc: usbh1-ocgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */ + >; + }; + + pinctrl_usbh1_vbus: usbh1-vbusgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */ + >; + }; + + pinctrl_usbotg_oc: usbotg-ocgrp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */ + >; + }; + + pinctrl_usbotg_vbus: usbotg-vbusgrp { + fsl,pins = < + MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 + >; + }; + + pinctrl_usdhc1_cd: usdhc1cdgrp { + fsl,pins = < + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1 + /* eMMC RESET */ + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 71778992f03d..4356b655ef02 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -55,15 +55,15 @@ clock-latency = <61036>; /* two CLK32 periods */ operating-points = < /* kHz uV */ - 528000 1250000 - 396000 1150000 - 198000 1150000 + 528000 1175000 + 396000 1025000 + 198000 950000 >; fsl,soc-operating-points = < /* KHz uV */ - 528000 1250000 - 396000 1150000 - 198000 1150000 + 528000 1175000 + 396000 1175000 + 198000 1175000 >; clocks = <&clks IMX6UL_CLK_ARM>, <&clks IMX6UL_CLK_PLL2_BUS>, diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi index d56d68fe7ffc..d56d68fe7ffc 100644 --- a/arch/arm/boot/dts/k2e-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-clocks.dtsi diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts index b7e99807f5c2..4c32ebc1425a 100644 --- a/arch/arm/boot/dts/k2e-evm.dts +++ b/arch/arm/boot/dts/keystone-k2e-evm.dts @@ -10,7 +10,7 @@ /dts-v1/; #include "keystone.dtsi" -#include "k2e.dtsi" +#include "keystone-k2e.dtsi" / { compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone"; diff --git a/arch/arm/boot/dts/k2e-netcp.dtsi b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi index ac990f679725..ac990f679725 100644 --- a/arch/arm/boot/dts/k2e-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2e-netcp.dtsi diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 1097dada56d2..96b349fb0430 100644 --- a/arch/arm/boot/dts/k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -44,7 +44,7 @@ }; soc { - /include/ "k2e-clocks.dtsi" + /include/ "keystone-k2e-clocks.dtsi" usb: usb@2680000 { interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; @@ -145,6 +145,6 @@ clock-names = "fck"; bus_freq = <2500000>; }; - /include/ "k2e-netcp.dtsi" + /include/ "keystone-k2e-netcp.dtsi" }; }; diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi index af9b7190533a..af9b7190533a 100644 --- a/arch/arm/boot/dts/k2hk-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk-clocks.dtsi diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts index 8161bf53271b..b38b3441818b 100644 --- a/arch/arm/boot/dts/k2hk-evm.dts +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts @@ -10,7 +10,7 @@ /dts-v1/; #include "keystone.dtsi" -#include "k2hk.dtsi" +#include "keystone-k2hk.dtsi" / { compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone"; diff --git a/arch/arm/boot/dts/k2hk-netcp.dtsi b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi index f86d6ddb832b..f86d6ddb832b 100644 --- a/arch/arm/boot/dts/k2hk-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk-netcp.dtsi diff --git a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/keystone-k2hk.dtsi index ada4c7ac96e7..8f67fa8df936 100644 --- a/arch/arm/boot/dts/k2hk.dtsi +++ b/arch/arm/boot/dts/keystone-k2hk.dtsi @@ -44,7 +44,7 @@ }; soc { - /include/ "k2hk-clocks.dtsi" + /include/ "keystone-k2hk-clocks.dtsi" dspgpio0: keystone_dsp_gpio@02620240 { compatible = "ti,keystone-dsp-gpio"; @@ -112,6 +112,6 @@ clock-names = "fck"; bus_freq = <2500000>; }; - /include/ "k2hk-netcp.dtsi" + /include/ "keystone-k2hk-netcp.dtsi" }; }; diff --git a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/keystone-k2l-clocks.dtsi index ef8464bb11ff..ef8464bb11ff 100644 --- a/arch/arm/boot/dts/k2l-clocks.dtsi +++ b/arch/arm/boot/dts/keystone-k2l-clocks.dtsi diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts index 00861244d788..7f9c2e94d605 100644 --- a/arch/arm/boot/dts/k2l-evm.dts +++ b/arch/arm/boot/dts/keystone-k2l-evm.dts @@ -10,7 +10,7 @@ /dts-v1/; #include "keystone.dtsi" -#include "k2l.dtsi" +#include "keystone-k2l.dtsi" / { compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone"; diff --git a/arch/arm/boot/dts/k2l-netcp.dtsi b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi index 5acbd0dcc2ab..5acbd0dcc2ab 100644 --- a/arch/arm/boot/dts/k2l-netcp.dtsi +++ b/arch/arm/boot/dts/keystone-k2l-netcp.dtsi diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi index 4446da72b0ae..ff22ffc3dee7 100644 --- a/arch/arm/boot/dts/k2l.dtsi +++ b/arch/arm/boot/dts/keystone-k2l.dtsi @@ -32,7 +32,7 @@ }; soc { - /include/ "k2l-clocks.dtsi" + /include/ "keystone-k2l-clocks.dtsi" uart2: serial@02348400 { compatible = "ns16550a"; @@ -92,7 +92,7 @@ clock-names = "fck"; bus_freq = <2500000>; }; - /include/ "k2l-netcp.dtsi" + /include/ "keystone-k2l-netcp.dtsi" }; }; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 3f272826f537..e34b2265458a 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -20,6 +20,9 @@ aliases { serial0 = &uart0; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; }; memory { @@ -59,6 +62,14 @@ <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; }; + psci { + compatible = "arm,psci"; + method = "smc"; + cpu_suspend = <0x84000001>; + cpu_off = <0x84000002>; + cpu_on = <0x84000003>; + }; + soc { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi index 9e6e9e2691d5..d573e03f3134 100644 --- a/arch/arm/boot/dts/kirkwood-6192.dtsi +++ b/arch/arm/boot/dts/kirkwood-6192.dtsi @@ -1,6 +1,6 @@ / { - mbus { - pciec: pcie-controller { + mbus@f1000000 { + pciec: pcie-controller@82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci"; diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi index 7dc7d6782e83..748d0b62f233 100644 --- a/arch/arm/boot/dts/kirkwood-6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-6281.dtsi @@ -1,6 +1,6 @@ / { - mbus { - pciec: pcie-controller { + mbus@f1000000 { + pciec: pcie-controller@82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci"; diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi index 4680eec990f0..bb63d2d50fc5 100644 --- a/arch/arm/boot/dts/kirkwood-6282.dtsi +++ b/arch/arm/boot/dts/kirkwood-6282.dtsi @@ -1,6 +1,6 @@ / { - mbus { - pciec: pcie-controller { + mbus@f1000000 { + pciec: pcie-controller@82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci"; diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi index 9e1f741d74ff..720c210d491d 100644 --- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi +++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi @@ -1,6 +1,6 @@ / { - mbus { - pciec: pcie-controller { + mbus@f1000000 { + pciec: pcie-controller@82000000 { compatible = "marvell,kirkwood-pcie"; status = "disabled"; device_type = "pci"; diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts index d2936ad3af1d..d091ecb61cd2 100644 --- a/arch/arm/boot/dts/kirkwood-b3.dts +++ b/arch/arm/boot/dts/kirkwood-b3.dts @@ -33,17 +33,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - /* Wifi model has Atheros chipset on pcie port */ - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pmx_button_power: pmx-button-power { @@ -199,3 +188,11 @@ }; }; +/* Wifi model has Atheros chipset on pcie port */ +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts index fa02a9aff05e..f16a73e49a88 100644 --- a/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts +++ b/arch/arm/boot/dts/kirkwood-blackarmor-nas220.dts @@ -36,13 +36,13 @@ gpio_keys { compatible = "gpio-keys"; - button@1{ + reset { label = "Reset"; linux,code = <KEY_POWER>; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - button@2{ + button { label = "Power"; linux,code = <KEY_SLEEP>; gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts index 7ec76566acf2..555b7e4c58a5 100644 --- a/arch/arm/boot/dts/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts @@ -60,7 +60,7 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + power { label = "Power push button"; linux,code = <KEY_POWER>; gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts index c39dd766c75a..aee6f02b1c80 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts @@ -17,14 +17,12 @@ / { model = "Marvell DB-88F6281-BP Development Board"; compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; +}; - mbus { - pcie-controller { - status = "okay"; +&pciec { + status = "okay"; +}; - pcie@1,0 { - status = "okay"; - }; - }; - }; +&pcie0 { + status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts index 701c6b6cdaa2..e8b23e13ec0c 100644 --- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts +++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts @@ -17,18 +17,16 @@ / { model = "Marvell DB-88F6282-BP Development Board"; compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; +}; - mbus { - pcie-controller { - status = "okay"; +&pciec { + status = "okay"; +}; - pcie@1,0 { - status = "okay"; - }; +&pcie0 { + status = "okay"; +}; - pcie@2,0 { - status = "okay"; - }; - }; - }; +&pcie1 { + status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts index 0473fcc260f7..41acbb6dd6ab 100644 --- a/arch/arm/boot/dts/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/kirkwood-dir665.dts @@ -25,16 +25,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pinctrl-0 =< &pmx_led_usb @@ -203,7 +193,7 @@ }; }; - dsa@0 { + dsa { compatible = "marvell,dsa"; #address-cells = <2>; #size-cells = <0>; @@ -276,3 +266,11 @@ &rtc { status = "disabled"; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi index 113dcf056dcf..d8fca9db46d0 100644 --- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi @@ -13,17 +13,17 @@ &pmx_button_reset>; pinctrl-names = "default"; - button@1 { + power { label = "Power button"; linux,code = <KEY_POWER>; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; }; - button@2 { + eject { label = "USB unmount button"; linux,code = <KEY_EJECTCD>; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - button@3 { + reset { label = "Reset button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts index 61f47fbe44d0..a85a4664431b 100644 --- a/arch/arm/boot/dts/kirkwood-ds111.dts +++ b/arch/arm/boot/dts/kirkwood-ds111.dts @@ -40,6 +40,6 @@ status = "okay"; }; -&pcie2 { +&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts index b84af3da8c84..6cef4bdbc01b 100644 --- a/arch/arm/boot/dts/kirkwood-ds112.dts +++ b/arch/arm/boot/dts/kirkwood-ds112.dts @@ -44,6 +44,10 @@ status = "okay"; }; -&pcie2 { +&pciec { + status = "okay"; +}; + +&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts index 99afd462f956..7f32e7abffac 100644 --- a/arch/arm/boot/dts/kirkwood-ds212.dts +++ b/arch/arm/boot/dts/kirkwood-ds212.dts @@ -43,6 +43,6 @@ status = "okay"; }; -&pcie2 { +&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts index 623cd4a37d71..72e58307416d 100644 --- a/arch/arm/boot/dts/kirkwood-ds411.dts +++ b/arch/arm/boot/dts/kirkwood-ds411.dts @@ -48,6 +48,10 @@ status = "okay"; }; -&pcie2 { +&pciec { + status = "okay"; +}; + +&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts index a0a1fad8b4de..aaaf31b81522 100644 --- a/arch/arm/boot/dts/kirkwood-ds411slim.dts +++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts @@ -44,6 +44,6 @@ status = "okay"; }; -&pcie2 { +&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts index bfa5edde179c..ef84d8699a76 100644 --- a/arch/arm/boot/dts/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts @@ -62,12 +62,12 @@ pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; pinctrl-names = "default"; - button@1 { + copy { label = "USB Copy"; linux,code = <KEY_COPY>; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; - button@2 { + reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts index 38e31d15a62d..d25184ae4af3 100644 --- a/arch/arm/boot/dts/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/kirkwood-iconnect.dts @@ -19,16 +19,6 @@ linux,initrd-end = <0x4800000>; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pmx_button_reset: pmx-button-reset { @@ -136,13 +126,13 @@ pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; pinctrl-names = "default"; - button@1 { + otb { label = "OTB Button"; linux,code = <KEY_COPY>; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - button@2 { + reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; @@ -194,3 +184,11 @@ phy-handle = <ðphy0>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-km_common.dtsi b/arch/arm/boot/dts/kirkwood-km_common.dtsi index 8367c772c764..7962bdefde49 100644 --- a/arch/arm/boot/dts/kirkwood-km_common.dtsi +++ b/arch/arm/boot/dts/kirkwood-km_common.dtsi @@ -4,16 +4,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >; @@ -34,7 +24,7 @@ }; }; - i2c@0 { + i2c { compatible = "i2c-gpio"; gpios = < &gpio0 8 GPIO_ACTIVE_HIGH /* sda */ &gpio0 9 GPIO_ACTIVE_HIGH>; /* scl */ @@ -46,3 +36,11 @@ status = "okay"; chip-delay = <25>; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts index 24425660e973..1b0f070c2676 100644 --- a/arch/arm/boot/dts/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/kirkwood-laplug.dts @@ -27,15 +27,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { serial@12000 { status = "okay"; @@ -62,7 +53,7 @@ gpio_keys { compatible = "gpio-keys"; - button@1{ + power { label = "Power push button"; linux,code = <KEY_POWER>; gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; @@ -169,3 +160,11 @@ phy-handle = <ðphy0>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-linkstation.dtsi b/arch/arm/boot/dts/kirkwood-linkstation.dtsi index 69061b6e987b..36c54c9dfa30 100644 --- a/arch/arm/boot/dts/kirkwood-linkstation.dtsi +++ b/arch/arm/boot/dts/kirkwood-linkstation.dtsi @@ -49,15 +49,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pmx_power_hdd0: pmx-power-hdd0 { @@ -200,3 +191,11 @@ }; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/kirkwood-linksys-viper.dts new file mode 100644 index 000000000000..345fcac48dc7 --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-linksys-viper.dts @@ -0,0 +1,240 @@ +/* + * kirkwood-viper.dts - Device Tree file for Linksys viper (E4200v2 / EA4500) + * + * (c) 2013 Jonas Gorski <jogo@openwrt.org> + * (c) 2013 Deutsche Telekom Innovation Laboratories + * (c) 2014 Luka Perkov <luka@openwrt.org> + * (c) 2014 Randy C. Will <randall.will@gmail.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6282.dtsi" + +/ { + model = "Linksys Viper (E4200v2 / EA4500)"; + compatible = "linksys,viper", "marvell,kirkwood-88f6282", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; + pinctrl-names = "default"; + + wps { + label = "WPS Button"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reset { + label = "Reset Button"; + linux,code = <KEY_RESTART>; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; + pinctrl-names = "default"; + + white-health { + label = "viper:white:health"; + gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; + }; + + white-pulse { + label = "viper:white:pulse"; + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + }; + }; + + dsa { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0port>; + dsa,mii-bus = <&mdio>; + + switch@16,0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <16 0>; /* MDIO address 16, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "ethernet1"; + }; + + port@1 { + reg = <1>; + label = "ethernet2"; + }; + + port@2 { + reg = <2>; + label = "ethernet3"; + }; + + port@3 { + reg = <3>; + label = "ethernet4"; + }; + + port@4 { + reg = <4>; + label = "internet"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; +}; + +&pinctrl { + pmx_led_white_health: pmx-led-white-health { + marvell,pins = "mpp7"; + marvell,function = "gpo"; + }; + pmx_led_white_pulse: pmx-led-white-pulse { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + pmx_btn_wps: pmx-btn-wps { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_btn_reset: pmx-btn-reset { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; +}; + +&nand { + status = "okay"; + pinctrl-0 = <&pmx_nand>; + pinctrl-names = "default"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "u_env"; + reg = <0x80000 0x20000>; + }; + + partition@A0000 { + label = "s_env"; + reg = <0xA0000 0x20000>; + }; + + partition@200000 { + label = "kernel"; + reg = <0x200000 0x2A0000>; + }; + + partition@4A0000 { + label = "rootfs"; + reg = <0x4A0000 0x1760000>; + }; + + partition@1C00000 { + label = "alt_kernel"; + reg = <0x1C00000 0x2A0000>; + }; + + partition@1EA0000 { + label = "alt_rootfs"; + reg = <0x1EA0000 0x1760000>; + }; + + partition@3600000 { + label = "syscfg"; + reg = <0x3600000 0x4A00000>; + }; + + partition@C0000 { + label = "unused"; + reg = <0xC0000 0x140000>; + }; + + }; +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&mdio { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set + * fixed speed and duplex. + */ +ð0 { + status = "okay"; + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +/* eth1 is connected to the switch at port 6. However DSA only supports a + * single CPU port. So leave this port disabled to avoid confusion. + */ +ð1 { + status = "disabled"; +}; + +/* There is no battery on the board, so the RTC does not keep + * time when there is no power, making it useless. + */ +&rtc { + status = "disabled"; +}; + diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi index 1d6528d82969..8b7c6ce79a41 100644 --- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi @@ -107,18 +107,18 @@ &pmx_power_auto_switch>; pinctrl-names = "default"; - button@1 { + option { label = "Function Button"; linux,code = <KEY_OPTION>; gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; - button@2 { + reserved { label = "Power-on Switch"; linux,code = <KEY_RESERVED>; linux,input-type = <5>; gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; - button@3 { + power { label = "Power-auto Switch"; linux,code = <KEY_ESC>; linux,input-type = <5>; @@ -133,28 +133,28 @@ &pmx_led_function_blue>; pinctrl-names = "default"; - led@1 { + func_blue { label = "lsxl:blue:func"; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; - led@2 { + alarm { label = "lsxl:red:alarm"; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; - led@3 { + info { label = "lsxl:amber:info"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; - led@4 { + power { label = "lsxl:blue:power"; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - led@5 { + func_red { label = "lsxl:red:func"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts index f3a991837515..aa413b0bcce2 100644 --- a/arch/arm/boot/dts/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts @@ -17,16 +17,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pmx_led_health: pmx-led-health { @@ -215,3 +205,11 @@ phy-handle = <ðphy1>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index b7e7d78c484e..172a38c0b8a9 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -31,16 +31,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pin-controller@10000 { pmx_usb_led: pmx-usb-led { @@ -109,19 +99,19 @@ pinctrl-0 = <&pmx_keys>; pinctrl-names = "default"; - button@1 { + restart { label = "SWR Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - button@2 { + wps { label = "WPS Button"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; }; - dsa@0 { + dsa { compatible = "marvell,dsa"; #address-cells = <1>; #size-cells = <0>; @@ -179,3 +169,11 @@ duplex = <1>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-nas2big.dts b/arch/arm/boot/dts/kirkwood-nas2big.dts index 7427ec50b829..f53bcacf6b63 100644 --- a/arch/arm/boot/dts/kirkwood-nas2big.dts +++ b/arch/arm/boot/dts/kirkwood-nas2big.dts @@ -28,16 +28,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { rtc@10300 { /* The on-chip RTC is not powered (no supercap). */ @@ -141,3 +131,11 @@ reg = <0x9100000 0x6f00000>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts index fd733c63bc27..c0413b63cf2e 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts @@ -28,16 +28,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pmx_button_power: pmx-button-power { @@ -193,7 +183,7 @@ #address-cells = <1>; #size-cells = <0>; - usb3_regulator: usb3-regulator { + usb3_regulator: usb3-regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "USB 3.0 Power"; @@ -251,3 +241,11 @@ phy-handle = <ðphy0>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts index b514d643fb6c..2bfc6cfa151d 100644 --- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts +++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts @@ -28,18 +28,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - /* Connected to NEC uPD720200 USB 3.0 controller */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pmx_button_power: pmx-button-power { @@ -205,7 +193,7 @@ #address-cells = <1>; #size-cells = <0>; - usb3_regulator: usb3-regulator { + usb3_regulator: usb3-regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "USB 3.0 Power"; @@ -265,3 +253,12 @@ phy-handle = <ðphy0>; }; }; + +/* Connected to NEC uPD720200 USB 3.0 controller */ +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/kirkwood-netxbig.dtsi index 62515a8b99b9..52b58fe0c4fe 100644 --- a/arch/arm/boot/dts/kirkwood-netxbig.dtsi +++ b/arch/arm/boot/dts/kirkwood-netxbig.dtsi @@ -59,22 +59,22 @@ #size-cells = <0>; /* - * button@1 and button@2 represent a three position rocker + * esc and power represent a three position rocker * switch. Thus the conventional KEY_POWER does not fit */ - button@1 { + exc { label = "Back power switch (on|auto)"; linux,code = <KEY_ESC>; linux,input-type = <5>; gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; }; - button@2 { + power { label = "Back power switch (auto|off)"; linux,code = <KEY_1>; linux,input-type = <5>; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; }; - button@3 { + option { label = "Function button"; linux,code = <KEY_OPTION>; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi index e832b6320264..282605f4c92c 100644 --- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi @@ -57,7 +57,7 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + power { label = "Power push button"; linux,code = <KEY_POWER>; gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; @@ -83,7 +83,7 @@ &mdio { status = "okay"; - ethphy0: ethernet-phy { + ethphy0: ethernet-phy@X { /* overwrite reg property in board file */ }; }; diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts index 6139df0f376c..0b69ee4934fa 100644 --- a/arch/arm/boot/dts/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/kirkwood-nsa310.dts @@ -15,16 +15,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_unknown>; @@ -138,3 +128,11 @@ }; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts index 24f686d1044d..6ab104b4bb42 100644 --- a/arch/arm/boot/dts/kirkwood-nsa320.dts +++ b/arch/arm/boot/dts/kirkwood-nsa320.dts @@ -27,16 +27,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pinctrl-names = "default"; @@ -193,10 +183,19 @@ }; }; + hwmon { + compatible = "zyxel,nsa320-mcu"; + pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; + pinctrl-names = "default"; + + data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + /* The following pins are currently not assigned to a driver, some of them should be configured as inputs. - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act - &pmx_htp &pmx_vid_b1 + pinctrl-0 = <&pmx_htp &pmx_vid_b1 &pmx_power_resume_data &pmx_power_resume_clk>; */ }; @@ -213,3 +212,11 @@ phy-handle = <ðphy0>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-nsa325.dts b/arch/arm/boot/dts/kirkwood-nsa325.dts index bc4ec9332387..36c64816bf7f 100644 --- a/arch/arm/boot/dts/kirkwood-nsa325.dts +++ b/arch/arm/boot/dts/kirkwood-nsa325.dts @@ -28,16 +28,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pinctrl-names = "default"; @@ -236,3 +226,10 @@ }; }; +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi index 2075a2e828f1..e09b79ac73fd 100644 --- a/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi +++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi @@ -4,16 +4,6 @@ / { model = "ZyXEL NSA310"; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { @@ -77,17 +67,17 @@ pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; pinctrl-names = "default"; - button@1 { + power { label = "Power Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; - button@2 { + copy { label = "Copy Button"; linux,code = <KEY_COPY>; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; - button@3 { + reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; @@ -157,3 +147,11 @@ reg = <0x5040000 0x2fc0000>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index fb9dc227255d..0db0e3edc88f 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -117,7 +117,7 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + power { label = "Init Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts index d5e3bc518968..cf2f5240e176 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts @@ -135,7 +135,7 @@ #address-cells = <1>; #size-cells = <0>; - button@1 { + button { label = "Init Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/kirkwood-openrd.dtsi b/arch/arm/boot/dts/kirkwood-openrd.dtsi index 24f1d30970a0..e4ecab112601 100644 --- a/arch/arm/boot/dts/kirkwood-openrd.dtsi +++ b/arch/arm/boot/dts/kirkwood-openrd.dtsi @@ -25,16 +25,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>; @@ -125,3 +115,7 @@ reg = <0x0600000 0x1FA00000>; }; }; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts index 8082d64266a3..b2f26239d298 100644 --- a/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts +++ b/arch/arm/boot/dts/kirkwood-pogoplug-series-4.dts @@ -33,7 +33,7 @@ pinctrl-0 = <&pmx_button_eject>; pinctrl-names = "default"; - button@1 { + eject { debounce_interval = <50>; wakeup-source; linux,code = <KEY_EJECTCD>; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts index e0b959396ca2..b8af907249fb 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts @@ -29,16 +29,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_usb_power>; @@ -108,4 +98,12 @@ ethernet0-port@0 { phy-handle = <ðphy0>; }; -};
\ No newline at end of file +}; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts index f2e08b3b33ea..6f771a99cb02 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts @@ -19,7 +19,7 @@ model = "Marvell RD88f6281 Reference design, with A0 or higher SoC"; compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - dsa@0 { + dsa { switch@0 { reg = <10 0>; /* MDIO address 10, switch 0 in tree */ }; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts index f4272b64ed7f..1a797381d3d4 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts @@ -19,7 +19,7 @@ model = "Marvell RD88f6281 Reference design, with Z0 SoC"; compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - dsa@0 { + dsa { switch@0 { reg = <0 0>; /* MDIO address 0, switch 0 in tree */ port@4 { diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index d195e884b3b5..d5aacf137e40 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi @@ -25,16 +25,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pinctrl-names = "default"; @@ -63,7 +53,7 @@ }; }; - dsa@0 { + dsa { compatible = "marvell,dsa"; #address-cells = <2>; #size-cells = <0>; @@ -134,3 +124,11 @@ duplex = <1>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts index 3b19f1fd4cac..2c722ecd5331 100644 --- a/arch/arm/boot/dts/kirkwood-rs212.dts +++ b/arch/arm/boot/dts/kirkwood-rs212.dts @@ -44,6 +44,10 @@ status = "okay"; }; -&pcie2 { +&pciec { + status = "okay"; +}; + +&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 04015c174b99..65e9524e852a 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -10,20 +10,6 @@ */ / { - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - - pcie2: pcie@2,0 { - status = "disabled"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pmx_alarmled_12: pmx-alarmled-12 { @@ -861,3 +847,11 @@ phy-handle = <ðphy1>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts index ed956b849a71..3500f4738fb0 100644 --- a/arch/arm/boot/dts/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/kirkwood-t5325.dts @@ -30,16 +30,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { pinctrl-0 = <&pmx_i2s &pmx_sysrst>; @@ -173,7 +163,7 @@ pinctrl-0 = <&pmx_button_power>; pinctrl-names = "default"; - button@1 { + power { label = "Power Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; @@ -217,7 +207,7 @@ &mdio { status = "okay"; - ethphy0: ethernet-phy { + ethphy0: ethernet-phy@8 { device_type = "ethernet-phy"; reg = <8>; }; @@ -229,3 +219,11 @@ phy-handle = <ðphy0>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts index 9767d73f3857..ee62204e4ecd 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts @@ -39,12 +39,12 @@ pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; - button@1 { + copy { label = "USB Copy"; linux,code = <KEY_COPY>; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; }; - button@2 { + reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts index bfc1a32d4e42..3437bb396844 100644 --- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts @@ -5,16 +5,6 @@ #include "kirkwood-ts219.dtsi" / { - mbus { - pcie-controller { - status = "okay"; - - pcie@2,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { pinctrl: pin-controller@10000 { @@ -49,12 +39,12 @@ pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; - button@1 { + copy { label = "USB Copy"; linux,code = <KEY_COPY>; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - button@2 { + reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; @@ -63,3 +53,5 @@ }; ðphy0 { reg = <0>; }; + +&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi index 0e46560551f4..62e5e2d5c348 100644 --- a/arch/arm/boot/dts/kirkwood-ts219.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi @@ -12,16 +12,6 @@ stdout-path = &uart0; }; - mbus { - pcie-controller { - status = "okay"; - - pcie@1,0 { - status = "okay"; - }; - }; - }; - ocp@f1000000 { i2c@11000 { status = "okay"; @@ -94,7 +84,7 @@ &mdio { status = "okay"; - ethphy0: ethernet-phy { + ethphy0: ethernet-phy@X { /* overwrite reg property in board file */ }; }; @@ -105,3 +95,11 @@ phy-handle = <ðphy0>; }; }; + +&pciec { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/kirkwood-ts419-6282.dts b/arch/arm/boot/dts/kirkwood-ts419-6282.dts index d7512d4cdced..e3e71f48acc8 100644 --- a/arch/arm/boot/dts/kirkwood-ts419-6282.dts +++ b/arch/arm/boot/dts/kirkwood-ts419-6282.dts @@ -16,17 +16,8 @@ #include "kirkwood-ts219.dtsi" #include "kirkwood-ts419.dtsi" -/ { - mbus { - pcie-controller { - status = "okay"; - - pcie@2,0 { - status = "okay"; - }; - }; - }; -}; - ðphy0 { reg = <0>; }; ðphy1 { reg = <1>; }; + +&pciec { status = "okay"; }; +&pcie1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/kirkwood-ts419.dtsi index 30ab93bfb1e4..02bd53762705 100644 --- a/arch/arm/boot/dts/kirkwood-ts419.dtsi +++ b/arch/arm/boot/dts/kirkwood-ts419.dtsi @@ -45,12 +45,12 @@ pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; - button@1 { + copy { label = "USB Copy"; linux,code = <KEY_COPY>; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - button@2 { + reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index 7445a15e259d..29b8bd7e0d93 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -27,7 +27,7 @@ i2c0 = &i2c0; }; - mbus { + mbus@f1000000 { compatible = "marvell,kirkwood-mbus", "simple-bus"; #address-cells = <2>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 053a1f54f4bb..fdb736c82045 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -195,13 +195,19 @@ clocks = <&ccu1 CLK_CPU_CREG>; resets = <&rgu 5>; - usb0_otg_phy: phy@004 { + creg_clk: clock-controller { + compatible = "nxp,lpc1850-creg-clk"; + clocks = <&xtal32>; + #clock-cells = <1>; + }; + + usb0_otg_phy: phy { compatible = "nxp,lpc1850-usb-otg-phy"; clocks = <&ccu1 CLK_USB0>; #phy-cells = <0>; }; - dmamux: dma-mux@11c { + dmamux: dma-mux { compatible = "nxp,lpc1850-dmamux"; #dma-cells = <3>; dma-requests = <64>; @@ -209,11 +215,19 @@ }; }; + rtc: rtc@40046000 { + compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc"; + reg = <0x40046000 0x1000>; + interrupts = <47>; + clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>; + clock-names = "rtc", "reg"; + }; + cgu: clock-controller@40050000 { compatible = "nxp,lpc1850-cgu"; reg = <0x40050000 0x1000>; #clock-cells = <1>; - clocks = <&xtal>, <&xtal32>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; + clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>; }; ccu1: clock-controller@40051000 { @@ -430,6 +444,15 @@ status = "disabled"; }; + dac: dac@400e1000 { + compatible = "nxp,lpc1850-dac"; + reg = <0x400e1000 0x1000>; + interrupts = <0>; + clocks = <&ccu1 CLK_APB3_DAC>; + resets = <&rgu 42>; + status = "disabled"; + }; + can0: can@400e2000 { compatible = "bosch,c_can"; reg = <0x400e2000 0x1000>; @@ -439,6 +462,24 @@ status = "disabled"; }; + adc0: adc@400e3000 { + compatible = "nxp,lpc1850-adc"; + reg = <0x400e3000 0x1000>; + interrupts = <17>; + clocks = <&ccu1 CLK_APB3_ADC0>; + resets = <&rgu 40>; + status = "disabled"; + }; + + adc1: adc@400e4000 { + compatible = "nxp,lpc1850-adc"; + reg = <0x400e4000 0x1000>; + interrupts = <21>; + clocks = <&ccu1 CLK_APB3_ADC1>; + resets = <&rgu 41>; + status = "disabled"; + }; + gpio: gpio@400f4000 { compatible = "nxp,lpc1850-gpio"; reg = <0x400f4000 0x4000>; diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/lpc3250-ea3250.dts index a4a281fe82af..52b3ed10283a 100644 --- a/arch/arm/boot/dts/ea3250.dts +++ b/arch/arm/boot/dts/lpc3250-ea3250.dts @@ -25,119 +25,6 @@ reg = <0x80000000 0x4000000>; }; - ahb { - mac: ethernet@31060000 { - phy-mode = "rmii"; - use-iram; - }; - - /* 128MB Flash via SLC NAND controller */ - slc: flash@20020000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - - nxp,wdr-clks = <14>; - nxp,wwidth = <260000000>; - nxp,whold = <104000000>; - nxp,wsetup = <200000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <34666666>; - nxp,rhold = <104000000>; - nxp,rsetup = <200000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - mtd0@00000000 { - label = "ea3250-boot"; - reg = <0x00000000 0x00080000>; - read-only; - }; - - mtd1@00080000 { - label = "ea3250-uboot"; - reg = <0x00080000 0x000c0000>; - read-only; - }; - - mtd2@00140000 { - label = "ea3250-kernel"; - reg = <0x00140000 0x00400000>; - }; - - mtd3@00540000 { - label = "ea3250-rootfs"; - reg = <0x00540000 0x07ac0000>; - }; - }; - - apb { - uart5: serial@40090000 { - status = "okay"; - }; - - uart3: serial@40080000 { - status = "okay"; - }; - - uart6: serial@40098000 { - status = "okay"; - }; - - i2c1: i2c@400A0000 { - clock-frequency = <100000>; - - eeprom@50 { - compatible = "at,24c256"; - reg = <0x50>; - }; - - eeprom@57 { - compatible = "at,24c64"; - reg = <0x57>; - }; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 0x59 0>; - reset-gpio = <&gpio 0x51 0>; - dac-clk = "wspll"; - }; - - pca9532: pca9532@60 { - compatible = "nxp,pca9532"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x60>; - }; - }; - - i2c2: i2c@400A8000 { - clock-frequency = <100000>; - }; - - sd@20098000 { - wp-gpios = <&pca9532 5 0>; - cd-gpios = <&pca9532 4 0>; - cd-inverted; - bus-width = <4>; - status = "okay"; - }; - }; - - fab { - uart1: serial@40014000 { - status = "okay"; - }; - - /* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ - adc@40048000 { - status = "okay"; - }; - }; - }; - gpio_keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -258,12 +145,44 @@ }; }; -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; +/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */ +&adc { status = "okay"; }; +&i2c1 { + clock-frequency = <100000>; + + uda1380: uda1380@18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 0x59 0>; + reset-gpio = <&gpio 0x51 0>; + dac-clk = "wspll"; + }; + + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; + + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; + + pca9532: pca9532@60 { + compatible = "nxp,pca9532"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x60>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + &i2cusb { clock-frequency = <100000>; @@ -272,3 +191,82 @@ reg = <0x2d>; }; }; + +&mac { + phy-mode = "rmii"; + use-iram; +}; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&sd { + wp-gpios = <&pca9532 5 0>; + cd-gpios = <&pca9532 4 0>; + cd-inverted; + bus-width = <4>; + status = "okay"; +}; + +/* 128MB Flash via SLC NAND controller */ +&slc { + status = "okay"; + + nxp,wdr-clks = <14>; + nxp,wwidth = <260000000>; + nxp,whold = <104000000>; + nxp,wsetup = <200000000>; + nxp,rdr-clks = <14>; + nxp,rwidth = <34666666>; + nxp,rhold = <104000000>; + nxp,rsetup = <200000000>; + nand-on-flash-bbt; + gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + mtd0@00000000 { + label = "ea3250-boot"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + mtd1@00080000 { + label = "ea3250-uboot"; + reg = <0x00080000 0x000c0000>; + read-only; + }; + + mtd2@00140000 { + label = "ea3250-kernel"; + reg = <0x00140000 0x00400000>; + }; + + mtd3@00540000 { + label = "ea3250-rootfs"; + reg = <0x00540000 0x07ac0000>; + }; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&uart6 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lpc3250-phy3250.dts b/arch/arm/boot/dts/lpc3250-phy3250.dts new file mode 100644 index 000000000000..fd95e2b10357 --- /dev/null +++ b/arch/arm/boot/dts/lpc3250-phy3250.dts @@ -0,0 +1,226 @@ +/* + * PHYTEC phyCORE-LPC3250 board + * + * Copyright 2012 Roland Stigge <stigge@antcom.de> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "lpc32xx.dtsi" + +/ { + model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; + compatible = "phytec,phy3250", "nxp,lpc3250"; + #address-cells = <1>; + #size-cells = <1>; + + memory { + device_type = "memory"; + reg = <0x80000000 0x4000000>; + }; + + regulators { + backlight_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "backlight_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 4 0>; + enable-active-high; + regulator-boot-on; + }; + + lcd_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "lcd_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 0 0>; + enable-active-high; + regulator-boot-on; + }; + + sd_reg: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "sd_reg"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio 5 5 0>; + enable-active-high; + }; + }; + + leds { + compatible = "gpio-leds"; + + led0 { /* red */ + gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ + default-state = "off"; + }; + + led1 { /* green */ + gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&clcd { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + + uda1380: uda1380@18 { + compatible = "nxp,uda1380"; + reg = <0x18>; + power-gpio = <&gpio 0x59 0>; + reset-gpio = <&gpio 0x51 0>; + dac-clk = "wspll"; + }; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; +}; + +&i2cusb { + clock-frequency = <100000>; + + isp1301: usb-transceiver@2c { + compatible = "nxp,isp1301"; + reg = <0x2c>; + }; +}; + +&key { + keypad,num-rows = <1>; + keypad,num-columns = <1>; + nxp,debounce-delay-ms = <3>; + nxp,scan-delay-ms = <34>; + linux,keymap = <0x00000002>; + status = "okay"; +}; + +&mac { + phy-mode = "rmii"; + use-iram; +}; + +/* Here, choose exactly one from: ohci, usbd */ +&ohci /* &usbd */ { + transceiver = <&isp1301>; + status = "okay"; +}; + +&sd { + wp-gpios = <&gpio 3 0 0>; + cd-gpios = <&gpio 3 1 0>; + cd-inverted; + bus-width = <4>; + vmmc-supply = <&sd_reg>; + status = "okay"; +}; + +/* 64MB Flash via SLC NAND controller */ +&slc { + status = "okay"; + + nxp,wdr-clks = <14>; + nxp,wwidth = <40000000>; + nxp,whold = <100000000>; + nxp,wsetup = <100000000>; + nxp,rdr-clks = <14>; + nxp,rwidth = <40000000>; + nxp,rhold = <66666666>; + nxp,rsetup = <100000000>; + nand-on-flash-bbt; + gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + mtd0@00000000 { + label = "phy3250-boot"; + reg = <0x00000000 0x00064000>; + read-only; + }; + + mtd1@00064000 { + label = "phy3250-uboot"; + reg = <0x00064000 0x00190000>; + read-only; + }; + + mtd2@001f4000 { + label = "phy3250-ubt-prms"; + reg = <0x001f4000 0x00010000>; + }; + + mtd3@00204000 { + label = "phy3250-kernel"; + reg = <0x00204000 0x00400000>; + }; + + mtd4@00604000 { + label = "phy3250-rootfs"; + reg = <0x00604000 0x039fc000>; + }; + }; +}; + +&ssp0 { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <1>; + cs-gpios = <&gpio 3 5 0>; + status = "okay"; + + eeprom: at25@0 { + compatible = "atmel,at25"; + reg = <0>; + spi-max-frequency = <5000000>; + + pl022,interface = <0>; + pl022,com-mode = <0>; + pl022,rx-level-trig = <1>; + pl022,tx-level-trig = <1>; + pl022,ctrl-len = <11>; + pl022,wait-state = <0>; + pl022,duplex = <0>; + + at25,byte-len = <0x8000>; + at25,addr-mode = <2>; + at25,page-size = <64>; + }; +}; + +&tsc { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi index c58d8da9ea2a..e295e1ec82a5 100644 --- a/arch/arm/boot/dts/lpc32xx.dtsi +++ b/arch/arm/boot/dts/lpc32xx.dtsi @@ -92,7 +92,8 @@ ohci: ohci@0 { compatible = "nxp,ohci-nxp", "usb-ohci"; reg = <0x0 0x300>; - interrupts = <59 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usbclk LPC32XX_USB_CLK_HOST>; status = "disabled"; }; @@ -100,10 +101,11 @@ usbd: usbd@0 { compatible = "nxp,lpc3220-udc"; reg = <0x0 0x300>; - interrupts = <61 IRQ_TYPE_LEVEL_HIGH>, - <62 IRQ_TYPE_LEVEL_HIGH>, - <60 IRQ_TYPE_LEVEL_HIGH>, - <58 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&sic1>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH>, + <30 IRQ_TYPE_LEVEL_HIGH>, + <28 IRQ_TYPE_LEVEL_HIGH>, + <26 IRQ_TYPE_LEVEL_LOW>; clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>; status = "disabled"; }; @@ -111,7 +113,8 @@ i2cusb: i2c@300 { compatible = "nxp,pnx-i2c"; reg = <0x300 0x100>; - interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usbclk LPC32XX_USB_CLK_I2C>; #address-cells = <1>; #size-cells = <0>; @@ -162,30 +165,44 @@ compatible = "simple-bus"; ranges = <0x20000000 0x20000000 0x30000000>; + /* + * ssp0 and spi1 are shared pins; + * enable one in your board dts, as needed. + */ ssp0: ssp@20084000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x20084000 0x1000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP0>; clock-names = "apb_pclk"; + status = "disabled"; }; spi1: spi@20088000 { compatible = "nxp,lpc3220-spi"; reg = <0x20088000 0x1000>; + clocks = <&clk LPC32XX_CLK_SPI1>; + status = "disabled"; }; + /* + * ssp1 and spi2 are shared pins; + * enable one in your board dts, as needed. + */ ssp1: ssp@2008c000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x2008c000 0x1000>; interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_SSP1>; clock-names = "apb_pclk"; + status = "disabled"; }; spi2: spi@20090000 { compatible = "nxp,lpc3220-spi"; reg = <0x20090000 0x1000>; + clocks = <&clk LPC32XX_CLK_SPI2>; + status = "disabled"; }; i2s0: i2s@20094000 { @@ -249,7 +266,8 @@ i2c1: i2c@400A0000 { compatible = "nxp,pnx-i2c"; reg = <0x400A0000 0x100>; - interrupts = <51 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&sic1>; + interrupts = <19 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; pnx,timeout = <0x64>; @@ -259,7 +277,8 @@ i2c2: i2c@400A8000 { compatible = "nxp,pnx-i2c"; reg = <0x400A8000 0x100>; - interrupts = <50 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&sic1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; #address-cells = <1>; #size-cells = <0>; pnx,timeout = <0x64>; @@ -294,22 +313,41 @@ clocks = <&xtal_32k>, <&xtal>; clock-names = "xtal_32k", "xtal"; + + assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>; + assigned-clock-rates = <208000000>; }; }; - /* - * MIC Interrupt controller includes: - * MIC @40008000 - * SIC1 @4000C000 - * SIC2 @40010000 - */ mic: interrupt-controller@40008000 { compatible = "nxp,lpc3220-mic"; + reg = <0x40008000 0x4000>; interrupt-controller; - reg = <0x40008000 0xC000>; #interrupt-cells = <2>; }; + sic1: interrupt-controller@4000c000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x4000c000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>, + <30 IRQ_TYPE_LEVEL_LOW>; + }; + + sic2: interrupt-controller@40010000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x40010000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&mic>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>, + <31 IRQ_TYPE_LEVEL_LOW>; + }; + uart1: serial@40014000 { compatible = "nxp,lpc3220-hsuart"; reg = <0x40014000 0x1000>; @@ -334,7 +372,8 @@ rtc: rtc@40024000 { compatible = "nxp,lpc3220-rtc"; reg = <0x40024000 0x1000>; - interrupts = <52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_RTC>; }; @@ -387,7 +426,8 @@ adc: adc@40048000 { compatible = "nxp,lpc3220-adc"; reg = <0x40048000 0x1000>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_ADC>; status = "disabled"; }; @@ -395,7 +435,8 @@ tsc: tsc@40048000 { compatible = "nxp,lpc3220-tsc"; reg = <0x40048000 0x1000>; - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&sic1>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk LPC32XX_CLK_ADC>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts index 022d495432c1..6c9048d4d03c 100644 --- a/arch/arm/boot/dts/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/lpc4350-hitex-eval.dts @@ -45,50 +45,50 @@ poll-interval = <100>; autorepeat; - button@0 { + button0 { label = "joy:right"; linux,code = <KEY_RIGHT>; gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>; }; - button@1 { + button1 { label = "joy:up"; linux,code = <KEY_UP>; gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>; }; - button@2 { + button2 { label = "joy:enter"; linux,code = <KEY_ENTER>; gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>; }; - button@3 { + button3 { label = "joy:left"; linux,code = <KEY_LEFT>; gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>; }; - button@4 { + button4 { label = "joy:down"; linux,code = <KEY_DOWN>; gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>; }; - button@5 { + button5 { label = "user:sw3"; linux,code = <KEY_F1>; gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>; }; - button@6 { + button6 { label = "user:sw4"; linux,code = <KEY_F2>; gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>; }; - button@7 { + button7 { label = "user:sw5"; linux,code = <KEY_F3>; gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>; @@ -119,9 +119,25 @@ gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>; }; }; + + vcc: vcc_fixed { + compatible = "regulator-fixed"; + regulator-name = "3v3io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &pinctrl { + adc1_pins: adc1-pins { + adc1_pins_cfg { + pins = "pf_9"; + function = "adc"; + input-disable; + bias-disable; + }; + }; + emc_pins: emc-pins { emc_addr0_23_cfg { pins = "p2_9", "p2_10", "p2_11", "p2_12", @@ -325,6 +341,13 @@ }; }; +&adc1 { + status = "okay"; + vref-supply = <&vcc>; + pinctrl-names = "default"; + pinctrl-0 = <&adc1_pins>; +}; + &emc { status = "okay"; pinctrl-names = "default"; @@ -430,7 +453,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spifi_pins>; - flash@0 { + flash { compatible = "jedec,spi-nor"; spi-rx-bus-width = <4>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index 079d3cf8c00b..1919be4dab2b 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -38,6 +38,13 @@ reg = <0x28000000 0x2000000>; /* 32 MB */ }; + vcc: vcc_fixed { + compatible = "regulator-fixed"; + regulator-name = "3v3-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + /* vmmc is controlled by sdmmc host internally */ vmmc: vmmc_fixed { compatible = "regulator-fixed"; @@ -55,31 +62,31 @@ poll-interval = <100>; autorepeat; - button@0 { + button0 { label = "joy_enter"; linux,code = <KEY_ENTER>; gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>; }; - button@1 { + button1 { label = "joy_left"; linux,code = <KEY_LEFT>; gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>; }; - button@2 { + button2 { label = "joy_up"; linux,code = <KEY_UP>; gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>; }; - button@3 { + button3 { label = "joy_right"; linux,code = <KEY_RIGHT>; gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>; }; - button@4 { + button4 { label = "joy_down"; linux,code = <KEY_DOWN>; gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>; @@ -461,6 +468,11 @@ }; }; +&adc0 { + status = "okay"; + vref-supply = <&vcc>; +}; + &i2c0 { status = "okay"; pinctrl-names = "default"; @@ -483,6 +495,11 @@ }; }; +&dac { + status = "okay"; + vref-supply = <&vcc>; +}; + &emc { status = "okay"; pinctrl-names = "default"; @@ -567,7 +584,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spifi_pins>; - flash@0 { + flash { compatible = "jedec,spi-nor"; spi-cpol; spi-cpha; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 726372d3adc0..5ae8e9297e9a 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -119,6 +119,20 @@ }; + msi1: msi-controller@1570e00 { + compatible = "fsl,1s1021a-msi"; + reg = <0x0 0x1570e00 0x0 0x8>; + msi-controller; + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; + }; + + msi2: msi-controller@1570e08 { + compatible = "fsl,1s1021a-msi"; + reg = <0x0 0x1570e08 0x0 0x8>; + msi-controller; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; @@ -245,7 +259,7 @@ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; clocks = <&platform_clk 1>; - spi-num-chipselects = <5>; + spi-num-chipselects = <6>; big-endian; status = "disabled"; }; @@ -258,7 +272,7 @@ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; clocks = <&platform_clk 1>; - spi-num-chipselects = <5>; + spi-num-chipselects = <6>; big-endian; status = "disabled"; }; @@ -332,6 +346,46 @@ status = "disabled"; }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@2310000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2320000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@2330000 { + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; + reg = <0x0 0x2330000 0x0 0x10000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + lpuart0: serial@2950000 { compatible = "fsl,ls1021a-lpuart"; reg = <0x0 0x2950000 0x0 0x1000>; @@ -443,8 +497,9 @@ compatible = "fsl,ls1021a-dcu"; reg = <0x0 0x2ce0000 0x0 0x10000>; interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&platform_clk 0>; - clock-names = "dcu"; + clocks = <&platform_clk 0>, + <&platform_clk 0>; + clock-names = "dcu", "pix"; big-endian; status = "disabled"; }; @@ -587,6 +642,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi1>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, @@ -609,6 +665,7 @@ bus-range = <0x0 0xff>; ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&msi2>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm/boot/dts/rk3288-thermal.dtsi b/arch/arm/boot/dts/mps2-an385.dts index 651b962e3d53..31c374d72a6f 100644 --- a/arch/arm/boot/dts/rk3288-thermal.dtsi +++ b/arch/arm/boot/dts/mps2-an385.dts @@ -1,7 +1,7 @@ /* - * Device Tree Source for RK3288 SoC thermal + * Copyright (C) 2015 ARM Limited * - * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * Author: Vladimir Murzin <vladimir.murzin@arm.com> * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -42,77 +42,51 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include <dt-bindings/thermal/thermal.h> +/dts-v1/; -reserve_thermal: reserve_thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ +#include "mps2.dtsi" - thermal-sensors = <&tsadc 0>; -}; +/ { + model = "ARM MPS2 Application Note 385/386"; + compatible = "arm,mps2"; -cpu_thermal: cpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ + aliases { + serial0 = &uart0; + }; - thermal-sensors = <&tsadc 1>; + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:9600n8"; + }; - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; + memory { + device_type = "memory"; + reg = <0x21000000 0x1000000>; }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + smb { + ethernet@0,0 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0 0x0 0x10000>; + interrupts = <13>; + interrupt-parent = <&nvic>; + smsc,irq-active-high; }; }; }; -gpu_thermal: gpu_thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ +&uart0 { + status = "okay"; +}; - thermal-sensors = <&tsadc 2>; +&timer0 { + status = "okay"; +}; - trips { - gpu_alert0: gpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - gpu_crit: gpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; +&timer1 { + status = "okay"; +}; - cooling-maps { - map0 { - trip = <&gpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; +&wdt { + status = "okay"; }; diff --git a/arch/arm/boot/dts/mps2-an399.dts b/arch/arm/boot/dts/mps2-an399.dts new file mode 100644 index 000000000000..5e7e5ca2edbf --- /dev/null +++ b/arch/arm/boot/dts/mps2-an399.dts @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Vladimir Murzin <vladimir.murzin@arm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "mps2.dtsi" + +/ { + model = "ARM MPS2 Application Note 399/400"; + compatible = "arm,mps2"; + + aliases { + serial0 = &uart0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:9600n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x1000000>; + }; + + smb { + ethernet@1,0 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <1 0x0 0x10000>; + interrupts = <13>; + interrupt-parent = <&nvic>; + smsc,irq-active-high; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi new file mode 100644 index 000000000000..e3fed8d34558 --- /dev/null +++ b/arch/arm/boot/dts/mps2.dtsi @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2015 ARM Limited + * + * Author: Vladimir Murzin <vladimir.murzin@arm.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armv7-m.dtsi" + +/ { + oscclk0: clk-osc0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + oscclk1: clk-osc1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + oscclk2: clk-osc2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + cfgclk: clk-cfg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <5000000>; + }; + + spicfgclk: clk-spicfg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <75000000>; + }; + + sysclk: clk-sys { + compatible = "fixed-factor-clock"; + clocks = <&oscclk0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + audmclk: clk-audm { + compatible = "fixed-factor-clock"; + clocks = <&oscclk1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + audsclk: clk-auds { + compatible = "fixed-factor-clock"; + clocks = <&oscclk1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; + + spiclcd: clk-cpiclcd { + compatible = "fixed-factor-clock"; + clocks = <&oscclk0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + spicon: clk-spicon { + compatible = "fixed-factor-clock"; + clocks = <&oscclk0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + i2cclcd: clk-i2cclcd { + compatible = "fixed-factor-clock"; + clocks = <&oscclk0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + i2caud: clk-i2caud { + compatible = "fixed-factor-clock"; + clocks = <&oscclk0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + + soc { + compatible = "simple-bus"; + ranges; + + apb@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x10000>; + + timer0: mps2-timer0@0 { + compatible = "arm,mps2-timer"; + reg = <0x0 0x1000>; + interrupts = <8>; + clocks = <&sysclk>; + status = "disabled"; + }; + + timer1: mps2-timer1@1000 { + compatible = "arm,mps2-timer"; + reg = <0x1000 0x1000>; + interrupts = <9>; + clocks = <&sysclk>; + status = "disabled"; + }; + + timer2: dual-timer@2000 { + compatible = "arm,sp804"; + reg = <0x2000 0x1000>; + clocks = <&sysclk>; + interrupts = <10>; + status = "disabled"; + }; + + uart0: serial@4000 { + compatible = "arm,mps2-uart"; + reg = <0x4000 0x1000>; + interrupts = <0 1 12>; + clocks = <&sysclk>; + status = "disabled"; + }; + + uart1: serial@5000 { + compatible = "arm,mps2-uart"; + reg = <0x5000 0x1000>; + interrupts = <2 3 12>; + clocks = <&sysclk>; + status = "disabled"; + }; + + uart2: serial@6000 { + compatible = "arm,mps2-uart"; + reg = <0x6000 0x1000>; + interrupts = <4 5 12>; + clocks = <&sysclk>; + status = "disabled"; + }; + + wdt: watchdog@8000 { + compatible = "arm,sp805", "arm,primecell"; + arm,primecell-periphid = <0x00141805>; + reg = <0x8000 0x1000>; + interrupts = <0>; + clocks = <&sysclk>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + }; + }; + + fpga@40020000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40020000 0x10000>; + + fpgaio@8000 { + compatible = "syscon", "simple-mfd"; + reg = <0x8000 0x10>; + + led0 { + compatible = "register-bit-led"; + offset = <0x0>; + mask = <0x01>; + label = "userled:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + + led1 { + compatible = "register-bit-led"; + offset = <0x0>; + mask = <0x02>; + label = "userled:1"; + linux,default-trigger = "usr"; + default-state = "off"; + }; + }; + }; + + smb { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x40200000 0x10000>, + <1 0 0xa0000000 0x10000>; + }; +}; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 83437683aa60..18596a2c58a1 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "skeleton64.dtsi" +#include "mt2701-pinfunc.h" / { compatible = "mediatek,mt2701"; @@ -85,6 +86,24 @@ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + pio: pinctrl@10005000 { + compatible = "mediatek,mt2701-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl_a>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; + + syscfg_pctl_a: syscfg@10005000 { + compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt2701-wdt", "mediatek,mt6589-wdt"; diff --git a/arch/arm/boot/dts/omap2420-clocks.dtsi b/arch/arm/boot/dts/omap2420-clocks.dtsi index ce8c742d7e92..f8e5bd3cc628 100644 --- a/arch/arm/boot/dts/omap2420-clocks.dtsi +++ b/arch/arm/boot/dts/omap2420-clocks.dtsi @@ -9,7 +9,7 @@ */ &prcm_clocks { - sys_clkout2_src_gate: sys_clkout2_src_gate { + sys_clkout2_src_gate: sys_clkout2_src_gate@70 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&core_ck>; @@ -17,7 +17,7 @@ reg = <0x0070>; }; - sys_clkout2_src_mux: sys_clkout2_src_mux { + sys_clkout2_src_mux: sys_clkout2_src_mux@70 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; @@ -31,7 +31,7 @@ clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>; }; - sys_clkout2: sys_clkout2 { + sys_clkout2: sys_clkout2@70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkout2_src>; @@ -41,7 +41,7 @@ ti,index-power-of-two; }; - dsp_gate_ick: dsp_gate_ick { + dsp_gate_ick: dsp_gate_ick@810 { #clock-cells = <0>; compatible = "ti,composite-interface-clock"; clocks = <&dsp_fck>; @@ -49,7 +49,7 @@ reg = <0x0810>; }; - dsp_div_ick: dsp_div_ick { + dsp_div_ick: dsp_div_ick@840 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&dsp_fck>; @@ -65,7 +65,7 @@ clocks = <&dsp_gate_ick>, <&dsp_div_ick>; }; - iva1_gate_ifck: iva1_gate_ifck { + iva1_gate_ifck: iva1_gate_ifck@800 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&core_ck>; @@ -73,7 +73,7 @@ reg = <0x0800>; }; - iva1_div_ifck: iva1_div_ifck { + iva1_div_ifck: iva1_div_ifck@840 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&core_ck>; @@ -96,7 +96,7 @@ clock-div = <2>; }; - iva1_mpu_int_ifck: iva1_mpu_int_ifck { + iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&iva1_ifck_div>; @@ -104,7 +104,7 @@ reg = <0x0800>; }; - wdt3_ick: wdt3_ick { + wdt3_ick: wdt3_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -112,7 +112,7 @@ reg = <0x0210>; }; - wdt3_fck: wdt3_fck { + wdt3_fck: wdt3_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_32k_ck>; @@ -120,7 +120,7 @@ reg = <0x0200>; }; - mmc_ick: mmc_ick { + mmc_ick: mmc_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -128,7 +128,7 @@ reg = <0x0210>; }; - mmc_fck: mmc_fck { + mmc_fck: mmc_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_96m_ck>; @@ -136,7 +136,7 @@ reg = <0x0200>; }; - eac_ick: eac_ick { + eac_ick: eac_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -144,7 +144,7 @@ reg = <0x0210>; }; - eac_fck: eac_fck { + eac_fck: eac_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_96m_ck>; @@ -152,7 +152,7 @@ reg = <0x0200>; }; - i2c1_fck: i2c1_fck { + i2c1_fck: i2c1_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_12m_ck>; @@ -160,7 +160,7 @@ reg = <0x0200>; }; - i2c2_fck: i2c2_fck { + i2c2_fck: i2c2_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_12m_ck>; @@ -168,7 +168,7 @@ reg = <0x0200>; }; - vlynq_ick: vlynq_ick { + vlynq_ick: vlynq_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l3_ck>; @@ -176,7 +176,7 @@ reg = <0x0210>; }; - vlynq_gate_fck: vlynq_gate_fck { + vlynq_gate_fck: vlynq_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&core_ck>; @@ -192,7 +192,7 @@ clock-div = <18>; }; - vlynq_mux_fck: vlynq_mux_fck { + vlynq_mux_fck: vlynq_mux_fck@240 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>; diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi index 8491f46c61b7..db95aadcca70 100644 --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi @@ -7,7 +7,7 @@ }; ocp { - i2c@0 { + i2c0 { compatible = "i2c-cbus-gpio"; gpios = <&gpio3 2 GPIO_ACTIVE_HIGH /* gpio66 clk */ &gpio3 1 GPIO_ACTIVE_HIGH /* gpio65 dat */ diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 5b9a376cc31e..fb712b9aa874 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -130,6 +130,10 @@ gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; mcbsp1: mcbsp@48074000 { diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi index 93fed68839b9..a5aa7d619849 100644 --- a/arch/arm/boot/dts/omap2430-clocks.dtsi +++ b/arch/arm/boot/dts/omap2430-clocks.dtsi @@ -9,7 +9,7 @@ */ &scm_clocks { - mcbsp3_mux_fck: mcbsp3_mux_fck { + mcbsp3_mux_fck: mcbsp3_mux_fck@78 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; @@ -22,7 +22,7 @@ clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; }; - mcbsp4_mux_fck: mcbsp4_mux_fck { + mcbsp4_mux_fck: mcbsp4_mux_fck@78 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; @@ -36,7 +36,7 @@ clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>; }; - mcbsp5_mux_fck: mcbsp5_mux_fck { + mcbsp5_mux_fck: mcbsp5_mux_fck@78 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; @@ -52,7 +52,7 @@ }; &prcm_clocks { - iva2_1_gate_ick: iva2_1_gate_ick { + iva2_1_gate_ick: iva2_1_gate_ick@800 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&dsp_fck>; @@ -60,7 +60,7 @@ reg = <0x0800>; }; - iva2_1_div_ick: iva2_1_div_ick { + iva2_1_div_ick: iva2_1_div_ick@840 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&dsp_fck>; @@ -76,7 +76,7 @@ clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>; }; - mdm_gate_ick: mdm_gate_ick { + mdm_gate_ick: mdm_gate_ick@c10 { #clock-cells = <0>; compatible = "ti,composite-interface-clock"; clocks = <&core_ck>; @@ -84,7 +84,7 @@ reg = <0x0c10>; }; - mdm_div_ick: mdm_div_ick { + mdm_div_ick: mdm_div_ick@c40 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&core_ck>; @@ -98,7 +98,7 @@ clocks = <&mdm_gate_ick>, <&mdm_div_ick>; }; - mdm_osc_ck: mdm_osc_ck { + mdm_osc_ck: mdm_osc_ck@c00 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&osc_ck>; @@ -106,7 +106,7 @@ reg = <0x0c00>; }; - mcbsp3_ick: mcbsp3_ick { + mcbsp3_ick: mcbsp3_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -114,7 +114,7 @@ reg = <0x0214>; }; - mcbsp3_gate_fck: mcbsp3_gate_fck { + mcbsp3_gate_fck: mcbsp3_gate_fck@204 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; @@ -122,7 +122,7 @@ reg = <0x0204>; }; - mcbsp4_ick: mcbsp4_ick { + mcbsp4_ick: mcbsp4_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -130,7 +130,7 @@ reg = <0x0214>; }; - mcbsp4_gate_fck: mcbsp4_gate_fck { + mcbsp4_gate_fck: mcbsp4_gate_fck@204 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; @@ -138,7 +138,7 @@ reg = <0x0204>; }; - mcbsp5_ick: mcbsp5_ick { + mcbsp5_ick: mcbsp5_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -146,7 +146,7 @@ reg = <0x0214>; }; - mcbsp5_gate_fck: mcbsp5_gate_fck { + mcbsp5_gate_fck: mcbsp5_gate_fck@204 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; @@ -154,7 +154,7 @@ reg = <0x0204>; }; - mcspi3_ick: mcspi3_ick { + mcspi3_ick: mcspi3_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -162,7 +162,7 @@ reg = <0x0214>; }; - mcspi3_fck: mcspi3_fck { + mcspi3_fck: mcspi3_fck@204 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_48m_ck>; @@ -170,7 +170,7 @@ reg = <0x0204>; }; - icr_ick: icr_ick { + icr_ick: icr_ick@410 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&sys_ck>; @@ -178,7 +178,7 @@ reg = <0x0410>; }; - i2chs1_fck: i2chs1_fck { + i2chs1_fck: i2chs1_fck@204 { #clock-cells = <0>; compatible = "ti,omap2430-interface-clock"; clocks = <&func_96m_ck>; @@ -186,7 +186,7 @@ reg = <0x0204>; }; - i2chs2_fck: i2chs2_fck { + i2chs2_fck: i2chs2_fck@204 { #clock-cells = <0>; compatible = "ti,omap2430-interface-clock"; clocks = <&func_96m_ck>; @@ -194,7 +194,7 @@ reg = <0x0204>; }; - usbhs_ick: usbhs_ick { + usbhs_ick: usbhs_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l3_ck>; @@ -202,7 +202,7 @@ reg = <0x0214>; }; - mmchs1_ick: mmchs1_ick { + mmchs1_ick: mmchs1_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -210,7 +210,7 @@ reg = <0x0214>; }; - mmchs1_fck: mmchs1_fck { + mmchs1_fck: mmchs1_fck@204 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_96m_ck>; @@ -218,7 +218,7 @@ reg = <0x0204>; }; - mmchs2_ick: mmchs2_ick { + mmchs2_ick: mmchs2_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -226,7 +226,7 @@ reg = <0x0214>; }; - mmchs2_fck: mmchs2_fck { + mmchs2_fck: mmchs2_fck@204 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_96m_ck>; @@ -234,7 +234,7 @@ reg = <0x0204>; }; - gpio5_ick: gpio5_ick { + gpio5_ick: gpio5_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -242,7 +242,7 @@ reg = <0x0214>; }; - gpio5_fck: gpio5_fck { + gpio5_fck: gpio5_fck@204 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_32k_ck>; @@ -250,7 +250,7 @@ reg = <0x0204>; }; - mdm_intc_ick: mdm_intc_ick { + mdm_intc_ick: mdm_intc_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -258,7 +258,7 @@ reg = <0x0214>; }; - mmchsdb1_fck: mmchsdb1_fck { + mmchsdb1_fck: mmchsdb1_fck@204 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_32k_ck>; @@ -266,7 +266,7 @@ reg = <0x0204>; }; - mmchsdb2_fck: mmchsdb2_fck { + mmchsdb2_fck: mmchsdb2_fck@204 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_32k_ck>; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 798dda072b2a..455aaea407dd 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -63,7 +63,7 @@ #size-cells = <0>; }; - pbias_regulator: pbias_regulator { + pbias_regulator: pbias_regulator@230 { compatible = "ti,pbias-omap2", "ti,pbias-omap"; reg = <0x230 0x4>; syscon = <&scm_conf>; @@ -154,6 +154,10 @@ gpmc,num-cs = <8>; gpmc,num-waitpins = <4>; ti,hwmods = "gpmc"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; mcbsp1: mcbsp@48074000 { diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi index 63965b876973..ca73722b5ea4 100644 --- a/arch/arm/boot/dts/omap24xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &scm_clocks { - mcbsp1_mux_fck: mcbsp1_mux_fck { + mcbsp1_mux_fck: mcbsp1_mux_fck@4 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; @@ -22,7 +22,7 @@ clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; }; - mcbsp2_mux_fck: mcbsp2_mux_fck { + mcbsp2_mux_fck: mcbsp2_mux_fck@4 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; @@ -74,7 +74,7 @@ clock-frequency = <26000000>; }; - aplls_clkin_ck: aplls_clkin_ck { + aplls_clkin_ck: aplls_clkin_ck@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>; @@ -90,7 +90,7 @@ clock-div = <1>; }; - osc_ck: osc_ck { + osc_ck: osc_ck@60 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>; @@ -99,7 +99,7 @@ ti,index-starts-at-one; }; - sys_ck: sys_ck { + sys_ck: sys_ck@60 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&osc_ck>; @@ -121,14 +121,14 @@ clock-frequency = <0x0>; }; - dpll_ck: dpll_ck { + dpll_ck: dpll_ck@500 { #clock-cells = <0>; compatible = "ti,omap2-dpll-core-clock"; clocks = <&sys_ck>, <&sys_ck>; reg = <0x0500>, <0x0540>; }; - apll96_ck: apll96_ck { + apll96_ck: apll96_ck@500 { #clock-cells = <0>; compatible = "ti,omap2-apll-clock"; clocks = <&sys_ck>; @@ -138,7 +138,7 @@ reg = <0x0500>, <0x0530>, <0x0520>; }; - apll54_ck: apll54_ck { + apll54_ck: apll54_ck@500 { #clock-cells = <0>; compatible = "ti,omap2-apll-clock"; clocks = <&sys_ck>; @@ -148,7 +148,7 @@ reg = <0x0500>, <0x0530>, <0x0520>; }; - func_54m_ck: func_54m_ck { + func_54m_ck: func_54m_ck@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&apll54_ck>, <&alt_ck>; @@ -176,7 +176,7 @@ clock-div = <2>; }; - func_48m_ck: func_48m_ck { + func_48m_ck: func_48m_ck@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&apll96_d2_ck>, <&alt_ck>; @@ -192,7 +192,7 @@ clock-div = <4>; }; - sys_clkout_src_gate: sys_clkout_src_gate { + sys_clkout_src_gate: sys_clkout_src_gate@70 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&core_ck>; @@ -200,7 +200,7 @@ reg = <0x0070>; }; - sys_clkout_src_mux: sys_clkout_src_mux { + sys_clkout_src_mux: sys_clkout_src_mux@70 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>; @@ -213,7 +213,7 @@ clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>; }; - sys_clkout: sys_clkout { + sys_clkout: sys_clkout@70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkout_src>; @@ -223,7 +223,7 @@ ti,index-power-of-two; }; - emul_ck: emul_ck { + emul_ck: emul_ck@78 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_54m_ck>; @@ -231,7 +231,7 @@ reg = <0x0078>; }; - mpu_ck: mpu_ck { + mpu_ck: mpu_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&core_ck>; @@ -240,7 +240,7 @@ ti,index-starts-at-one; }; - dsp_gate_fck: dsp_gate_fck { + dsp_gate_fck: dsp_gate_fck@800 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&core_ck>; @@ -248,7 +248,7 @@ reg = <0x0800>; }; - dsp_div_fck: dsp_div_fck { + dsp_div_fck: dsp_div_fck@840 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&core_ck>; @@ -261,7 +261,7 @@ clocks = <&dsp_gate_fck>, <&dsp_div_fck>; }; - core_l3_ck: core_l3_ck { + core_l3_ck: core_l3_ck@240 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&core_ck>; @@ -270,7 +270,7 @@ ti,index-starts-at-one; }; - gfx_3d_gate_fck: gfx_3d_gate_fck { + gfx_3d_gate_fck: gfx_3d_gate_fck@300 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&core_l3_ck>; @@ -278,7 +278,7 @@ reg = <0x0300>; }; - gfx_3d_div_fck: gfx_3d_div_fck { + gfx_3d_div_fck: gfx_3d_div_fck@340 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&core_l3_ck>; @@ -293,7 +293,7 @@ clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>; }; - gfx_2d_gate_fck: gfx_2d_gate_fck { + gfx_2d_gate_fck: gfx_2d_gate_fck@300 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&core_l3_ck>; @@ -301,7 +301,7 @@ reg = <0x0300>; }; - gfx_2d_div_fck: gfx_2d_div_fck { + gfx_2d_div_fck: gfx_2d_div_fck@340 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&core_l3_ck>; @@ -316,7 +316,7 @@ clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>; }; - gfx_ick: gfx_ick { + gfx_ick: gfx_ick@310 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_l3_ck>; @@ -324,7 +324,7 @@ reg = <0x0310>; }; - l4_ck: l4_ck { + l4_ck: l4_ck@240 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&core_l3_ck>; @@ -334,7 +334,7 @@ ti,index-starts-at-one; }; - dss_ick: dss_ick { + dss_ick: dss_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&l4_ck>; @@ -342,7 +342,7 @@ reg = <0x0210>; }; - dss1_gate_fck: dss1_gate_fck { + dss1_gate_fck: dss1_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&core_ck>; @@ -428,7 +428,7 @@ clock-div = <16>; }; - dss1_mux_fck: dss1_mux_fck { + dss1_mux_fck: dss1_mux_fck@240 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>; @@ -442,7 +442,7 @@ clocks = <&dss1_gate_fck>, <&dss1_mux_fck>; }; - dss2_gate_fck: dss2_gate_fck { + dss2_gate_fck: dss2_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&func_48m_ck>; @@ -450,7 +450,7 @@ reg = <0x0200>; }; - dss2_mux_fck: dss2_mux_fck { + dss2_mux_fck: dss2_mux_fck@240 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_ck>, <&func_48m_ck>; @@ -464,7 +464,7 @@ clocks = <&dss2_gate_fck>, <&dss2_mux_fck>; }; - dss_54m_fck: dss_54m_fck { + dss_54m_fck: dss_54m_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_54m_ck>; @@ -472,7 +472,7 @@ reg = <0x0200>; }; - ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck { + ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck@204 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&core_ck>; @@ -480,7 +480,7 @@ reg = <0x0204>; }; - ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck { + ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck@240 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&core_ck>; @@ -494,7 +494,7 @@ clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>; }; - usb_l4_gate_ick: usb_l4_gate_ick { + usb_l4_gate_ick: usb_l4_gate_ick@214 { #clock-cells = <0>; compatible = "ti,composite-interface-clock"; clocks = <&core_l3_ck>; @@ -502,7 +502,7 @@ reg = <0x0214>; }; - usb_l4_div_ick: usb_l4_div_ick { + usb_l4_div_ick: usb_l4_div_ick@240 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&core_l3_ck>; @@ -517,7 +517,7 @@ clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; }; - ssi_l4_ick: ssi_l4_ick { + ssi_l4_ick: ssi_l4_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -525,7 +525,7 @@ reg = <0x0214>; }; - gpt1_ick: gpt1_ick { + gpt1_ick: gpt1_ick@410 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&sys_ck>; @@ -533,7 +533,7 @@ reg = <0x0410>; }; - gpt1_gate_fck: gpt1_gate_fck { + gpt1_gate_fck: gpt1_gate_fck@400 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -541,7 +541,7 @@ reg = <0x0400>; }; - gpt1_mux_fck: gpt1_mux_fck { + gpt1_mux_fck: gpt1_mux_fck@440 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -554,7 +554,7 @@ clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; }; - gpt2_ick: gpt2_ick { + gpt2_ick: gpt2_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -562,7 +562,7 @@ reg = <0x0210>; }; - gpt2_gate_fck: gpt2_gate_fck { + gpt2_gate_fck: gpt2_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -570,7 +570,7 @@ reg = <0x0200>; }; - gpt2_mux_fck: gpt2_mux_fck { + gpt2_mux_fck: gpt2_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -584,7 +584,7 @@ clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; }; - gpt3_ick: gpt3_ick { + gpt3_ick: gpt3_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -592,7 +592,7 @@ reg = <0x0210>; }; - gpt3_gate_fck: gpt3_gate_fck { + gpt3_gate_fck: gpt3_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -600,7 +600,7 @@ reg = <0x0200>; }; - gpt3_mux_fck: gpt3_mux_fck { + gpt3_mux_fck: gpt3_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -614,7 +614,7 @@ clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; }; - gpt4_ick: gpt4_ick { + gpt4_ick: gpt4_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -622,7 +622,7 @@ reg = <0x0210>; }; - gpt4_gate_fck: gpt4_gate_fck { + gpt4_gate_fck: gpt4_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -630,7 +630,7 @@ reg = <0x0200>; }; - gpt4_mux_fck: gpt4_mux_fck { + gpt4_mux_fck: gpt4_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -644,7 +644,7 @@ clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; }; - gpt5_ick: gpt5_ick { + gpt5_ick: gpt5_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -652,7 +652,7 @@ reg = <0x0210>; }; - gpt5_gate_fck: gpt5_gate_fck { + gpt5_gate_fck: gpt5_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -660,7 +660,7 @@ reg = <0x0200>; }; - gpt5_mux_fck: gpt5_mux_fck { + gpt5_mux_fck: gpt5_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -674,7 +674,7 @@ clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; }; - gpt6_ick: gpt6_ick { + gpt6_ick: gpt6_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -682,7 +682,7 @@ reg = <0x0210>; }; - gpt6_gate_fck: gpt6_gate_fck { + gpt6_gate_fck: gpt6_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -690,7 +690,7 @@ reg = <0x0200>; }; - gpt6_mux_fck: gpt6_mux_fck { + gpt6_mux_fck: gpt6_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -704,7 +704,7 @@ clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; }; - gpt7_ick: gpt7_ick { + gpt7_ick: gpt7_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -712,7 +712,7 @@ reg = <0x0210>; }; - gpt7_gate_fck: gpt7_gate_fck { + gpt7_gate_fck: gpt7_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -720,7 +720,7 @@ reg = <0x0200>; }; - gpt7_mux_fck: gpt7_mux_fck { + gpt7_mux_fck: gpt7_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -734,7 +734,7 @@ clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; }; - gpt8_ick: gpt8_ick { + gpt8_ick: gpt8_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -742,7 +742,7 @@ reg = <0x0210>; }; - gpt8_gate_fck: gpt8_gate_fck { + gpt8_gate_fck: gpt8_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -750,7 +750,7 @@ reg = <0x0200>; }; - gpt8_mux_fck: gpt8_mux_fck { + gpt8_mux_fck: gpt8_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -764,7 +764,7 @@ clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; }; - gpt9_ick: gpt9_ick { + gpt9_ick: gpt9_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -772,7 +772,7 @@ reg = <0x0210>; }; - gpt9_gate_fck: gpt9_gate_fck { + gpt9_gate_fck: gpt9_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -780,7 +780,7 @@ reg = <0x0200>; }; - gpt9_mux_fck: gpt9_mux_fck { + gpt9_mux_fck: gpt9_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -794,7 +794,7 @@ clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>; }; - gpt10_ick: gpt10_ick { + gpt10_ick: gpt10_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -802,7 +802,7 @@ reg = <0x0210>; }; - gpt10_gate_fck: gpt10_gate_fck { + gpt10_gate_fck: gpt10_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -810,7 +810,7 @@ reg = <0x0200>; }; - gpt10_mux_fck: gpt10_mux_fck { + gpt10_mux_fck: gpt10_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -824,7 +824,7 @@ clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; }; - gpt11_ick: gpt11_ick { + gpt11_ick: gpt11_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -832,7 +832,7 @@ reg = <0x0210>; }; - gpt11_gate_fck: gpt11_gate_fck { + gpt11_gate_fck: gpt11_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -840,7 +840,7 @@ reg = <0x0200>; }; - gpt11_mux_fck: gpt11_mux_fck { + gpt11_mux_fck: gpt11_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -854,7 +854,7 @@ clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>; }; - gpt12_ick: gpt12_ick { + gpt12_ick: gpt12_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -862,7 +862,7 @@ reg = <0x0210>; }; - gpt12_gate_fck: gpt12_gate_fck { + gpt12_gate_fck: gpt12_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&func_32k_ck>; @@ -870,7 +870,7 @@ reg = <0x0200>; }; - gpt12_mux_fck: gpt12_mux_fck { + gpt12_mux_fck: gpt12_mux_fck@244 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>; @@ -884,7 +884,7 @@ clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>; }; - mcbsp1_ick: mcbsp1_ick { + mcbsp1_ick: mcbsp1_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -892,7 +892,7 @@ reg = <0x0210>; }; - mcbsp1_gate_fck: mcbsp1_gate_fck { + mcbsp1_gate_fck: mcbsp1_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; @@ -900,7 +900,7 @@ reg = <0x0200>; }; - mcbsp2_ick: mcbsp2_ick { + mcbsp2_ick: mcbsp2_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -908,7 +908,7 @@ reg = <0x0210>; }; - mcbsp2_gate_fck: mcbsp2_gate_fck { + mcbsp2_gate_fck: mcbsp2_gate_fck@200 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; @@ -916,7 +916,7 @@ reg = <0x0200>; }; - mcspi1_ick: mcspi1_ick { + mcspi1_ick: mcspi1_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -924,7 +924,7 @@ reg = <0x0210>; }; - mcspi1_fck: mcspi1_fck { + mcspi1_fck: mcspi1_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_48m_ck>; @@ -932,7 +932,7 @@ reg = <0x0200>; }; - mcspi2_ick: mcspi2_ick { + mcspi2_ick: mcspi2_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -940,7 +940,7 @@ reg = <0x0210>; }; - mcspi2_fck: mcspi2_fck { + mcspi2_fck: mcspi2_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_48m_ck>; @@ -948,7 +948,7 @@ reg = <0x0200>; }; - uart1_ick: uart1_ick { + uart1_ick: uart1_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -956,7 +956,7 @@ reg = <0x0210>; }; - uart1_fck: uart1_fck { + uart1_fck: uart1_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_48m_ck>; @@ -964,7 +964,7 @@ reg = <0x0200>; }; - uart2_ick: uart2_ick { + uart2_ick: uart2_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -972,7 +972,7 @@ reg = <0x0210>; }; - uart2_fck: uart2_fck { + uart2_fck: uart2_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_48m_ck>; @@ -980,7 +980,7 @@ reg = <0x0200>; }; - uart3_ick: uart3_ick { + uart3_ick: uart3_ick@214 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -988,7 +988,7 @@ reg = <0x0214>; }; - uart3_fck: uart3_fck { + uart3_fck: uart3_fck@204 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_48m_ck>; @@ -996,7 +996,7 @@ reg = <0x0204>; }; - gpios_ick: gpios_ick { + gpios_ick: gpios_ick@410 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&sys_ck>; @@ -1004,7 +1004,7 @@ reg = <0x0410>; }; - gpios_fck: gpios_fck { + gpios_fck: gpios_fck@400 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_32k_ck>; @@ -1012,7 +1012,7 @@ reg = <0x0400>; }; - mpu_wdt_ick: mpu_wdt_ick { + mpu_wdt_ick: mpu_wdt_ick@410 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&sys_ck>; @@ -1020,7 +1020,7 @@ reg = <0x0410>; }; - mpu_wdt_fck: mpu_wdt_fck { + mpu_wdt_fck: mpu_wdt_fck@400 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_32k_ck>; @@ -1028,7 +1028,7 @@ reg = <0x0400>; }; - sync_32k_ick: sync_32k_ick { + sync_32k_ick: sync_32k_ick@410 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&sys_ck>; @@ -1036,7 +1036,7 @@ reg = <0x0410>; }; - wdt1_ick: wdt1_ick { + wdt1_ick: wdt1_ick@410 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&sys_ck>; @@ -1044,7 +1044,7 @@ reg = <0x0410>; }; - omapctrl_ick: omapctrl_ick { + omapctrl_ick: omapctrl_ick@410 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&sys_ck>; @@ -1052,7 +1052,7 @@ reg = <0x0410>; }; - cam_fck: cam_fck { + cam_fck: cam_fck@200 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_96m_ck>; @@ -1060,7 +1060,7 @@ reg = <0x0200>; }; - cam_ick: cam_ick { + cam_ick: cam_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&l4_ck>; @@ -1068,7 +1068,7 @@ reg = <0x0210>; }; - mailboxes_ick: mailboxes_ick { + mailboxes_ick: mailboxes_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1076,7 +1076,7 @@ reg = <0x0210>; }; - wdt4_ick: wdt4_ick { + wdt4_ick: wdt4_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1084,7 +1084,7 @@ reg = <0x0210>; }; - wdt4_fck: wdt4_fck { + wdt4_fck: wdt4_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_32k_ck>; @@ -1092,7 +1092,7 @@ reg = <0x0200>; }; - mspro_ick: mspro_ick { + mspro_ick: mspro_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1100,7 +1100,7 @@ reg = <0x0210>; }; - mspro_fck: mspro_fck { + mspro_fck: mspro_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_96m_ck>; @@ -1108,7 +1108,7 @@ reg = <0x0200>; }; - fac_ick: fac_ick { + fac_ick: fac_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1116,7 +1116,7 @@ reg = <0x0210>; }; - fac_fck: fac_fck { + fac_fck: fac_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_12m_ck>; @@ -1124,7 +1124,7 @@ reg = <0x0200>; }; - hdq_ick: hdq_ick { + hdq_ick: hdq_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1132,7 +1132,7 @@ reg = <0x0210>; }; - hdq_fck: hdq_fck { + hdq_fck: hdq_fck@200 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_12m_ck>; @@ -1140,7 +1140,7 @@ reg = <0x0200>; }; - i2c1_ick: i2c1_ick { + i2c1_ick: i2c1_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1148,7 +1148,7 @@ reg = <0x0210>; }; - i2c2_ick: i2c2_ick { + i2c2_ick: i2c2_ick@210 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1156,7 +1156,7 @@ reg = <0x0210>; }; - gpmc_fck: gpmc_fck { + gpmc_fck: gpmc_fck@238 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; clocks = <&core_l3_ck>; @@ -1174,7 +1174,7 @@ clock-div = <1>; }; - sdma_ick: sdma_ick { + sdma_ick: sdma_ick@238 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; clocks = <&core_l3_ck>; @@ -1184,7 +1184,7 @@ ti,clock-mult = <1>; }; - sdrc_ick: sdrc_ick { + sdrc_ick: sdrc_ick@238 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; clocks = <&core_l3_ck>; @@ -1194,7 +1194,7 @@ ti,clock-mult = <1>; }; - des_ick: des_ick { + des_ick: des_ick@21c { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1202,7 +1202,7 @@ reg = <0x021c>; }; - sha_ick: sha_ick { + sha_ick: sha_ick@21c { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1210,7 +1210,7 @@ reg = <0x021c>; }; - rng_ick: rng_ick { + rng_ick: rng_ick@21c { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1218,7 +1218,7 @@ reg = <0x021c>; }; - aes_ick: aes_ick { + aes_ick: aes_ick@21c { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1226,7 +1226,7 @@ reg = <0x021c>; }; - pka_ick: pka_ick { + pka_ick: pka_ick@21c { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l4_ck>; @@ -1234,7 +1234,7 @@ reg = <0x021c>; }; - usb_fck: usb_fck { + usb_fck: usb_fck@204 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&func_48m_ck>; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index 4602866792be..a4deff0e2d52 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -390,6 +390,7 @@ interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ ti,nand-ecc-opt = "ham1"; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ nand-bus-width = <16>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/omap3-n9.dts b/arch/arm/boot/dts/omap3-n9.dts index 5c67429a4da7..b9e58c536afd 100644 --- a/arch/arm/boot/dts/omap3-n9.dts +++ b/arch/arm/boot/dts/omap3-n9.dts @@ -57,3 +57,17 @@ &modem { compatible = "nokia,n9-modem"; }; + +&lis302 { + st,axis-x = <1>; /* LIS3_DEV_X */ + st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ + st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ + + st,min-limit-x = <(-46)>; + st,min-limit-y = <3>; + st,min-limit-z = <3>; + + st,max-limit-x = <(-3)>; + st,max-limit-y = <46>; + st,max-limit-z = <46>; +}; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 858a25048102..a00ca761675d 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -14,6 +14,13 @@ cpus { cpu@0 { cpu0-supply = <&vcc>; + operating-points = < + /* kHz uV */ + 300000 1012500 + 600000 1200000 + 800000 1325000 + 1000000 1375000 + >; }; }; @@ -39,9 +46,34 @@ enable-active-high; regulator-boot-off; }; + + leds { + compatible = "gpio-leds"; + + heartbeat { + label = "debug::sleep"; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; /* gpio92 */ + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&debug_leds>; + }; + }; }; &omap3_pmx_core { + accelerator_pins: pinmux_accelerator_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT | MUX_MODE4) /* mcspi2_somi.gpio_180 -> LIS302 INT1 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT | MUX_MODE4) /* mcspi2_cs0.gpio_181 -> LIS302 INT2 */ + >; + }; + + debug_leds: pinmux_debug_led_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE4) /* dss_data22.gpio_92 */ + >; + }; + mmc2_pins: pinmux_mmc2_pins { pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk */ @@ -129,6 +161,30 @@ ti,pulldowns = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */ }; +&vdac { + regulator-name = "vdac"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vpll1 { + regulator-name = "vpll1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vpll2 { + regulator-name = "vpll2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vaux1 { + regulator-name = "vaux1"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + /* CSI-2 receiver */ &vaux2 { regulator-name = "vaux2"; @@ -143,12 +199,107 @@ regulator-max-microvolt = <2800000>; }; +&vaux4 { + regulator-name = "vaux4"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; + +&vmmc1 { + regulator-name = "vmmc1"; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <3150000>; +}; + +&vmmc2 { + regulator-name = "vmmc2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; +}; + +&vintana1 { + regulator-name = "vintana1"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; +}; + +&vintana2 { + regulator-name = "vintana2"; + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; +}; + +&vintdig { + regulator-name = "vintdig"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; +}; + +&vsim { + regulator-name = "vsim"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + +&vio { + regulator-name = "vio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + &i2c2 { clock-frequency = <400000>; }; &i2c3 { clock-frequency = <400000>; + + lis302: lis302@1d { + compatible = "st,lis3lv02d"; + reg = <0x1d>; + + Vdd-supply = <&vaux1>; + Vdd_IO-supply = <&vio>; + + pinctrl-names = "default"; + pinctrl-0 = <&accelerator_pins>; + + interrupts-extended = <&gpio6 20 IRQ_TYPE_EDGE_FALLING>, <&gpio6 21 IRQ_TYPE_EDGE_FALLING>; /* 180, 181 */ + + /* click flags */ + st,click-single-x; + st,click-single-y; + st,click-single-z; + + /* Limits are 0.5g * value */ + st,click-threshold-x = <8>; + st,click-threshold-y = <8>; + st,click-threshold-z = <10>; + + /* Click must be longer than time limit */ + st,click-time-limit = <9>; + + /* Kind of debounce filter */ + st,click-latency = <50>; + + st,wakeup-x-hi; + st,wakeup-y-hi; + st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ + + st,wakeup2-z-hi; + st,wakeup2-threshold = <(1000/18)>; /* millig-value / 18 to get HW values */ + + st,highpass-cutoff-hz = <2>; + + /* Interrupt line 1 for thresholds */ + st,irq1-ff-wu-1; + st,irq1-ff-wu-2; + /* Interrupt line 2 for click detection */ + st,irq2-click; + + st,wu-duration-1 = <8>; + st,wu-duration-2 = <8>; + }; }; &mmc1 { diff --git a/arch/arm/boot/dts/omap3-n950.dts b/arch/arm/boot/dts/omap3-n950.dts index 7f219a9dc5be..646601a3ebd8 100644 --- a/arch/arm/boot/dts/omap3-n950.dts +++ b/arch/arm/boot/dts/omap3-n950.dts @@ -11,10 +11,33 @@ /dts-v1/; #include "omap3-n950-n9.dtsi" +#include <dt-bindings/input/input.h> / { model = "Nokia N950"; compatible = "nokia,omap3-n950", "ti,omap36xx", "ti,omap3"; + + keys { + compatible = "gpio-keys"; + + keypad_slide { + label = "Keypad Slide"; + gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; /* 109 */ + linux,input-type = <EV_SW>; + linux,code = <SW_KEYPAD_SLIDE>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&keypad_slide_pins>; + }; + }; +}; + +&omap3_pmx_core { + keypad_slide_pins: pinmux_debug_led_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212a, PIN_INPUT | MUX_MODE4) /* cam_d10.gpio_109 */ + >; + }; }; &omap3_pmx_core { @@ -86,3 +109,79 @@ &modem { compatible = "nokia,n950-modem"; }; + +&twl { + twl_audio: audio { + compatible = "ti,twl4030-audio"; + ti,enable-vibra = <1>; + }; +}; + +&twl_keypad { + linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_BACKSLASH) + MATRIX_KEY(0x01, 0x00, KEY_LEFTSHIFT) + MATRIX_KEY(0x02, 0x00, KEY_COMPOSE) + MATRIX_KEY(0x03, 0x00, KEY_LEFTMETA) + MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL) + MATRIX_KEY(0x05, 0x00, KEY_BACKSPACE) + MATRIX_KEY(0x06, 0x00, KEY_VOLUMEDOWN) + MATRIX_KEY(0x07, 0x00, KEY_VOLUMEUP) + + MATRIX_KEY(0x03, 0x01, KEY_Z) + MATRIX_KEY(0x04, 0x01, KEY_A) + MATRIX_KEY(0x05, 0x01, KEY_Q) + MATRIX_KEY(0x06, 0x01, KEY_W) + MATRIX_KEY(0x07, 0x01, KEY_E) + + MATRIX_KEY(0x03, 0x02, KEY_X) + MATRIX_KEY(0x04, 0x02, KEY_S) + MATRIX_KEY(0x05, 0x02, KEY_D) + MATRIX_KEY(0x06, 0x02, KEY_C) + MATRIX_KEY(0x07, 0x02, KEY_V) + + MATRIX_KEY(0x03, 0x03, KEY_O) + MATRIX_KEY(0x04, 0x03, KEY_I) + MATRIX_KEY(0x05, 0x03, KEY_U) + MATRIX_KEY(0x06, 0x03, KEY_L) + MATRIX_KEY(0x07, 0x03, KEY_APOSTROPHE) + + MATRIX_KEY(0x03, 0x04, KEY_Y) + MATRIX_KEY(0x04, 0x04, KEY_K) + MATRIX_KEY(0x05, 0x04, KEY_J) + MATRIX_KEY(0x06, 0x04, KEY_H) + MATRIX_KEY(0x07, 0x04, KEY_G) + + MATRIX_KEY(0x03, 0x05, KEY_B) + MATRIX_KEY(0x04, 0x05, KEY_COMMA) + MATRIX_KEY(0x05, 0x05, KEY_M) + MATRIX_KEY(0x06, 0x05, KEY_N) + MATRIX_KEY(0x07, 0x05, KEY_DOT) + + MATRIX_KEY(0x00, 0x06, KEY_SPACE) + MATRIX_KEY(0x03, 0x06, KEY_T) + MATRIX_KEY(0x04, 0x06, KEY_UP) + MATRIX_KEY(0x05, 0x06, KEY_LEFT) + MATRIX_KEY(0x06, 0x06, KEY_RIGHT) + MATRIX_KEY(0x07, 0x06, KEY_DOWN) + + MATRIX_KEY(0x03, 0x07, KEY_P) + MATRIX_KEY(0x04, 0x07, KEY_ENTER) + MATRIX_KEY(0x05, 0x07, KEY_SLASH) + MATRIX_KEY(0x06, 0x07, KEY_F) + MATRIX_KEY(0x07, 0x07, KEY_R) + >; +}; + +&lis302 { + st,axis-x = <(-2)>; /* LIS3_INV_DEV_Y */ + st,axis-y = <(-1)>; /* LIS3_INV_DEV_X */ + st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ + + st,min-limit-x = <(-32)>; + st,min-limit-y = <3>; + st,min-limit-z = <3>; + + st,max-limit-x = <(-3)>; + st,max-limit-y = <32>; + st,max-limit-z = <32>; +}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index b41d07e8e765..9fbda38528dc 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -43,7 +43,7 @@ }; }; - pmu { + pmu@54000000 { compatible = "arm,cortex-a8-pmu"; reg = <0x54000000 0x800000>; interrupts = <3>; @@ -119,7 +119,7 @@ #size-cells = <1>; ranges = <0 0x270 0x330>; - pbias_regulator: pbias_regulator { + pbias_regulator: pbias_regulator@2b0 { compatible = "ti,pbias-omap3", "ti,pbias-omap"; reg = <0x2b0 0x4>; syscon = <&scm_conf>; @@ -725,6 +725,8 @@ #size-cells = <1>; interrupt-controller; #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; usb_otg_hs: usb_otg_hs@480ab000 { diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi index 4c22f3a7f813..86de819a0dcf 100644 --- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi +++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &cm_clocks { - gfx_l3_ck: gfx_l3_ck { + gfx_l3_ck: gfx_l3_ck@b10 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&l3_ick>; @@ -16,7 +16,7 @@ ti,bit-shift = <0>; }; - gfx_l3_fck: gfx_l3_fck { + gfx_l3_fck: gfx_l3_fck@b40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&l3_ick>; @@ -33,7 +33,7 @@ clock-div = <1>; }; - gfx_cg1_ck: gfx_cg1_ck { + gfx_cg1_ck: gfx_cg1_ck@b00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&gfx_l3_fck>; @@ -41,7 +41,7 @@ ti,bit-shift = <1>; }; - gfx_cg2_ck: gfx_cg2_ck { + gfx_cg2_ck: gfx_cg2_ck@b00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&gfx_l3_fck>; @@ -49,7 +49,7 @@ ti,bit-shift = <2>; }; - d2d_26m_fck: d2d_26m_fck { + d2d_26m_fck: d2d_26m_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&sys_ck>; @@ -57,7 +57,7 @@ ti,bit-shift = <3>; }; - fshostusb_fck: fshostusb_fck { + fshostusb_fck: fshostusb_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; @@ -65,7 +65,7 @@ ti,bit-shift = <5>; }; - ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 { + ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&corex2_fck>; @@ -73,7 +73,7 @@ reg = <0x0a00>; }; - ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 { + ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&corex2_fck>; @@ -96,7 +96,7 @@ clock-div = <2>; }; - hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 { + hsotgusb_ick_3430es1: hsotgusb_ick_3430es1@a10 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&core_l3_ick>; @@ -104,7 +104,7 @@ ti,bit-shift = <4>; }; - fac_ick: fac_ick { + fac_ick: fac_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -120,7 +120,7 @@ clock-div = <1>; }; - ssi_ick: ssi_ick_3430es1 { + ssi_ick: ssi_ick_3430es1@a10 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&ssi_l4_ick>; @@ -128,7 +128,7 @@ ti,bit-shift = <0>; }; - usb_l4_gate_ick: usb_l4_gate_ick { + usb_l4_gate_ick: usb_l4_gate_ick@a10 { #clock-cells = <0>; compatible = "ti,composite-interface-clock"; clocks = <&l4_ick>; @@ -136,7 +136,7 @@ reg = <0x0a10>; }; - usb_l4_div_ick: usb_l4_div_ick { + usb_l4_div_ick: usb_l4_div_ick@a40 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&l4_ick>; @@ -152,7 +152,7 @@ clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>; }; - dss1_alwon_fck: dss1_alwon_fck_3430es1 { + dss1_alwon_fck: dss1_alwon_fck_3430es1@e00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m4x2_ck>; @@ -161,7 +161,7 @@ ti,set-rate-parent; }; - dss_ick: dss_ick_3430es1 { + dss_ick: dss_ick_3430es1@e10 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&l4_ick>; diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi index b02017b7630e..858aa0796ec8 100644 --- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi @@ -16,7 +16,7 @@ clock-div = <1>; }; - aes1_ick: aes1_ick { + aes1_ick: aes1_ick@a14 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&security_l4_ick2>; @@ -24,7 +24,7 @@ reg = <0x0a14>; }; - rng_ick: rng_ick { + rng_ick: rng_ick@a14 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&security_l4_ick2>; @@ -32,7 +32,7 @@ ti,bit-shift = <2>; }; - sha11_ick: sha11_ick { + sha11_ick: sha11_ick@a14 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&security_l4_ick2>; @@ -40,7 +40,7 @@ ti,bit-shift = <1>; }; - des1_ick: des1_ick { + des1_ick: des1_ick@a14 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&security_l4_ick2>; @@ -48,7 +48,7 @@ ti,bit-shift = <0>; }; - cam_mclk: cam_mclk { + cam_mclk: cam_mclk@f00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m5x2_ck>; @@ -57,7 +57,7 @@ ti,set-rate-parent; }; - cam_ick: cam_ick { + cam_ick: cam_ick@f10 { #clock-cells = <0>; compatible = "ti,omap3-no-wait-interface-clock"; clocks = <&l4_ick>; @@ -65,7 +65,7 @@ ti,bit-shift = <0>; }; - csi2_96m_fck: csi2_96m_fck { + csi2_96m_fck: csi2_96m_fck@f00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&core_96m_fck>; @@ -81,7 +81,7 @@ clock-div = <1>; }; - pka_ick: pka_ick { + pka_ick: pka_ick@a14 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&security_l3_ick>; @@ -89,7 +89,7 @@ ti,bit-shift = <4>; }; - icr_ick: icr_ick { + icr_ick: icr_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -97,7 +97,7 @@ ti,bit-shift = <29>; }; - des2_ick: des2_ick { + des2_ick: des2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -105,7 +105,7 @@ ti,bit-shift = <26>; }; - mspro_ick: mspro_ick { + mspro_ick: mspro_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -113,7 +113,7 @@ ti,bit-shift = <23>; }; - mailboxes_ick: mailboxes_ick { + mailboxes_ick: mailboxes_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -129,7 +129,7 @@ clock-div = <1>; }; - sr1_fck: sr1_fck { + sr1_fck: sr1_fck@c00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&sys_ck>; @@ -137,7 +137,7 @@ ti,bit-shift = <6>; }; - sr2_fck: sr2_fck { + sr2_fck: sr2_fck@c00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&sys_ck>; @@ -153,7 +153,7 @@ clock-div = <1>; }; - dpll2_fck: dpll2_fck { + dpll2_fck: dpll2_fck@40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&core_ck>; @@ -163,7 +163,7 @@ ti,index-starts-at-one; }; - dpll2_ck: dpll2_ck { + dpll2_ck: dpll2_ck@4 { #clock-cells = <0>; compatible = "ti,omap3-dpll-clock"; clocks = <&sys_ck>, <&dpll2_fck>; @@ -173,7 +173,7 @@ ti,low-power-bypass; }; - dpll2_m2_ck: dpll2_m2_ck { + dpll2_m2_ck: dpll2_m2_ck@44 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll2_ck>; @@ -182,7 +182,7 @@ ti,index-starts-at-one; }; - iva2_ck: iva2_ck { + iva2_ck: iva2_ck@0 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&dpll2_m2_ck>; @@ -190,7 +190,7 @@ ti,bit-shift = <0>; }; - modem_fck: modem_fck { + modem_fck: modem_fck@a00 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&sys_ck>; @@ -198,7 +198,7 @@ ti,bit-shift = <31>; }; - sad2d_ick: sad2d_ick { + sad2d_ick: sad2d_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l3_ick>; @@ -206,7 +206,7 @@ ti,bit-shift = <3>; }; - mad2d_ick: mad2d_ick { + mad2d_ick: mad2d_ick@a18 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&l3_ick>; @@ -214,7 +214,7 @@ ti,bit-shift = <3>; }; - mspro_fck: mspro_fck { + mspro_fck: mspro_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index 96f8ce7bd2af..e44656258225 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -55,7 +55,7 @@ }; }; - bandgap { + bandgap@48002524 { reg = <0x48002524 0x4>; compatible = "ti,omap34xx-bandgap"; #thermal-sensor-cells = <0>; diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi index 080fb3f4e429..15d18669000e 100644 --- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi @@ -25,7 +25,7 @@ }; }; &cm_clocks { - dpll5_ck: dpll5_ck { + dpll5_ck: dpll5_ck@d04 { #clock-cells = <0>; compatible = "ti,omap3-dpll-clock"; clocks = <&sys_ck>, <&sys_ck>; @@ -34,7 +34,7 @@ ti,lock; }; - dpll5_m2_ck: dpll5_m2_ck { + dpll5_m2_ck: dpll5_m2_ck@d50 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll5_ck>; @@ -43,7 +43,7 @@ ti,index-starts-at-one; }; - sgx_gate_fck: sgx_gate_fck { + sgx_gate_fck: sgx_gate_fck@b00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&core_ck>; @@ -91,7 +91,7 @@ clock-div = <2>; }; - sgx_mux_fck: sgx_mux_fck { + sgx_mux_fck: sgx_mux_fck@b40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>; @@ -104,7 +104,7 @@ clocks = <&sgx_gate_fck>, <&sgx_mux_fck>; }; - sgx_ick: sgx_ick { + sgx_ick: sgx_ick@b10 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&l3_ick>; @@ -112,7 +112,7 @@ ti,bit-shift = <0>; }; - cpefuse_fck: cpefuse_fck { + cpefuse_fck: cpefuse_fck@a08 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_ck>; @@ -120,7 +120,7 @@ ti,bit-shift = <0>; }; - ts_fck: ts_fck { + ts_fck: ts_fck@a08 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&omap_32k_fck>; @@ -128,7 +128,7 @@ ti,bit-shift = <1>; }; - usbtll_fck: usbtll_fck { + usbtll_fck: usbtll_fck@a08 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&dpll5_m2_ck>; @@ -136,7 +136,7 @@ ti,bit-shift = <2>; }; - usbtll_ick: usbtll_ick { + usbtll_ick: usbtll_ick@a18 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -144,7 +144,7 @@ ti,bit-shift = <2>; }; - mmchs3_ick: mmchs3_ick { + mmchs3_ick: mmchs3_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -152,7 +152,7 @@ ti,bit-shift = <30>; }; - mmchs3_fck: mmchs3_fck { + mmchs3_fck: mmchs3_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; @@ -160,7 +160,7 @@ ti,bit-shift = <30>; }; - dss1_alwon_fck: dss1_alwon_fck_3430es2 { + dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 { #clock-cells = <0>; compatible = "ti,dss-gate-clock"; clocks = <&dpll4_m4x2_ck>; @@ -169,7 +169,7 @@ ti,set-rate-parent; }; - dss_ick: dss_ick_3430es2 { + dss_ick: dss_ick_3430es2@e10 { #clock-cells = <0>; compatible = "ti,omap3-dss-interface-clock"; clocks = <&l4_ick>; @@ -177,7 +177,7 @@ ti,bit-shift = <0>; }; - usbhost_120m_fck: usbhost_120m_fck { + usbhost_120m_fck: usbhost_120m_fck@1400 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll5_m2_ck>; @@ -185,7 +185,7 @@ ti,bit-shift = <1>; }; - usbhost_48m_fck: usbhost_48m_fck { + usbhost_48m_fck: usbhost_48m_fck@1400 { #clock-cells = <0>; compatible = "ti,dss-gate-clock"; clocks = <&omap_48m_fck>; @@ -193,7 +193,7 @@ ti,bit-shift = <0>; }; - usbhost_ick: usbhost_ick { + usbhost_ick: usbhost_ick@1410 { #clock-cells = <0>; compatible = "ti,omap3-dss-interface-clock"; clocks = <&l4_ick>; diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi index 200ae3a5cbbb..a21d1f021267 100644 --- a/arch/arm/boot/dts/omap36xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi @@ -8,14 +8,14 @@ * published by the Free Software Foundation. */ &cm_clocks { - dpll4_ck: dpll4_ck { + dpll4_ck: dpll4_ck@d00 { #clock-cells = <0>; compatible = "ti,omap3-dpll-per-j-type-clock"; clocks = <&sys_ck>, <&sys_ck>; reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; }; - dpll4_m5x2_ck: dpll4_m5x2_ck { + dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m5x2_mul_ck>; @@ -25,7 +25,7 @@ ti,set-bit-to-disable; }; - dpll4_m2x2_ck: dpll4_m2x2_ck { + dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m2x2_mul_ck>; @@ -34,7 +34,7 @@ ti,set-bit-to-disable; }; - dpll3_m3x2_ck: dpll3_m3x2_ck { + dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll3_m3x2_mul_ck>; @@ -43,7 +43,7 @@ ti,set-bit-to-disable; }; - dpll4_m3x2_ck: dpll4_m3x2_ck { + dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m3x2_mul_ck>; @@ -52,7 +52,7 @@ ti,set-bit-to-disable; }; - dpll4_m6x2_ck: dpll4_m6x2_ck { + dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { #clock-cells = <0>; compatible = "ti,hsdiv-gate-clock"; clocks = <&dpll4_m6x2_mul_ck>; @@ -61,7 +61,7 @@ ti,set-bit-to-disable; }; - uart4_fck: uart4_fck { + uart4_fck: uart4_fck@1000 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&per_48m_fck>; diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi index 877318c28364..1a4fbdf0d9cc 100644 --- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi +++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &cm_clocks { - ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 { + ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&corex2_fck>; @@ -16,7 +16,7 @@ reg = <0x0a00>; }; - ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 { + ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&corex2_fck>; @@ -39,7 +39,7 @@ clock-div = <2>; }; - hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 { + hsotgusb_ick_3430es2: hsotgusb_ick_3430es2@a10 { #clock-cells = <0>; compatible = "ti,omap3-hsotgusb-interface-clock"; clocks = <&core_l3_ick>; @@ -55,7 +55,7 @@ clock-div = <1>; }; - ssi_ick: ssi_ick_3430es2 { + ssi_ick: ssi_ick_3430es2@a10 { #clock-cells = <0>; compatible = "ti,omap3-ssi-interface-clock"; clocks = <&ssi_l4_ick>; @@ -63,7 +63,7 @@ ti,bit-shift = <0>; }; - usim_gate_fck: usim_gate_fck { + usim_gate_fck: usim_gate_fck@c00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&omap_96m_fck>; @@ -143,7 +143,7 @@ clock-div = <20>; }; - usim_mux_fck: usim_mux_fck { + usim_mux_fck: usim_mux_fck@c40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>; @@ -158,7 +158,7 @@ clocks = <&usim_gate_fck>, <&usim_mux_fck>; }; - usim_ick: usim_ick { + usim_ick: usim_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index f19c87bd6bf3..8b7979153008 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -44,7 +44,7 @@ abb_mpu_iva: regulator-abb-mpu { compatible = "ti,abb-v1"; regulator-name = "abb_mpu_iva"; - #address-cell = <0>; + #address-cells = <0>; #size-cells = <0>; reg = <0x483072f0 0x8>, <0x48306818 0x4>; reg-names = "base-address", "int-address"; @@ -87,7 +87,7 @@ }; }; - bandgap { + bandgap@48002524 { reg = <0x48002524 0x4>; compatible = "ti,omap36xx-bandgap"; #thermal-sensor-cells = <0>; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index bbba5bdc4bc9..9bd91641aa7c 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -14,14 +14,14 @@ clock-frequency = <16800000>; }; - osc_sys_ck: osc_sys_ck { + osc_sys_ck: osc_sys_ck@d40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>; reg = <0x0d40>; }; - sys_ck: sys_ck { + sys_ck: sys_ck@1270 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&osc_sys_ck>; @@ -31,7 +31,7 @@ ti,index-starts-at-one; }; - sys_clkout1: sys_clkout1 { + sys_clkout1: sys_clkout1@d70 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&osc_sys_ck>; @@ -81,7 +81,7 @@ }; &scm_clocks { - mcbsp5_mux_fck: mcbsp5_mux_fck { + mcbsp5_mux_fck: mcbsp5_mux_fck@68 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_96m_fck>, <&mcbsp_clks>; @@ -95,7 +95,7 @@ clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>; }; - mcbsp1_mux_fck: mcbsp1_mux_fck { + mcbsp1_mux_fck: mcbsp1_mux_fck@4 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_96m_fck>, <&mcbsp_clks>; @@ -109,7 +109,7 @@ clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>; }; - mcbsp2_mux_fck: mcbsp2_mux_fck { + mcbsp2_mux_fck: mcbsp2_mux_fck@4 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; @@ -123,7 +123,7 @@ clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>; }; - mcbsp3_mux_fck: mcbsp3_mux_fck { + mcbsp3_mux_fck: mcbsp3_mux_fck@68 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; @@ -136,7 +136,7 @@ clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>; }; - mcbsp4_mux_fck: mcbsp4_mux_fck { + mcbsp4_mux_fck: mcbsp4_mux_fck@68 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; @@ -193,14 +193,14 @@ clock-frequency = <38400000>; }; - dpll4_ck: dpll4_ck { + dpll4_ck: dpll4_ck@d00 { #clock-cells = <0>; compatible = "ti,omap3-dpll-per-clock"; clocks = <&sys_ck>, <&sys_ck>; reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>; }; - dpll4_m2_ck: dpll4_m2_ck { + dpll4_m2_ck: dpll4_m2_ck@d48 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; @@ -217,7 +217,7 @@ clock-div = <1>; }; - dpll4_m2x2_ck: dpll4_m2x2_ck { + dpll4_m2x2_ck: dpll4_m2x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m2x2_mul_ck>; @@ -234,14 +234,14 @@ clock-div = <1>; }; - dpll3_ck: dpll3_ck { + dpll3_ck: dpll3_ck@d00 { #clock-cells = <0>; compatible = "ti,omap3-dpll-core-clock"; clocks = <&sys_ck>, <&sys_ck>; reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>; }; - dpll3_m3_ck: dpll3_m3_ck { + dpll3_m3_ck: dpll3_m3_ck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll3_ck>; @@ -259,7 +259,7 @@ clock-div = <1>; }; - dpll3_m3x2_ck: dpll3_m3x2_ck { + dpll3_m3x2_ck: dpll3_m3x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll3_m3x2_mul_ck>; @@ -288,7 +288,7 @@ clock-frequency = <0x0>; }; - dpll3_m2_ck: dpll3_m2_ck { + dpll3_m2_ck: dpll3_m2_ck@d40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll3_ck>; @@ -306,7 +306,7 @@ clock-div = <1>; }; - dpll1_fck: dpll1_fck { + dpll1_fck: dpll1_fck@940 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&core_ck>; @@ -316,7 +316,7 @@ ti,index-starts-at-one; }; - dpll1_ck: dpll1_ck { + dpll1_ck: dpll1_ck@904 { #clock-cells = <0>; compatible = "ti,omap3-dpll-clock"; clocks = <&sys_ck>, <&dpll1_fck>; @@ -331,7 +331,7 @@ clock-div = <1>; }; - dpll1_x2m2_ck: dpll1_x2m2_ck { + dpll1_x2m2_ck: dpll1_x2m2_ck@944 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll1_x2_ck>; @@ -348,7 +348,7 @@ clock-div = <1>; }; - omap_96m_fck: omap_96m_fck { + omap_96m_fck: omap_96m_fck@d40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&cm_96m_fck>, <&sys_ck>; @@ -356,7 +356,7 @@ reg = <0x0d40>; }; - dpll4_m3_ck: dpll4_m3_ck { + dpll4_m3_ck: dpll4_m3_ck@e40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; @@ -374,7 +374,7 @@ clock-div = <1>; }; - dpll4_m3x2_ck: dpll4_m3x2_ck { + dpll4_m3x2_ck: dpll4_m3x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m3x2_mul_ck>; @@ -383,7 +383,7 @@ ti,set-bit-to-disable; }; - omap_54m_fck: omap_54m_fck { + omap_54m_fck: omap_54m_fck@d40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll4_m3x2_ck>, <&sys_altclk>; @@ -399,7 +399,7 @@ clock-div = <2>; }; - omap_48m_fck: omap_48m_fck { + omap_48m_fck: omap_48m_fck@d40 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&cm_96m_d2_fck>, <&sys_altclk>; @@ -415,7 +415,7 @@ clock-div = <4>; }; - dpll4_m4_ck: dpll4_m4_ck { + dpll4_m4_ck: dpll4_m4_ck@e40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; @@ -433,7 +433,7 @@ ti,set-rate-parent; }; - dpll4_m4x2_ck: dpll4_m4x2_ck { + dpll4_m4x2_ck: dpll4_m4x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m4x2_mul_ck>; @@ -443,7 +443,7 @@ ti,set-rate-parent; }; - dpll4_m5_ck: dpll4_m5_ck { + dpll4_m5_ck: dpll4_m5_ck@f40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; @@ -461,7 +461,7 @@ ti,set-rate-parent; }; - dpll4_m5x2_ck: dpll4_m5x2_ck { + dpll4_m5x2_ck: dpll4_m5x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m5x2_mul_ck>; @@ -471,7 +471,7 @@ ti,set-rate-parent; }; - dpll4_m6_ck: dpll4_m6_ck { + dpll4_m6_ck: dpll4_m6_ck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll4_ck>; @@ -489,7 +489,7 @@ clock-div = <1>; }; - dpll4_m6x2_ck: dpll4_m6x2_ck { + dpll4_m6x2_ck: dpll4_m6x2_ck@d00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll4_m6x2_mul_ck>; @@ -506,7 +506,7 @@ clock-div = <1>; }; - clkout2_src_gate_ck: clkout2_src_gate_ck { + clkout2_src_gate_ck: clkout2_src_gate_ck@d70 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&core_ck>; @@ -514,7 +514,7 @@ reg = <0x0d70>; }; - clkout2_src_mux_ck: clkout2_src_mux_ck { + clkout2_src_mux_ck: clkout2_src_mux_ck@d70 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>; @@ -527,7 +527,7 @@ clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>; }; - sys_clkout2: sys_clkout2 { + sys_clkout2: sys_clkout2@d70 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&clkout2_src_ck>; @@ -545,7 +545,7 @@ clock-div = <1>; }; - arm_fck: arm_fck { + arm_fck: arm_fck@924 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mpu_ck>; @@ -561,7 +561,7 @@ clock-div = <1>; }; - l3_ick: l3_ick { + l3_ick: l3_ick@a40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&core_ck>; @@ -570,7 +570,7 @@ ti,index-starts-at-one; }; - l4_ick: l4_ick { + l4_ick: l4_ick@a40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&l3_ick>; @@ -580,7 +580,7 @@ ti,index-starts-at-one; }; - rm_ick: rm_ick { + rm_ick: rm_ick@c40 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&l4_ick>; @@ -590,7 +590,7 @@ ti,index-starts-at-one; }; - gpt10_gate_fck: gpt10_gate_fck { + gpt10_gate_fck: gpt10_gate_fck@a00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -598,7 +598,7 @@ reg = <0x0a00>; }; - gpt10_mux_fck: gpt10_mux_fck { + gpt10_mux_fck: gpt10_mux_fck@a40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -612,7 +612,7 @@ clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>; }; - gpt11_gate_fck: gpt11_gate_fck { + gpt11_gate_fck: gpt11_gate_fck@a00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -620,7 +620,7 @@ reg = <0x0a00>; }; - gpt11_mux_fck: gpt11_mux_fck { + gpt11_mux_fck: gpt11_mux_fck@a40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -642,7 +642,7 @@ clock-div = <1>; }; - mmchs2_fck: mmchs2_fck { + mmchs2_fck: mmchs2_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; @@ -650,7 +650,7 @@ ti,bit-shift = <25>; }; - mmchs1_fck: mmchs1_fck { + mmchs1_fck: mmchs1_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; @@ -658,7 +658,7 @@ ti,bit-shift = <24>; }; - i2c3_fck: i2c3_fck { + i2c3_fck: i2c3_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; @@ -666,7 +666,7 @@ ti,bit-shift = <17>; }; - i2c2_fck: i2c2_fck { + i2c2_fck: i2c2_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; @@ -674,7 +674,7 @@ ti,bit-shift = <16>; }; - i2c1_fck: i2c1_fck { + i2c1_fck: i2c1_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_96m_fck>; @@ -682,7 +682,7 @@ ti,bit-shift = <15>; }; - mcbsp5_gate_fck: mcbsp5_gate_fck { + mcbsp5_gate_fck: mcbsp5_gate_fck@a00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; @@ -690,7 +690,7 @@ reg = <0x0a00>; }; - mcbsp1_gate_fck: mcbsp1_gate_fck { + mcbsp1_gate_fck: mcbsp1_gate_fck@a00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; @@ -706,7 +706,7 @@ clock-div = <1>; }; - mcspi4_fck: mcspi4_fck { + mcspi4_fck: mcspi4_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; @@ -714,7 +714,7 @@ ti,bit-shift = <21>; }; - mcspi3_fck: mcspi3_fck { + mcspi3_fck: mcspi3_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; @@ -722,7 +722,7 @@ ti,bit-shift = <20>; }; - mcspi2_fck: mcspi2_fck { + mcspi2_fck: mcspi2_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; @@ -730,7 +730,7 @@ ti,bit-shift = <19>; }; - mcspi1_fck: mcspi1_fck { + mcspi1_fck: mcspi1_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; @@ -738,7 +738,7 @@ ti,bit-shift = <18>; }; - uart2_fck: uart2_fck { + uart2_fck: uart2_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; @@ -746,7 +746,7 @@ ti,bit-shift = <14>; }; - uart1_fck: uart1_fck { + uart1_fck: uart1_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_48m_fck>; @@ -762,7 +762,7 @@ clock-div = <1>; }; - hdq_fck: hdq_fck { + hdq_fck: hdq_fck@a00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_12m_fck>; @@ -778,7 +778,7 @@ clock-div = <1>; }; - sdrc_ick: sdrc_ick { + sdrc_ick: sdrc_ick@a10 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&core_l3_ick>; @@ -802,7 +802,7 @@ clock-div = <1>; }; - mmchs2_ick: mmchs2_ick { + mmchs2_ick: mmchs2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -810,7 +810,7 @@ ti,bit-shift = <25>; }; - mmchs1_ick: mmchs1_ick { + mmchs1_ick: mmchs1_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -818,7 +818,7 @@ ti,bit-shift = <24>; }; - hdq_ick: hdq_ick { + hdq_ick: hdq_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -826,7 +826,7 @@ ti,bit-shift = <22>; }; - mcspi4_ick: mcspi4_ick { + mcspi4_ick: mcspi4_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -834,7 +834,7 @@ ti,bit-shift = <21>; }; - mcspi3_ick: mcspi3_ick { + mcspi3_ick: mcspi3_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -842,7 +842,7 @@ ti,bit-shift = <20>; }; - mcspi2_ick: mcspi2_ick { + mcspi2_ick: mcspi2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -850,7 +850,7 @@ ti,bit-shift = <19>; }; - mcspi1_ick: mcspi1_ick { + mcspi1_ick: mcspi1_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -858,7 +858,7 @@ ti,bit-shift = <18>; }; - i2c3_ick: i2c3_ick { + i2c3_ick: i2c3_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -866,7 +866,7 @@ ti,bit-shift = <17>; }; - i2c2_ick: i2c2_ick { + i2c2_ick: i2c2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -874,7 +874,7 @@ ti,bit-shift = <16>; }; - i2c1_ick: i2c1_ick { + i2c1_ick: i2c1_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -882,7 +882,7 @@ ti,bit-shift = <15>; }; - uart2_ick: uart2_ick { + uart2_ick: uart2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -890,7 +890,7 @@ ti,bit-shift = <14>; }; - uart1_ick: uart1_ick { + uart1_ick: uart1_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -898,7 +898,7 @@ ti,bit-shift = <13>; }; - gpt11_ick: gpt11_ick { + gpt11_ick: gpt11_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -906,7 +906,7 @@ ti,bit-shift = <12>; }; - gpt10_ick: gpt10_ick { + gpt10_ick: gpt10_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -914,7 +914,7 @@ ti,bit-shift = <11>; }; - mcbsp5_ick: mcbsp5_ick { + mcbsp5_ick: mcbsp5_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -922,7 +922,7 @@ ti,bit-shift = <10>; }; - mcbsp1_ick: mcbsp1_ick { + mcbsp1_ick: mcbsp1_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -930,7 +930,7 @@ ti,bit-shift = <9>; }; - omapctrl_ick: omapctrl_ick { + omapctrl_ick: omapctrl_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -938,7 +938,7 @@ ti,bit-shift = <6>; }; - dss_tv_fck: dss_tv_fck { + dss_tv_fck: dss_tv_fck@e00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&omap_54m_fck>; @@ -946,7 +946,7 @@ ti,bit-shift = <2>; }; - dss_96m_fck: dss_96m_fck { + dss_96m_fck: dss_96m_fck@e00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&omap_96m_fck>; @@ -954,7 +954,7 @@ ti,bit-shift = <2>; }; - dss2_alwon_fck: dss2_alwon_fck { + dss2_alwon_fck: dss2_alwon_fck@e00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_ck>; @@ -968,7 +968,7 @@ clock-frequency = <0>; }; - gpt1_gate_fck: gpt1_gate_fck { + gpt1_gate_fck: gpt1_gate_fck@c00 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -976,7 +976,7 @@ reg = <0x0c00>; }; - gpt1_mux_fck: gpt1_mux_fck { + gpt1_mux_fck: gpt1_mux_fck@c40 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -989,7 +989,7 @@ clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>; }; - aes2_ick: aes2_ick { + aes2_ick: aes2_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -1005,7 +1005,7 @@ clock-div = <1>; }; - gpio1_dbck: gpio1_dbck { + gpio1_dbck: gpio1_dbck@c00 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&wkup_32k_fck>; @@ -1013,7 +1013,7 @@ ti,bit-shift = <3>; }; - sha12_ick: sha12_ick { + sha12_ick: sha12_ick@a10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&core_l4_ick>; @@ -1021,7 +1021,7 @@ ti,bit-shift = <27>; }; - wdt2_fck: wdt2_fck { + wdt2_fck: wdt2_fck@c00 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&wkup_32k_fck>; @@ -1029,7 +1029,7 @@ ti,bit-shift = <5>; }; - wdt2_ick: wdt2_ick { + wdt2_ick: wdt2_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; @@ -1037,7 +1037,7 @@ ti,bit-shift = <5>; }; - wdt1_ick: wdt1_ick { + wdt1_ick: wdt1_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; @@ -1045,7 +1045,7 @@ ti,bit-shift = <4>; }; - gpio1_ick: gpio1_ick { + gpio1_ick: gpio1_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; @@ -1053,7 +1053,7 @@ ti,bit-shift = <3>; }; - omap_32ksync_ick: omap_32ksync_ick { + omap_32ksync_ick: omap_32ksync_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; @@ -1061,7 +1061,7 @@ ti,bit-shift = <2>; }; - gpt12_ick: gpt12_ick { + gpt12_ick: gpt12_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; @@ -1069,7 +1069,7 @@ ti,bit-shift = <1>; }; - gpt1_ick: gpt1_ick { + gpt1_ick: gpt1_ick@c10 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&wkup_l4_ick>; @@ -1093,7 +1093,7 @@ clock-div = <1>; }; - uart3_fck: uart3_fck { + uart3_fck: uart3_fck@1000 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&per_48m_fck>; @@ -1101,7 +1101,7 @@ ti,bit-shift = <11>; }; - gpt2_gate_fck: gpt2_gate_fck { + gpt2_gate_fck: gpt2_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -1109,7 +1109,7 @@ reg = <0x1000>; }; - gpt2_mux_fck: gpt2_mux_fck { + gpt2_mux_fck: gpt2_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -1122,7 +1122,7 @@ clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>; }; - gpt3_gate_fck: gpt3_gate_fck { + gpt3_gate_fck: gpt3_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -1130,7 +1130,7 @@ reg = <0x1000>; }; - gpt3_mux_fck: gpt3_mux_fck { + gpt3_mux_fck: gpt3_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -1144,7 +1144,7 @@ clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>; }; - gpt4_gate_fck: gpt4_gate_fck { + gpt4_gate_fck: gpt4_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -1152,7 +1152,7 @@ reg = <0x1000>; }; - gpt4_mux_fck: gpt4_mux_fck { + gpt4_mux_fck: gpt4_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -1166,7 +1166,7 @@ clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>; }; - gpt5_gate_fck: gpt5_gate_fck { + gpt5_gate_fck: gpt5_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -1174,7 +1174,7 @@ reg = <0x1000>; }; - gpt5_mux_fck: gpt5_mux_fck { + gpt5_mux_fck: gpt5_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -1188,7 +1188,7 @@ clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>; }; - gpt6_gate_fck: gpt6_gate_fck { + gpt6_gate_fck: gpt6_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -1196,7 +1196,7 @@ reg = <0x1000>; }; - gpt6_mux_fck: gpt6_mux_fck { + gpt6_mux_fck: gpt6_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -1210,7 +1210,7 @@ clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>; }; - gpt7_gate_fck: gpt7_gate_fck { + gpt7_gate_fck: gpt7_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -1218,7 +1218,7 @@ reg = <0x1000>; }; - gpt7_mux_fck: gpt7_mux_fck { + gpt7_mux_fck: gpt7_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -1232,7 +1232,7 @@ clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>; }; - gpt8_gate_fck: gpt8_gate_fck { + gpt8_gate_fck: gpt8_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -1240,7 +1240,7 @@ reg = <0x1000>; }; - gpt8_mux_fck: gpt8_mux_fck { + gpt8_mux_fck: gpt8_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -1254,7 +1254,7 @@ clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>; }; - gpt9_gate_fck: gpt9_gate_fck { + gpt9_gate_fck: gpt9_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&sys_ck>; @@ -1262,7 +1262,7 @@ reg = <0x1000>; }; - gpt9_mux_fck: gpt9_mux_fck { + gpt9_mux_fck: gpt9_mux_fck@1040 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&omap_32k_fck>, <&sys_ck>; @@ -1284,7 +1284,7 @@ clock-div = <1>; }; - gpio6_dbck: gpio6_dbck { + gpio6_dbck: gpio6_dbck@1000 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_32k_alwon_fck>; @@ -1292,7 +1292,7 @@ ti,bit-shift = <17>; }; - gpio5_dbck: gpio5_dbck { + gpio5_dbck: gpio5_dbck@1000 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_32k_alwon_fck>; @@ -1300,7 +1300,7 @@ ti,bit-shift = <16>; }; - gpio4_dbck: gpio4_dbck { + gpio4_dbck: gpio4_dbck@1000 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_32k_alwon_fck>; @@ -1308,7 +1308,7 @@ ti,bit-shift = <15>; }; - gpio3_dbck: gpio3_dbck { + gpio3_dbck: gpio3_dbck@1000 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_32k_alwon_fck>; @@ -1316,7 +1316,7 @@ ti,bit-shift = <14>; }; - gpio2_dbck: gpio2_dbck { + gpio2_dbck: gpio2_dbck@1000 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_32k_alwon_fck>; @@ -1324,7 +1324,7 @@ ti,bit-shift = <13>; }; - wdt3_fck: wdt3_fck { + wdt3_fck: wdt3_fck@1000 { #clock-cells = <0>; compatible = "ti,wait-gate-clock"; clocks = <&per_32k_alwon_fck>; @@ -1340,7 +1340,7 @@ clock-div = <1>; }; - gpio6_ick: gpio6_ick { + gpio6_ick: gpio6_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1348,7 +1348,7 @@ ti,bit-shift = <17>; }; - gpio5_ick: gpio5_ick { + gpio5_ick: gpio5_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1356,7 +1356,7 @@ ti,bit-shift = <16>; }; - gpio4_ick: gpio4_ick { + gpio4_ick: gpio4_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1364,7 +1364,7 @@ ti,bit-shift = <15>; }; - gpio3_ick: gpio3_ick { + gpio3_ick: gpio3_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1372,7 +1372,7 @@ ti,bit-shift = <14>; }; - gpio2_ick: gpio2_ick { + gpio2_ick: gpio2_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1380,7 +1380,7 @@ ti,bit-shift = <13>; }; - wdt3_ick: wdt3_ick { + wdt3_ick: wdt3_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1388,7 +1388,7 @@ ti,bit-shift = <12>; }; - uart3_ick: uart3_ick { + uart3_ick: uart3_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1396,7 +1396,7 @@ ti,bit-shift = <11>; }; - uart4_ick: uart4_ick { + uart4_ick: uart4_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1404,7 +1404,7 @@ ti,bit-shift = <18>; }; - gpt9_ick: gpt9_ick { + gpt9_ick: gpt9_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1412,7 +1412,7 @@ ti,bit-shift = <10>; }; - gpt8_ick: gpt8_ick { + gpt8_ick: gpt8_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1420,7 +1420,7 @@ ti,bit-shift = <9>; }; - gpt7_ick: gpt7_ick { + gpt7_ick: gpt7_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1428,7 +1428,7 @@ ti,bit-shift = <8>; }; - gpt6_ick: gpt6_ick { + gpt6_ick: gpt6_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1436,7 +1436,7 @@ ti,bit-shift = <7>; }; - gpt5_ick: gpt5_ick { + gpt5_ick: gpt5_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1444,7 +1444,7 @@ ti,bit-shift = <6>; }; - gpt4_ick: gpt4_ick { + gpt4_ick: gpt4_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1452,7 +1452,7 @@ ti,bit-shift = <5>; }; - gpt3_ick: gpt3_ick { + gpt3_ick: gpt3_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1460,7 +1460,7 @@ ti,bit-shift = <4>; }; - gpt2_ick: gpt2_ick { + gpt2_ick: gpt2_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1468,7 +1468,7 @@ ti,bit-shift = <3>; }; - mcbsp2_ick: mcbsp2_ick { + mcbsp2_ick: mcbsp2_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1476,7 +1476,7 @@ ti,bit-shift = <0>; }; - mcbsp3_ick: mcbsp3_ick { + mcbsp3_ick: mcbsp3_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1484,7 +1484,7 @@ ti,bit-shift = <1>; }; - mcbsp4_ick: mcbsp4_ick { + mcbsp4_ick: mcbsp4_ick@1010 { #clock-cells = <0>; compatible = "ti,omap3-interface-clock"; clocks = <&per_l4_ick>; @@ -1492,7 +1492,7 @@ ti,bit-shift = <2>; }; - mcbsp2_gate_fck: mcbsp2_gate_fck { + mcbsp2_gate_fck: mcbsp2_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; @@ -1500,7 +1500,7 @@ reg = <0x1000>; }; - mcbsp3_gate_fck: mcbsp3_gate_fck { + mcbsp3_gate_fck: mcbsp3_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; @@ -1508,7 +1508,7 @@ reg = <0x1000>; }; - mcbsp4_gate_fck: mcbsp4_gate_fck { + mcbsp4_gate_fck: mcbsp4_gate_fck@1000 { #clock-cells = <0>; compatible = "ti,composite-gate-clock"; clocks = <&mcbsp_clks>; @@ -1516,7 +1516,7 @@ reg = <0x1000>; }; - emu_src_mux_ck: emu_src_mux_ck { + emu_src_mux_ck: emu_src_mux_ck@1140 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; @@ -1529,7 +1529,7 @@ clocks = <&emu_src_mux_ck>; }; - pclk_fck: pclk_fck { + pclk_fck: pclk_fck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&emu_src_ck>; @@ -1539,7 +1539,7 @@ ti,index-starts-at-one; }; - pclkx2_fck: pclkx2_fck { + pclkx2_fck: pclkx2_fck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&emu_src_ck>; @@ -1549,7 +1549,7 @@ ti,index-starts-at-one; }; - atclk_fck: atclk_fck { + atclk_fck: atclk_fck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&emu_src_ck>; @@ -1559,7 +1559,7 @@ ti,index-starts-at-one; }; - traceclk_src_fck: traceclk_src_fck { + traceclk_src_fck: traceclk_src_fck@1140 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>; @@ -1567,7 +1567,7 @@ reg = <0x1140>; }; - traceclk_fck: traceclk_fck { + traceclk_fck: traceclk_fck@1140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&traceclk_src_fck>; diff --git a/arch/arm/boot/dts/omap4-kc1.dts b/arch/arm/boot/dts/omap4-kc1.dts new file mode 100644 index 000000000000..2251bd54e4e6 --- /dev/null +++ b/arch/arm/boot/dts/omap4-kc1.dts @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap443x.dtsi" + +/ { + model = "Amazon Kindle Fire (first generation)"; + compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + pwmleds { + compatible = "pwm-leds"; + + green { + label = "green"; + pwms = <&twl_pwm 0 7812500>; + max-brightness = <127>; + }; + + orange { + label = "orange"; + pwms = <&twl_pwm 1 7812500>; + max-brightness = <127>; + }; + }; +}; + +&omap4_pmx_core { + pinctrl-names = "default"; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx */ + OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ + OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + i2c4_pins: pinmux_i2c4_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */ + OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x040, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat0 */ + OMAP4_IOPAD(0x042, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat1 */ + OMAP4_IOPAD(0x044, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat2 */ + OMAP4_IOPAD(0x046, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat3 */ + OMAP4_IOPAD(0x048, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat4 */ + OMAP4_IOPAD(0x04a, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat5 */ + OMAP4_IOPAD(0x04c, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat6 */ + OMAP4_IOPAD(0x04e, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_dat7 */ + OMAP4_IOPAD(0x082, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_clk */ + OMAP4_IOPAD(0x084, PIN_INPUT_PULLUP | MUX_MODE1) /* sdmmc2_cmd */ + >; + }; + + usb_otg_hs_pins: pinmux_usb_otg_hs_pins { + pinctrl-single,pins = < + OMAP4_IOPAD(0x194, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usba0_otg_ce */ + OMAP4_IOPAD(0x196, PIN_INPUT | MUX_MODE0) /* usba0_otg_dp */ + OMAP4_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* usba0_otg_dm */ + >; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core OMAP4_UART3_RX>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + + clock-frequency = <400000>; + + twl: twl@48 { + reg = <0x48>; + /* IRQ# = 7 */ + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */ + + twl_power: power { + compatible = "ti,twl6030-power"; + ti,system-power-controller; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <400000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <400000>; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + + clock-frequency = <400000>; +}; + +&mmc1 { + status = "disabled"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + + vmmc-supply = <&vaux1>; + ti,non-removable; + bus-width = <8>; +}; + +&mmc3 { + status = "disabled"; +}; + +&mmc4 { + status = "disabled"; +}; + +&usb_otg_hs { + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_hs_pins>; + + interface-type = <1>; + mode = <3>; + power = <50>; +}; + +#include "twl6030.dtsi" +#include "twl6030_omap4.dtsi" + +&twl_usb_comparator { + usb-supply = <&vusb>; +}; diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi index 49d032b846be..a17997f4e9aa 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -17,7 +17,7 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; - sound: sound@0 { + sound: sound { compatible = "ti,abe-twl6040"; ti,model = "VAR-SOM-OM44"; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 421fe9f8a9eb..3fdc51cd0fad 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -198,7 +198,7 @@ #size-cells = <1>; ranges = <0 0x5a0 0x170>; - pbias_regulator: pbias_regulator { + pbias_regulator: pbias_regulator@60 { compatible = "ti,pbias-omap4", "ti,pbias-omap"; reg = <0x60 0x4>; syscon = <&omap4_padconf_global>; @@ -370,6 +370,10 @@ ti,no-idle-on-init; clocks = <&l3_div_ck>; clock-names = "fck"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; uart1: serial@4806a000 { diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi index 2bd2166f88d3..f370d96a87e5 100644 --- a/arch/arm/boot/dts/omap443x-clocks.dtsi +++ b/arch/arm/boot/dts/omap443x-clocks.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &prm_clocks { - bandgap_fclk: bandgap_fclk { + bandgap_fclk: bandgap_fclk@1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi index 0adfa1d1ef20..fc6a8610c24c 100644 --- a/arch/arm/boot/dts/omap443x.dtsi +++ b/arch/arm/boot/dts/omap443x.dtsi @@ -35,7 +35,7 @@ }; ocp { - bandgap: bandgap { + bandgap: bandgap@4a002260 { reg = <0x4a002260 0x4 0x4a00232C 0x4>; compatible = "ti,omap4430-bandgap"; diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi index 5fa68f191af7..ef66e12e0a67 100644 --- a/arch/arm/boot/dts/omap4460.dtsi +++ b/arch/arm/boot/dts/omap4460.dtsi @@ -40,7 +40,7 @@ }; ocp { - bandgap: bandgap { + bandgap: bandgap@4a002260 { reg = <0x4a002260 0x4 0x4a00232C 0x4 0x4a002378 0x18>; diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi index be033e9803e9..fb5929b742d4 100644 --- a/arch/arm/boot/dts/omap446x-clocks.dtsi +++ b/arch/arm/boot/dts/omap446x-clocks.dtsi @@ -8,7 +8,7 @@ * published by the Free Software Foundation. */ &prm_clocks { - div_ts_ck: div_ts_ck { + div_ts_ck: div_ts_ck@1888 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&l4_wkup_clk_mux_ck>; @@ -17,7 +17,7 @@ ti,dividers = <8>, <16>, <32>; }; - bandgap_ts_fclk: bandgap_ts_fclk { + bandgap_ts_fclk: bandgap_ts_fclk@1888 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&div_ts_ck>; diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index f2c48f09824e..9573b37fbaa7 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -20,7 +20,7 @@ clock-frequency = <12000000>; }; - pad_clks_ck: pad_clks_ck { + pad_clks_ck: pad_clks_ck@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&pad_clks_src_ck>; @@ -46,7 +46,7 @@ clock-frequency = <12000000>; }; - slimbus_clk: slimbus_clk { + slimbus_clk: slimbus_clk@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&slimbus_src_clk>; @@ -132,21 +132,21 @@ clock-frequency = <60000000>; }; - dpll_abe_ck: dpll_abe_ck { + dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>; reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>; }; - dpll_abe_x2_ck: dpll_abe_x2_ck { + dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_abe_ck>; reg = <0x01f0>; }; - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; @@ -165,7 +165,7 @@ clock-div = <8>; }; - abe_clk: abe_clk { + abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; @@ -174,7 +174,7 @@ ti,index-power-of-two; }; - aess_fclk: aess_fclk { + aess_fclk: aess_fclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&abe_clk>; @@ -183,7 +183,7 @@ reg = <0x0528>; }; - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; @@ -194,7 +194,7 @@ ti,invert-autoidle-bit; }; - core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck { + core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>; @@ -202,7 +202,7 @@ reg = <0x012c>; }; - dpll_core_ck: dpll_core_ck { + dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>; @@ -215,7 +215,7 @@ clocks = <&dpll_core_ck>; }; - dpll_core_m6x2_ck: dpll_core_m6x2_ck { + dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -226,7 +226,7 @@ ti,invert-autoidle-bit; }; - dpll_core_m2_ck: dpll_core_m2_ck { + dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_ck>; @@ -245,7 +245,7 @@ clock-div = <2>; }; - dpll_core_m5x2_ck: dpll_core_m5x2_ck { + dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -256,7 +256,7 @@ ti,invert-autoidle-bit; }; - div_core_ck: div_core_ck { + div_core_ck: div_core_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5x2_ck>; @@ -264,7 +264,7 @@ ti,max-div = <2>; }; - div_iva_hs_clk: div_iva_hs_clk { + div_iva_hs_clk: div_iva_hs_clk@1dc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5x2_ck>; @@ -273,7 +273,7 @@ ti,index-power-of-two; }; - div_mpu_hs_clk: div_mpu_hs_clk { + div_mpu_hs_clk: div_mpu_hs_clk@19c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_m5x2_ck>; @@ -282,7 +282,7 @@ ti,index-power-of-two; }; - dpll_core_m4x2_ck: dpll_core_m4x2_ck { + dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -301,7 +301,7 @@ clock-div = <2>; }; - dpll_abe_m2_ck: dpll_abe_m2_ck { + dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_ck>; @@ -310,7 +310,7 @@ ti,index-starts-at-one; }; - dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck { + dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_x2_ck>; @@ -318,7 +318,7 @@ reg = <0x0134>; }; - dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck { + dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -333,7 +333,7 @@ clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>; }; - dpll_core_m7x2_ck: dpll_core_m7x2_ck { + dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -344,7 +344,7 @@ ti,invert-autoidle-bit; }; - iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck { + iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>; @@ -352,7 +352,7 @@ reg = <0x01ac>; }; - dpll_iva_ck: dpll_iva_ck { + dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>; @@ -365,7 +365,7 @@ clocks = <&dpll_iva_ck>; }; - dpll_iva_m4x2_ck: dpll_iva_m4x2_ck { + dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>; @@ -376,7 +376,7 @@ ti,invert-autoidle-bit; }; - dpll_iva_m5x2_ck: dpll_iva_m5x2_ck { + dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>; @@ -387,14 +387,14 @@ ti,invert-autoidle-bit; }; - dpll_mpu_ck: dpll_mpu_ck { + dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck { + dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; @@ -421,7 +421,7 @@ clock-div = <3>; }; - l3_div_ck: l3_div_ck { + l3_div_ck: l3_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&div_core_ck>; @@ -430,7 +430,7 @@ reg = <0x0100>; }; - l4_div_ck: l4_div_ck { + l4_div_ck: l4_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&l3_div_ck>; @@ -455,7 +455,7 @@ clock-div = <2>; }; - ocp_abe_iclk: ocp_abe_iclk { + ocp_abe_iclk: ocp_abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&aess_fclk>; @@ -472,7 +472,7 @@ clock-div = <4>; }; - dmic_sync_mux_ck: dmic_sync_mux_ck { + dmic_sync_mux_ck: dmic_sync_mux_ck@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; @@ -480,7 +480,7 @@ reg = <0x0538>; }; - func_dmic_abe_gfclk: func_dmic_abe_gfclk { + func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; @@ -488,7 +488,7 @@ reg = <0x0538>; }; - mcasp_sync_mux_ck: mcasp_sync_mux_ck { + mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; @@ -496,7 +496,7 @@ reg = <0x0540>; }; - func_mcasp_abe_gfclk: func_mcasp_abe_gfclk { + func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; @@ -504,7 +504,7 @@ reg = <0x0540>; }; - mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { + mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; @@ -512,7 +512,7 @@ reg = <0x0548>; }; - func_mcbsp1_gfclk: func_mcbsp1_gfclk { + func_mcbsp1_gfclk: func_mcbsp1_gfclk@548 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; @@ -520,7 +520,7 @@ reg = <0x0548>; }; - mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { + mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; @@ -528,7 +528,7 @@ reg = <0x0550>; }; - func_mcbsp2_gfclk: func_mcbsp2_gfclk { + func_mcbsp2_gfclk: func_mcbsp2_gfclk@550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; @@ -536,7 +536,7 @@ reg = <0x0550>; }; - mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { + mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>; @@ -544,7 +544,7 @@ reg = <0x0558>; }; - func_mcbsp3_gfclk: func_mcbsp3_gfclk { + func_mcbsp3_gfclk: func_mcbsp3_gfclk@558 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; @@ -552,7 +552,7 @@ reg = <0x0558>; }; - slimbus1_fclk_1: slimbus1_fclk_1 { + slimbus1_fclk_1: slimbus1_fclk_1@560 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_24m_clk>; @@ -560,7 +560,7 @@ reg = <0x0560>; }; - slimbus1_fclk_0: slimbus1_fclk_0 { + slimbus1_fclk_0: slimbus1_fclk_0@560 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&abe_24m_fclk>; @@ -568,7 +568,7 @@ reg = <0x0560>; }; - slimbus1_fclk_2: slimbus1_fclk_2 { + slimbus1_fclk_2: slimbus1_fclk_2@560 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&pad_clks_ck>; @@ -576,7 +576,7 @@ reg = <0x0560>; }; - slimbus1_slimbus_clk: slimbus1_slimbus_clk { + slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&slimbus_clk>; @@ -584,7 +584,7 @@ reg = <0x0560>; }; - timer5_sync_mux: timer5_sync_mux { + timer5_sync_mux: timer5_sync_mux@568 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; @@ -592,7 +592,7 @@ reg = <0x0568>; }; - timer6_sync_mux: timer6_sync_mux { + timer6_sync_mux: timer6_sync_mux@570 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; @@ -600,7 +600,7 @@ reg = <0x0570>; }; - timer7_sync_mux: timer7_sync_mux { + timer7_sync_mux: timer7_sync_mux@578 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; @@ -608,7 +608,7 @@ reg = <0x0578>; }; - timer8_sync_mux: timer8_sync_mux { + timer8_sync_mux: timer8_sync_mux@580 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&syc_clk_div_ck>, <&sys_32k_ck>; @@ -623,7 +623,7 @@ }; }; &prm_clocks { - sys_clkin_ck: sys_clkin_ck { + sys_clkin_ck: sys_clkin_ck@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; @@ -631,7 +631,7 @@ ti,index-starts-at-one; }; - abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck { + abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -639,7 +639,7 @@ reg = <0x0108>; }; - abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck { + abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -654,14 +654,14 @@ clock-div = <1>; }; - l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck { + l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>; reg = <0x0108>; }; - syc_clk_div_ck: syc_clk_div_ck { + syc_clk_div_ck: syc_clk_div_ck@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&sys_clkin_ck>; @@ -669,7 +669,7 @@ ti,max-div = <2>; }; - gpio1_dbclk: gpio1_dbclk { + gpio1_dbclk: gpio1_dbclk@1838 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -677,7 +677,7 @@ reg = <0x1838>; }; - dmt1_clk_mux: dmt1_clk_mux { + dmt1_clk_mux: dmt1_clk_mux@1840 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -685,7 +685,7 @@ reg = <0x1840>; }; - usim_ck: usim_ck { + usim_ck: usim_ck@1858 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m4x2_ck>; @@ -694,7 +694,7 @@ ti,dividers = <14>, <18>; }; - usim_fclk: usim_fclk { + usim_fclk: usim_fclk@1858 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&usim_ck>; @@ -702,7 +702,7 @@ reg = <0x1858>; }; - pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck { + pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@1a20 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; @@ -710,7 +710,7 @@ reg = <0x1a20>; }; - pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck { + pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@1a20 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>; @@ -718,7 +718,7 @@ reg = <0x1a20>; }; - stm_clk_div_ck: stm_clk_div_ck { + stm_clk_div_ck: stm_clk_div_ck@1a20 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&pmd_stm_clock_mux_ck>; @@ -728,7 +728,7 @@ ti,index-power-of-two; }; - trace_clk_div_div_ck: trace_clk_div_div_ck { + trace_clk_div_div_ck: trace_clk_div_div_ck@1a20 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&pmd_trace_clk_mux_ck>; @@ -752,7 +752,7 @@ }; &cm2_clocks { - per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck { + per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>; @@ -760,14 +760,14 @@ reg = <0x014c>; }; - dpll_per_ck: dpll_per_ck { + dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>; reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>; }; - dpll_per_m2_ck: dpll_per_m2_ck { + dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; @@ -776,14 +776,14 @@ ti,index-starts-at-one; }; - dpll_per_x2_ck: dpll_per_x2_ck { + dpll_per_x2_ck: dpll_per_x2_ck@150 { #clock-cells = <0>; compatible = "ti,omap4-dpll-x2-clock"; clocks = <&dpll_per_ck>; reg = <0x0150>; }; - dpll_per_m2x2_ck: dpll_per_m2x2_ck { + dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -794,7 +794,7 @@ ti,invert-autoidle-bit; }; - dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck { + dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_per_x2_ck>; @@ -802,7 +802,7 @@ reg = <0x0154>; }; - dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck { + dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 { #clock-cells = <0>; compatible = "ti,composite-divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -817,7 +817,7 @@ clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>; }; - dpll_per_m4x2_ck: dpll_per_m4x2_ck { + dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -828,7 +828,7 @@ ti,invert-autoidle-bit; }; - dpll_per_m5x2_ck: dpll_per_m5x2_ck { + dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -839,7 +839,7 @@ ti,invert-autoidle-bit; }; - dpll_per_m6x2_ck: dpll_per_m6x2_ck { + dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -850,7 +850,7 @@ ti,invert-autoidle-bit; }; - dpll_per_m7x2_ck: dpll_per_m7x2_ck { + dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -861,14 +861,14 @@ ti,invert-autoidle-bit; }; - dpll_usb_ck: dpll_usb_ck { + dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>; reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>; }; - dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck { + dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 { #clock-cells = <0>; compatible = "ti,fixed-factor-clock"; clocks = <&dpll_usb_ck>; @@ -879,7 +879,7 @@ ti,invert-autoidle-bit; }; - dpll_usb_m2_ck: dpll_usb_m2_ck { + dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_ck>; @@ -890,7 +890,7 @@ ti,invert-autoidle-bit; }; - ducati_clk_mux_ck: ducati_clk_mux_ck { + ducati_clk_mux_ck: ducati_clk_mux_ck@100 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>; @@ -921,7 +921,7 @@ clock-div = <8>; }; - func_48m_fclk: func_48m_fclk { + func_48m_fclk: func_48m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m2x2_ck>; @@ -937,7 +937,7 @@ clock-div = <4>; }; - func_64m_fclk: func_64m_fclk { + func_64m_fclk: func_64m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m4x2_ck>; @@ -945,7 +945,7 @@ ti,dividers = <2>, <4>; }; - func_96m_fclk: func_96m_fclk { + func_96m_fclk: func_96m_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m2x2_ck>; @@ -953,7 +953,7 @@ ti,dividers = <2>, <4>; }; - init_60m_fclk: init_60m_fclk { + init_60m_fclk: init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>; @@ -961,7 +961,7 @@ ti,dividers = <1>, <8>; }; - per_abe_nc_fclk: per_abe_nc_fclk { + per_abe_nc_fclk: per_abe_nc_fclk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2_ck>; @@ -969,7 +969,7 @@ ti,max-div = <2>; }; - aes1_fck: aes1_fck { + aes1_fck: aes1_fck@15a0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3_div_ck>; @@ -977,7 +977,7 @@ reg = <0x15a0>; }; - aes2_fck: aes2_fck { + aes2_fck: aes2_fck@15a8 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3_div_ck>; @@ -985,7 +985,7 @@ reg = <0x15a8>; }; - dss_sys_clk: dss_sys_clk { + dss_sys_clk: dss_sys_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&syc_clk_div_ck>; @@ -993,7 +993,7 @@ reg = <0x1120>; }; - dss_tv_clk: dss_tv_clk { + dss_tv_clk: dss_tv_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&extalt_clkin_ck>; @@ -1001,7 +1001,7 @@ reg = <0x1120>; }; - dss_dss_clk: dss_dss_clk { + dss_dss_clk: dss_dss_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_m5x2_ck>; @@ -1010,7 +1010,7 @@ ti,set-rate-parent; }; - dss_48mhz_clk: dss_48mhz_clk { + dss_48mhz_clk: dss_48mhz_clk@1120 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_48mc_fclk>; @@ -1018,7 +1018,7 @@ reg = <0x1120>; }; - fdif_fck: fdif_fck { + fdif_fck: fdif_fck@1028 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m4x2_ck>; @@ -1028,7 +1028,7 @@ ti,index-power-of-two; }; - gpio2_dbclk: gpio2_dbclk { + gpio2_dbclk: gpio2_dbclk@1460 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1036,7 +1036,7 @@ reg = <0x1460>; }; - gpio3_dbclk: gpio3_dbclk { + gpio3_dbclk: gpio3_dbclk@1468 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1044,7 +1044,7 @@ reg = <0x1468>; }; - gpio4_dbclk: gpio4_dbclk { + gpio4_dbclk: gpio4_dbclk@1470 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1052,7 +1052,7 @@ reg = <0x1470>; }; - gpio5_dbclk: gpio5_dbclk { + gpio5_dbclk: gpio5_dbclk@1478 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1060,7 +1060,7 @@ reg = <0x1478>; }; - gpio6_dbclk: gpio6_dbclk { + gpio6_dbclk: gpio6_dbclk@1480 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1068,7 +1068,7 @@ reg = <0x1480>; }; - sgx_clk_mux: sgx_clk_mux { + sgx_clk_mux: sgx_clk_mux@1220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>; @@ -1076,7 +1076,7 @@ reg = <0x1220>; }; - hsi_fck: hsi_fck { + hsi_fck: hsi_fck@1338 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m2x2_ck>; @@ -1086,7 +1086,7 @@ ti,index-power-of-two; }; - iss_ctrlclk: iss_ctrlclk { + iss_ctrlclk: iss_ctrlclk@1020 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_96m_fclk>; @@ -1094,7 +1094,7 @@ reg = <0x1020>; }; - mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck { + mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>; @@ -1102,7 +1102,7 @@ reg = <0x14e0>; }; - per_mcbsp4_gfclk: per_mcbsp4_gfclk { + per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>; @@ -1110,7 +1110,7 @@ reg = <0x14e0>; }; - hsmmc1_fclk: hsmmc1_fclk { + hsmmc1_fclk: hsmmc1_fclk@1328 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_64m_fclk>, <&func_96m_fclk>; @@ -1118,7 +1118,7 @@ reg = <0x1328>; }; - hsmmc2_fclk: hsmmc2_fclk { + hsmmc2_fclk: hsmmc2_fclk@1330 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_64m_fclk>, <&func_96m_fclk>; @@ -1126,7 +1126,7 @@ reg = <0x1330>; }; - ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m { + ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_48m_fclk>; @@ -1134,7 +1134,7 @@ reg = <0x13e0>; }; - sha2md5_fck: sha2md5_fck { + sha2md5_fck: sha2md5_fck@15c8 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3_div_ck>; @@ -1142,7 +1142,7 @@ reg = <0x15c8>; }; - slimbus2_fclk_1: slimbus2_fclk_1 { + slimbus2_fclk_1: slimbus2_fclk_1@1538 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&per_abe_24m_fclk>; @@ -1150,7 +1150,7 @@ reg = <0x1538>; }; - slimbus2_fclk_0: slimbus2_fclk_0 { + slimbus2_fclk_0: slimbus2_fclk_0@1538 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_24mc_fclk>; @@ -1158,7 +1158,7 @@ reg = <0x1538>; }; - slimbus2_slimbus_clk: slimbus2_slimbus_clk { + slimbus2_slimbus_clk: slimbus2_slimbus_clk@1538 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&pad_slimbus_core_clks_ck>; @@ -1166,7 +1166,7 @@ reg = <0x1538>; }; - smartreflex_core_fck: smartreflex_core_fck { + smartreflex_core_fck: smartreflex_core_fck@638 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_wkup_clk_mux_ck>; @@ -1174,7 +1174,7 @@ reg = <0x0638>; }; - smartreflex_iva_fck: smartreflex_iva_fck { + smartreflex_iva_fck: smartreflex_iva_fck@630 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_wkup_clk_mux_ck>; @@ -1182,7 +1182,7 @@ reg = <0x0630>; }; - smartreflex_mpu_fck: smartreflex_mpu_fck { + smartreflex_mpu_fck: smartreflex_mpu_fck@628 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_wkup_clk_mux_ck>; @@ -1190,7 +1190,7 @@ reg = <0x0628>; }; - cm2_dm10_mux: cm2_dm10_mux { + cm2_dm10_mux: cm2_dm10_mux@1428 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -1198,7 +1198,7 @@ reg = <0x1428>; }; - cm2_dm11_mux: cm2_dm11_mux { + cm2_dm11_mux: cm2_dm11_mux@1430 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -1206,7 +1206,7 @@ reg = <0x1430>; }; - cm2_dm2_mux: cm2_dm2_mux { + cm2_dm2_mux: cm2_dm2_mux@1438 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -1214,7 +1214,7 @@ reg = <0x1438>; }; - cm2_dm3_mux: cm2_dm3_mux { + cm2_dm3_mux: cm2_dm3_mux@1440 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -1222,7 +1222,7 @@ reg = <0x1440>; }; - cm2_dm4_mux: cm2_dm4_mux { + cm2_dm4_mux: cm2_dm4_mux@1448 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -1230,7 +1230,7 @@ reg = <0x1448>; }; - cm2_dm9_mux: cm2_dm9_mux { + cm2_dm9_mux: cm2_dm9_mux@1450 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin_ck>, <&sys_32k_ck>; @@ -1238,7 +1238,7 @@ reg = <0x1450>; }; - usb_host_fs_fck: usb_host_fs_fck { + usb_host_fs_fck: usb_host_fs_fck@13d0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_48mc_fclk>; @@ -1246,7 +1246,7 @@ reg = <0x13d0>; }; - utmi_p1_gfclk: utmi_p1_gfclk { + utmi_p1_gfclk: utmi_p1_gfclk@1358 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>; @@ -1254,7 +1254,7 @@ reg = <0x1358>; }; - usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { + usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1358 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&utmi_p1_gfclk>; @@ -1262,7 +1262,7 @@ reg = <0x1358>; }; - utmi_p2_gfclk: utmi_p2_gfclk { + utmi_p2_gfclk: utmi_p2_gfclk@1358 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>; @@ -1270,7 +1270,7 @@ reg = <0x1358>; }; - usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { + usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1358 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&utmi_p2_gfclk>; @@ -1278,7 +1278,7 @@ reg = <0x1358>; }; - usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { + usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1358 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&init_60m_fclk>; @@ -1286,7 +1286,7 @@ reg = <0x1358>; }; - usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { + usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1358 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_m2_ck>; @@ -1294,7 +1294,7 @@ reg = <0x1358>; }; - usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { + usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1358 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&init_60m_fclk>; @@ -1302,7 +1302,7 @@ reg = <0x1358>; }; - usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { + usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1358 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&init_60m_fclk>; @@ -1310,7 +1310,7 @@ reg = <0x1358>; }; - usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { + usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1358 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_m2_ck>; @@ -1318,7 +1318,7 @@ reg = <0x1358>; }; - usb_host_hs_func48mclk: usb_host_hs_func48mclk { + usb_host_hs_func48mclk: usb_host_hs_func48mclk@1358 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_48mc_fclk>; @@ -1326,7 +1326,7 @@ reg = <0x1358>; }; - usb_host_hs_fck: usb_host_hs_fck { + usb_host_hs_fck: usb_host_hs_fck@1358 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&init_60m_fclk>; @@ -1334,7 +1334,7 @@ reg = <0x1358>; }; - otg_60m_gfclk: otg_60m_gfclk { + otg_60m_gfclk: otg_60m_gfclk@1360 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>; @@ -1342,7 +1342,7 @@ reg = <0x1360>; }; - usb_otg_hs_xclk: usb_otg_hs_xclk { + usb_otg_hs_xclk: usb_otg_hs_xclk@1360 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&otg_60m_gfclk>; @@ -1350,7 +1350,7 @@ reg = <0x1360>; }; - usb_otg_hs_ick: usb_otg_hs_ick { + usb_otg_hs_ick: usb_otg_hs_ick@1360 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3_div_ck>; @@ -1358,7 +1358,7 @@ reg = <0x1360>; }; - usb_phy_cm_clk32k: usb_phy_cm_clk32k { + usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1366,7 +1366,7 @@ reg = <0x0640>; }; - usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { + usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&init_60m_fclk>; @@ -1374,7 +1374,7 @@ reg = <0x1368>; }; - usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { + usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1368 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&init_60m_fclk>; @@ -1382,7 +1382,7 @@ reg = <0x1368>; }; - usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { + usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1368 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&init_60m_fclk>; @@ -1390,7 +1390,7 @@ reg = <0x1368>; }; - usb_tll_hs_ick: usb_tll_hs_ick { + usb_tll_hs_ick: usb_tll_hs_ick@1368 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l4_div_ck>; @@ -1407,7 +1407,7 @@ }; &scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck { + auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1415,7 +1415,7 @@ reg = <0x0310>; }; - auxclk0_src_mux_ck: auxclk0_src_mux_ck { + auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1429,7 +1429,7 @@ clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; - auxclk0_ck: auxclk0_ck { + auxclk0_ck: auxclk0_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk0_src_ck>; @@ -1438,7 +1438,7 @@ reg = <0x0310>; }; - auxclk1_src_gate_ck: auxclk1_src_gate_ck { + auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1446,7 +1446,7 @@ reg = <0x0314>; }; - auxclk1_src_mux_ck: auxclk1_src_mux_ck { + auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1460,7 +1460,7 @@ clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; - auxclk1_ck: auxclk1_ck { + auxclk1_ck: auxclk1_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk1_src_ck>; @@ -1469,7 +1469,7 @@ reg = <0x0314>; }; - auxclk2_src_gate_ck: auxclk2_src_gate_ck { + auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1477,7 +1477,7 @@ reg = <0x0318>; }; - auxclk2_src_mux_ck: auxclk2_src_mux_ck { + auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1491,7 +1491,7 @@ clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; - auxclk2_ck: auxclk2_ck { + auxclk2_ck: auxclk2_ck@318 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk2_src_ck>; @@ -1500,7 +1500,7 @@ reg = <0x0318>; }; - auxclk3_src_gate_ck: auxclk3_src_gate_ck { + auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1508,7 +1508,7 @@ reg = <0x031c>; }; - auxclk3_src_mux_ck: auxclk3_src_mux_ck { + auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1522,7 +1522,7 @@ clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; - auxclk3_ck: auxclk3_ck { + auxclk3_ck: auxclk3_ck@31c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk3_src_ck>; @@ -1531,7 +1531,7 @@ reg = <0x031c>; }; - auxclk4_src_gate_ck: auxclk4_src_gate_ck { + auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1539,7 +1539,7 @@ reg = <0x0320>; }; - auxclk4_src_mux_ck: auxclk4_src_mux_ck { + auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1553,7 +1553,7 @@ clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; - auxclk4_ck: auxclk4_ck { + auxclk4_ck: auxclk4_ck@320 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk4_src_ck>; @@ -1562,7 +1562,7 @@ reg = <0x0320>; }; - auxclk5_src_gate_ck: auxclk5_src_gate_ck { + auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1570,7 +1570,7 @@ reg = <0x0324>; }; - auxclk5_src_mux_ck: auxclk5_src_mux_ck { + auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1584,7 +1584,7 @@ clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>; }; - auxclk5_ck: auxclk5_ck { + auxclk5_ck: auxclk5_ck@324 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk5_src_ck>; @@ -1593,7 +1593,7 @@ reg = <0x0324>; }; - auxclkreq0_ck: auxclkreq0_ck { + auxclkreq0_ck: auxclkreq0_ck@210 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; @@ -1601,7 +1601,7 @@ reg = <0x0210>; }; - auxclkreq1_ck: auxclkreq1_ck { + auxclkreq1_ck: auxclkreq1_ck@214 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; @@ -1609,7 +1609,7 @@ reg = <0x0214>; }; - auxclkreq2_ck: auxclkreq2_ck { + auxclkreq2_ck: auxclkreq2_ck@218 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; @@ -1617,7 +1617,7 @@ reg = <0x0218>; }; - auxclkreq3_ck: auxclkreq3_ck { + auxclkreq3_ck: auxclkreq3_ck@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; @@ -1625,7 +1625,7 @@ reg = <0x021c>; }; - auxclkreq4_ck: auxclkreq4_ck { + auxclkreq4_ck: auxclkreq4_ck@220 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; @@ -1633,7 +1633,7 @@ reg = <0x0220>; }; - auxclkreq5_ck: auxclkreq5_ck { + auxclkreq5_ck: auxclkreq5_ck@224 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>; diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 914bf4c47404..dc759a3028b7 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -391,11 +391,21 @@ ti,backup-battery-charge-high-current; }; + gpadc { + compatible = "ti,palmas-gpadc"; + interrupts = <18 0 + 16 0 + 17 0>; + #io-channel-cells = <1>; + ti,channel0-current-microamp = <5>; + ti,channel3-current-microamp = <10>; + }; + palmas_pmic { compatible = "ti,palmas-pmic"; interrupt-parent = <&palmas>; interrupts = <14 IRQ_TYPE_NONE>; - interrupt-name = "short-irq"; + interrupt-names = "short-irq"; ti,ldo6-vibrator; diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index 4d87d9c6c86d..93fdfa96776e 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -434,7 +434,7 @@ compatible = "ti,palmas-pmic"; interrupt-parent = <&palmas>; interrupts = <14 IRQ_TYPE_NONE>; - interrupt-name = "short-irq"; + interrupt-names = "short-irq"; ti,ldo6-vibrator; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 120b6b80cd39..84c10195e79b 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -187,7 +187,7 @@ #size-cells = <1>; ranges = <0 0x5a0 0xec>; - pbias_regulator: pbias_regulator { + pbias_regulator: pbias_regulator@60 { compatible = "ti,pbias-omap5", "ti,pbias-omap"; reg = <0x60 0x4>; syscon = <&omap5_padconf_global>; @@ -398,6 +398,10 @@ ti,hwmods = "gpmc"; clocks = <&l3_iclk_div>; clock-names = "fck"; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; }; i2c1: i2c@48070000 { diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi index 83b425fb3ac2..4899c2359d0a 100644 --- a/arch/arm/boot/dts/omap54xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi @@ -14,7 +14,7 @@ clock-frequency = <12000000>; }; - pad_clks_ck: pad_clks_ck { + pad_clks_ck: pad_clks_ck@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&pad_clks_src_ck>; @@ -34,7 +34,7 @@ clock-frequency = <12000000>; }; - slimbus_clk: slimbus_clk { + slimbus_clk: slimbus_clk@108 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&slimbus_src_clk>; @@ -102,7 +102,7 @@ clock-frequency = <60000000>; }; - dpll_abe_ck: dpll_abe_ck { + dpll_abe_ck: dpll_abe_ck@1e0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-m4xen-clock"; clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>; @@ -115,7 +115,7 @@ clocks = <&dpll_abe_ck>; }; - dpll_abe_m2x2_ck: dpll_abe_m2x2_ck { + dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; @@ -132,7 +132,7 @@ clock-div = <8>; }; - abe_clk: abe_clk { + abe_clk: abe_clk@108 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_m2x2_ck>; @@ -141,7 +141,7 @@ ti,index-power-of-two; }; - abe_iclk: abe_iclk { + abe_iclk: abe_iclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&aess_fclk>; @@ -158,7 +158,7 @@ clock-div = <16>; }; - dpll_abe_m3x2_ck: dpll_abe_m3x2_ck { + dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_abe_x2_ck>; @@ -167,7 +167,7 @@ ti,index-starts-at-one; }; - dpll_core_byp_mux: dpll_core_byp_mux { + dpll_core_byp_mux: dpll_core_byp_mux@12c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>; @@ -175,7 +175,7 @@ reg = <0x012c>; }; - dpll_core_ck: dpll_core_ck { + dpll_core_ck: dpll_core_ck@120 { #clock-cells = <0>; compatible = "ti,omap4-dpll-core-clock"; clocks = <&sys_clkin>, <&dpll_core_byp_mux>; @@ -188,7 +188,7 @@ clocks = <&dpll_core_ck>; }; - dpll_core_h21x2_ck: dpll_core_h21x2_ck { + dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -213,7 +213,7 @@ clock-div = <2>; }; - dpll_core_h11x2_ck: dpll_core_h11x2_ck { + dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -222,7 +222,7 @@ ti,index-starts-at-one; }; - dpll_core_h12x2_ck: dpll_core_h12x2_ck { + dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -231,7 +231,7 @@ ti,index-starts-at-one; }; - dpll_core_h13x2_ck: dpll_core_h13x2_ck { + dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -240,7 +240,7 @@ ti,index-starts-at-one; }; - dpll_core_h14x2_ck: dpll_core_h14x2_ck { + dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -249,7 +249,7 @@ ti,index-starts-at-one; }; - dpll_core_h22x2_ck: dpll_core_h22x2_ck { + dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -258,7 +258,7 @@ ti,index-starts-at-one; }; - dpll_core_h23x2_ck: dpll_core_h23x2_ck { + dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -267,7 +267,7 @@ ti,index-starts-at-one; }; - dpll_core_h24x2_ck: dpll_core_h24x2_ck { + dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -276,7 +276,7 @@ ti,index-starts-at-one; }; - dpll_core_m2_ck: dpll_core_m2_ck { + dpll_core_m2_ck: dpll_core_m2_ck@130 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_ck>; @@ -285,7 +285,7 @@ ti,index-starts-at-one; }; - dpll_core_m3x2_ck: dpll_core_m3x2_ck { + dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_core_x2_ck>; @@ -302,7 +302,7 @@ clock-div = <1>; }; - dpll_iva_byp_mux: dpll_iva_byp_mux { + dpll_iva_byp_mux: dpll_iva_byp_mux@1ac { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>; @@ -310,7 +310,7 @@ reg = <0x01ac>; }; - dpll_iva_ck: dpll_iva_ck { + dpll_iva_ck: dpll_iva_ck@1a0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_iva_byp_mux>; @@ -323,7 +323,7 @@ clocks = <&dpll_iva_ck>; }; - dpll_iva_h11x2_ck: dpll_iva_h11x2_ck { + dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>; @@ -332,7 +332,7 @@ ti,index-starts-at-one; }; - dpll_iva_h12x2_ck: dpll_iva_h12x2_ck { + dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_iva_x2_ck>; @@ -349,14 +349,14 @@ clock-div = <1>; }; - dpll_mpu_ck: dpll_mpu_ck { + dpll_mpu_ck: dpll_mpu_ck@160 { #clock-cells = <0>; compatible = "ti,omap5-mpu-dpll-clock"; clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; }; - dpll_mpu_m2_ck: dpll_mpu_m2_ck { + dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_mpu_ck>; @@ -381,7 +381,7 @@ clock-div = <3>; }; - l3_iclk_div: l3_iclk_div { + l3_iclk_div: l3_iclk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; ti,max-div = <2>; @@ -399,7 +399,7 @@ clock-div = <1>; }; - l4_root_clk_div: l4_root_clk_div { + l4_root_clk_div: l4_root_clk_div@100 { #clock-cells = <0>; compatible = "ti,divider-clock"; ti,max-div = <2>; @@ -409,7 +409,7 @@ ti,index-power-of-two; }; - slimbus1_slimbus_clk: slimbus1_slimbus_clk { + slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&slimbus_clk>; @@ -417,7 +417,7 @@ reg = <0x0560>; }; - aess_fclk: aess_fclk { + aess_fclk: aess_fclk@528 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&abe_clk>; @@ -426,7 +426,7 @@ reg = <0x0528>; }; - dmic_sync_mux_ck: dmic_sync_mux_ck { + dmic_sync_mux_ck: dmic_sync_mux_ck@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; @@ -434,7 +434,7 @@ reg = <0x0538>; }; - dmic_gfclk: dmic_gfclk { + dmic_gfclk: dmic_gfclk@538 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; @@ -442,7 +442,7 @@ reg = <0x0538>; }; - mcasp_sync_mux_ck: mcasp_sync_mux_ck { + mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; @@ -450,7 +450,7 @@ reg = <0x0540>; }; - mcasp_gfclk: mcasp_gfclk { + mcasp_gfclk: mcasp_gfclk@540 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; @@ -458,7 +458,7 @@ reg = <0x0540>; }; - mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck { + mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; @@ -466,7 +466,7 @@ reg = <0x0548>; }; - mcbsp1_gfclk: mcbsp1_gfclk { + mcbsp1_gfclk: mcbsp1_gfclk@548 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; @@ -474,7 +474,7 @@ reg = <0x0548>; }; - mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck { + mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; @@ -482,7 +482,7 @@ reg = <0x0550>; }; - mcbsp2_gfclk: mcbsp2_gfclk { + mcbsp2_gfclk: mcbsp2_gfclk@550 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; @@ -490,7 +490,7 @@ reg = <0x0550>; }; - mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck { + mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>; @@ -498,7 +498,7 @@ reg = <0x0558>; }; - mcbsp3_gfclk: mcbsp3_gfclk { + mcbsp3_gfclk: mcbsp3_gfclk@558 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>; @@ -506,7 +506,7 @@ reg = <0x0558>; }; - timer5_gfclk_mux: timer5_gfclk_mux { + timer5_gfclk_mux: timer5_gfclk_mux@568 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; @@ -514,7 +514,7 @@ reg = <0x0568>; }; - timer6_gfclk_mux: timer6_gfclk_mux { + timer6_gfclk_mux: timer6_gfclk_mux@570 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; @@ -522,7 +522,7 @@ reg = <0x0570>; }; - timer7_gfclk_mux: timer7_gfclk_mux { + timer7_gfclk_mux: timer7_gfclk_mux@578 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; @@ -530,7 +530,7 @@ reg = <0x0578>; }; - timer8_gfclk_mux: timer8_gfclk_mux { + timer8_gfclk_mux: timer8_gfclk_mux@580 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>; @@ -545,7 +545,7 @@ }; }; &prm_clocks { - sys_clkin: sys_clkin { + sys_clkin: sys_clkin@110 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>; @@ -553,14 +553,14 @@ ti,index-starts-at-one; }; - abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux { + abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; reg = <0x0108>; }; - abe_dpll_clk_mux: abe_dpll_clk_mux { + abe_dpll_clk_mux: abe_dpll_clk_mux@10c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; @@ -583,7 +583,7 @@ clock-div = <1>; }; - wkupaon_iclk_mux: wkupaon_iclk_mux { + wkupaon_iclk_mux: wkupaon_iclk_mux@108 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&abe_lp_clk_div>; @@ -598,7 +598,7 @@ clock-div = <1>; }; - gpio1_dbclk: gpio1_dbclk { + gpio1_dbclk: gpio1_dbclk@1938 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -606,7 +606,7 @@ reg = <0x1938>; }; - timer1_gfclk_mux: timer1_gfclk_mux { + timer1_gfclk_mux: timer1_gfclk_mux@1940 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; @@ -616,7 +616,7 @@ }; &cm_core_clocks { - dpll_per_byp_mux: dpll_per_byp_mux { + dpll_per_byp_mux: dpll_per_byp_mux@14c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>; @@ -624,7 +624,7 @@ reg = <0x014c>; }; - dpll_per_ck: dpll_per_ck { + dpll_per_ck: dpll_per_ck@140 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&dpll_per_byp_mux>; @@ -637,7 +637,7 @@ clocks = <&dpll_per_ck>; }; - dpll_per_h11x2_ck: dpll_per_h11x2_ck { + dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -646,7 +646,7 @@ ti,index-starts-at-one; }; - dpll_per_h12x2_ck: dpll_per_h12x2_ck { + dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -655,7 +655,7 @@ ti,index-starts-at-one; }; - dpll_per_h14x2_ck: dpll_per_h14x2_ck { + dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -664,7 +664,7 @@ ti,index-starts-at-one; }; - dpll_per_m2_ck: dpll_per_m2_ck { + dpll_per_m2_ck: dpll_per_m2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_ck>; @@ -673,7 +673,7 @@ ti,index-starts-at-one; }; - dpll_per_m2x2_ck: dpll_per_m2x2_ck { + dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -682,7 +682,7 @@ ti,index-starts-at-one; }; - dpll_per_m3x2_ck: dpll_per_m3x2_ck { + dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_x2_ck>; @@ -691,7 +691,7 @@ ti,index-starts-at-one; }; - dpll_unipro1_ck: dpll_unipro1_ck { + dpll_unipro1_ck: dpll_unipro1_ck@200 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&sys_clkin>; @@ -706,7 +706,7 @@ clock-div = <1>; }; - dpll_unipro1_m2_ck: dpll_unipro1_m2_ck { + dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_unipro1_ck>; @@ -715,7 +715,7 @@ ti,index-starts-at-one; }; - dpll_unipro2_ck: dpll_unipro2_ck { + dpll_unipro2_ck: dpll_unipro2_ck@1c0 { #clock-cells = <0>; compatible = "ti,omap4-dpll-clock"; clocks = <&sys_clkin>, <&sys_clkin>; @@ -730,7 +730,7 @@ clock-div = <1>; }; - dpll_unipro2_m2_ck: dpll_unipro2_m2_ck { + dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_unipro2_ck>; @@ -739,7 +739,7 @@ ti,index-starts-at-one; }; - dpll_usb_byp_mux: dpll_usb_byp_mux { + dpll_usb_byp_mux: dpll_usb_byp_mux@18c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>; @@ -747,7 +747,7 @@ reg = <0x018c>; }; - dpll_usb_ck: dpll_usb_ck { + dpll_usb_ck: dpll_usb_ck@180 { #clock-cells = <0>; compatible = "ti,omap4-dpll-j-type-clock"; clocks = <&sys_clkin>, <&dpll_usb_byp_mux>; @@ -762,7 +762,7 @@ clock-div = <1>; }; - dpll_usb_m2_ck: dpll_usb_m2_ck { + dpll_usb_m2_ck: dpll_usb_m2_ck@190 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_ck>; @@ -811,7 +811,7 @@ clock-div = <2>; }; - l3init_60m_fclk: l3init_60m_fclk { + l3init_60m_fclk: l3init_60m_fclk@104 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_usb_m2_ck>; @@ -819,7 +819,7 @@ ti,dividers = <1>, <8>; }; - dss_32khz_clk: dss_32khz_clk { + dss_32khz_clk: dss_32khz_clk@1420 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -827,7 +827,7 @@ reg = <0x1420>; }; - dss_48mhz_clk: dss_48mhz_clk { + dss_48mhz_clk: dss_48mhz_clk@1420 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_48m_fclk>; @@ -835,7 +835,7 @@ reg = <0x1420>; }; - dss_dss_clk: dss_dss_clk { + dss_dss_clk: dss_dss_clk@1420 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_per_h12x2_ck>; @@ -844,7 +844,7 @@ ti,set-rate-parent; }; - dss_sys_clk: dss_sys_clk { + dss_sys_clk: dss_sys_clk@1420 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dss_syc_gfclk_div>; @@ -852,7 +852,7 @@ reg = <0x1420>; }; - gpio2_dbclk: gpio2_dbclk { + gpio2_dbclk: gpio2_dbclk@1060 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -860,7 +860,7 @@ reg = <0x1060>; }; - gpio3_dbclk: gpio3_dbclk { + gpio3_dbclk: gpio3_dbclk@1068 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -868,7 +868,7 @@ reg = <0x1068>; }; - gpio4_dbclk: gpio4_dbclk { + gpio4_dbclk: gpio4_dbclk@1070 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -876,7 +876,7 @@ reg = <0x1070>; }; - gpio5_dbclk: gpio5_dbclk { + gpio5_dbclk: gpio5_dbclk@1078 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -884,7 +884,7 @@ reg = <0x1078>; }; - gpio6_dbclk: gpio6_dbclk { + gpio6_dbclk: gpio6_dbclk@1080 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -892,7 +892,7 @@ reg = <0x1080>; }; - gpio7_dbclk: gpio7_dbclk { + gpio7_dbclk: gpio7_dbclk@1110 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -900,7 +900,7 @@ reg = <0x1110>; }; - gpio8_dbclk: gpio8_dbclk { + gpio8_dbclk: gpio8_dbclk@1118 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -908,7 +908,7 @@ reg = <0x1118>; }; - iss_ctrlclk: iss_ctrlclk { + iss_ctrlclk: iss_ctrlclk@1320 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&func_96m_fclk>; @@ -916,7 +916,7 @@ reg = <0x1320>; }; - lli_txphy_clk: lli_txphy_clk { + lli_txphy_clk: lli_txphy_clk@f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_unipro1_clkdcoldo>; @@ -924,7 +924,7 @@ reg = <0x0f20>; }; - lli_txphy_ls_clk: lli_txphy_ls_clk { + lli_txphy_ls_clk: lli_txphy_ls_clk@f20 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_unipro1_m2_ck>; @@ -932,7 +932,7 @@ reg = <0x0f20>; }; - mmc1_32khz_clk: mmc1_32khz_clk { + mmc1_32khz_clk: mmc1_32khz_clk@1628 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -940,7 +940,7 @@ reg = <0x1628>; }; - sata_ref_clk: sata_ref_clk { + sata_ref_clk: sata_ref_clk@1688 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_clkin>; @@ -948,7 +948,7 @@ reg = <0x1688>; }; - usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk { + usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_m2_ck>; @@ -956,7 +956,7 @@ reg = <0x1658>; }; - usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk { + usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_m2_ck>; @@ -964,7 +964,7 @@ reg = <0x1658>; }; - usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk { + usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_m2_ck>; @@ -972,7 +972,7 @@ reg = <0x1658>; }; - usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk { + usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>; @@ -980,7 +980,7 @@ reg = <0x1658>; }; - usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk { + usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>; @@ -988,7 +988,7 @@ reg = <0x1658>; }; - usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk { + usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>; @@ -996,7 +996,7 @@ reg = <0x1658>; }; - utmi_p1_gfclk: utmi_p1_gfclk { + utmi_p1_gfclk: utmi_p1_gfclk@1658 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>; @@ -1004,7 +1004,7 @@ reg = <0x1658>; }; - usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk { + usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&utmi_p1_gfclk>; @@ -1012,7 +1012,7 @@ reg = <0x1658>; }; - utmi_p2_gfclk: utmi_p2_gfclk { + utmi_p2_gfclk: utmi_p2_gfclk@1658 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>; @@ -1020,7 +1020,7 @@ reg = <0x1658>; }; - usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk { + usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&utmi_p2_gfclk>; @@ -1028,7 +1028,7 @@ reg = <0x1658>; }; - usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk { + usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1658 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>; @@ -1036,7 +1036,7 @@ reg = <0x1658>; }; - usb_otg_ss_refclk960m: usb_otg_ss_refclk960m { + usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@16f0 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&dpll_usb_clkdcoldo>; @@ -1044,7 +1044,7 @@ reg = <0x16f0>; }; - usb_phy_cm_clk32k: usb_phy_cm_clk32k { + usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; @@ -1052,7 +1052,7 @@ reg = <0x0640>; }; - usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk { + usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>; @@ -1060,7 +1060,7 @@ reg = <0x1668>; }; - usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk { + usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>; @@ -1068,7 +1068,7 @@ reg = <0x1668>; }; - usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk { + usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1668 { #clock-cells = <0>; compatible = "ti,gate-clock"; clocks = <&l3init_60m_fclk>; @@ -1076,7 +1076,7 @@ reg = <0x1668>; }; - fdif_fclk: fdif_fclk { + fdif_fclk: fdif_fclk@1328 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_h11x2_ck>; @@ -1085,7 +1085,7 @@ reg = <0x1328>; }; - gpu_core_gclk_mux: gpu_core_gclk_mux { + gpu_core_gclk_mux: gpu_core_gclk_mux@1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; @@ -1093,7 +1093,7 @@ reg = <0x1520>; }; - gpu_hyd_gclk_mux: gpu_hyd_gclk_mux { + gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>; @@ -1101,7 +1101,7 @@ reg = <0x1520>; }; - hsi_fclk: hsi_fclk { + hsi_fclk: hsi_fclk@1638 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&dpll_per_m2x2_ck>; @@ -1110,7 +1110,7 @@ reg = <0x1638>; }; - mmc1_fclk_mux: mmc1_fclk_mux { + mmc1_fclk_mux: mmc1_fclk_mux@1628 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; @@ -1118,7 +1118,7 @@ reg = <0x1628>; }; - mmc1_fclk: mmc1_fclk { + mmc1_fclk: mmc1_fclk@1628 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc1_fclk_mux>; @@ -1127,7 +1127,7 @@ reg = <0x1628>; }; - mmc2_fclk_mux: mmc2_fclk_mux { + mmc2_fclk_mux: mmc2_fclk_mux@1630 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>; @@ -1135,7 +1135,7 @@ reg = <0x1630>; }; - mmc2_fclk: mmc2_fclk { + mmc2_fclk: mmc2_fclk@1630 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&mmc2_fclk_mux>; @@ -1144,7 +1144,7 @@ reg = <0x1630>; }; - timer10_gfclk_mux: timer10_gfclk_mux { + timer10_gfclk_mux: timer10_gfclk_mux@1028 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; @@ -1152,7 +1152,7 @@ reg = <0x1028>; }; - timer11_gfclk_mux: timer11_gfclk_mux { + timer11_gfclk_mux: timer11_gfclk_mux@1030 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; @@ -1160,7 +1160,7 @@ reg = <0x1030>; }; - timer2_gfclk_mux: timer2_gfclk_mux { + timer2_gfclk_mux: timer2_gfclk_mux@1038 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; @@ -1168,7 +1168,7 @@ reg = <0x1038>; }; - timer3_gfclk_mux: timer3_gfclk_mux { + timer3_gfclk_mux: timer3_gfclk_mux@1040 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; @@ -1176,7 +1176,7 @@ reg = <0x1040>; }; - timer4_gfclk_mux: timer4_gfclk_mux { + timer4_gfclk_mux: timer4_gfclk_mux@1048 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; @@ -1184,7 +1184,7 @@ reg = <0x1048>; }; - timer9_gfclk_mux: timer9_gfclk_mux { + timer9_gfclk_mux: timer9_gfclk_mux@1050 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin>, <&sys_32k_ck>; @@ -1201,7 +1201,7 @@ }; &scrm_clocks { - auxclk0_src_gate_ck: auxclk0_src_gate_ck { + auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1209,7 +1209,7 @@ reg = <0x0310>; }; - auxclk0_src_mux_ck: auxclk0_src_mux_ck { + auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1223,7 +1223,7 @@ clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>; }; - auxclk0_ck: auxclk0_ck { + auxclk0_ck: auxclk0_ck@310 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk0_src_ck>; @@ -1232,7 +1232,7 @@ reg = <0x0310>; }; - auxclk1_src_gate_ck: auxclk1_src_gate_ck { + auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1240,7 +1240,7 @@ reg = <0x0314>; }; - auxclk1_src_mux_ck: auxclk1_src_mux_ck { + auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1254,7 +1254,7 @@ clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>; }; - auxclk1_ck: auxclk1_ck { + auxclk1_ck: auxclk1_ck@314 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk1_src_ck>; @@ -1263,7 +1263,7 @@ reg = <0x0314>; }; - auxclk2_src_gate_ck: auxclk2_src_gate_ck { + auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1271,7 +1271,7 @@ reg = <0x0318>; }; - auxclk2_src_mux_ck: auxclk2_src_mux_ck { + auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1285,7 +1285,7 @@ clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>; }; - auxclk2_ck: auxclk2_ck { + auxclk2_ck: auxclk2_ck@318 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk2_src_ck>; @@ -1294,7 +1294,7 @@ reg = <0x0318>; }; - auxclk3_src_gate_ck: auxclk3_src_gate_ck { + auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1302,7 +1302,7 @@ reg = <0x031c>; }; - auxclk3_src_mux_ck: auxclk3_src_mux_ck { + auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1316,7 +1316,7 @@ clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>; }; - auxclk3_ck: auxclk3_ck { + auxclk3_ck: auxclk3_ck@31c { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk3_src_ck>; @@ -1325,7 +1325,7 @@ reg = <0x031c>; }; - auxclk4_src_gate_ck: auxclk4_src_gate_ck { + auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 { #clock-cells = <0>; compatible = "ti,composite-no-wait-gate-clock"; clocks = <&dpll_core_m3x2_ck>; @@ -1333,7 +1333,7 @@ reg = <0x0320>; }; - auxclk4_src_mux_ck: auxclk4_src_mux_ck { + auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>; @@ -1347,7 +1347,7 @@ clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>; }; - auxclk4_ck: auxclk4_ck { + auxclk4_ck: auxclk4_ck@320 { #clock-cells = <0>; compatible = "ti,divider-clock"; clocks = <&auxclk4_src_ck>; @@ -1356,7 +1356,7 @@ reg = <0x0320>; }; - auxclkreq0_ck: auxclkreq0_ck { + auxclkreq0_ck: auxclkreq0_ck@210 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; @@ -1364,7 +1364,7 @@ reg = <0x0210>; }; - auxclkreq1_ck: auxclkreq1_ck { + auxclkreq1_ck: auxclkreq1_ck@214 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; @@ -1372,7 +1372,7 @@ reg = <0x0214>; }; - auxclkreq2_ck: auxclkreq2_ck { + auxclkreq2_ck: auxclkreq2_ck@218 { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; @@ -1380,7 +1380,7 @@ reg = <0x0218>; }; - auxclkreq3_ck: auxclkreq3_ck { + auxclkreq3_ck: auxclkreq3_ck@21c { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>; diff --git a/arch/arm/boot/dts/orion5x-kuroboxpro.dts b/arch/arm/boot/dts/orion5x-kuroboxpro.dts new file mode 100644 index 000000000000..1a672b098d0b --- /dev/null +++ b/arch/arm/boot/dts/orion5x-kuroboxpro.dts @@ -0,0 +1,127 @@ +/* + * Device Tree file for Buffalo/Revogear Kurobox Pro + * + * Copyright (C) 2016 + * Roger Shimizu <rogershimizu@gmail.com> + * + * Based on the board file arch/arm/mach-orion5x/kurobox_pro-setup.c + * Copyright (C) Ronen Shitrit <rshitrit@marvell.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "orion5x-linkstation.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Buffalo/Revogear Kurobox Pro"; + compatible = "buffalo,kurobox-pro", "marvell,orion5x-88f5182", "marvell,orion5x"; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>, + <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>, + <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x40000>, + <MBUS_ID(0x01, 0x1e) 0 0xfc000000 0x1000000>; + }; + + memory { /* 128 MB */ + device_type = "memory"; + reg = <0x00000000 0x8000000>; + }; +}; + +&pinctrl { + pmx_power_hdd: pmx-power-hdd { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_power_usb: pmx-power-usb { + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; +}; + +&devbus_cs0 { + status = "okay"; + compatible = "marvell,orion-nand"; + reg = <MBUS_ID(0x01, 0x1e) 0 0x400>; + cle = <0>; + ale = <1>; + bank-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uImage@0 { /* 4 MB */ + reg = <0 0x400000>; + read-only; + }; + + rootfs@400000 { /* 64 MB */ + reg = <0x400000 0x4000000>; + read-only; + }; + + extra@4400000 { /* 188 MB */ + reg = <0x4400000 0xBC00000>; + read-only; + }; + }; +}; + +&hdd_power { + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; +}; + +&usb_power { + gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; +}; + +&sata { + nr-ports = <2>; +}; + +&ehci1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ox810se.dtsi b/arch/arm/boot/dts/ox810se.dtsi new file mode 100644 index 000000000000..ce13705c38d4 --- /dev/null +++ b/arch/arm/boot/dts/ox810se.dtsi @@ -0,0 +1,336 @@ +/* + * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC + * + * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> + * + * Licensed under GPLv2 or later + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "oxsemi,ox810se"; + + cpus { + #address-cells = <0>; + #size-cells = <0>; + + cpu { + device_type = "cpu"; + compatible = "arm,arm926ej-s"; + clocks = <&armclk>; + }; + }; + + memory { + /* Max 256MB @ 0x48000000 */ + reg = <0x48000000 0x10000000>; + }; + + clocks { + osc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + gmacclk: gmacclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + rpsclk: rpsclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clocks = <&osc>; + }; + + pll400: pll400 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <733333333>; + }; + + sysclk: sysclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clocks = <&pll400>; + }; + + armclk: armclk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clocks = <&pll400>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + interrupt-parent = <&intc>; + + apb-bridge@44000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x44000000 0x1000000>; + + pinctrl: pinctrl { + compatible = "oxsemi,ox810se-pinctrl"; + + /* Regmap for sys registers */ + oxsemi,sys-ctrl = <&sys>; + + pinctrl_uart0: uart0 { + uart0a { + pins = "gpio31"; + function = "fct3"; + }; + uart0b { + pins = "gpio32"; + function = "fct3"; + }; + }; + + pinctrl_uart0_modem: uart0_modem { + uart0c { + pins = "gpio27"; + function = "fct3"; + }; + uart0d { + pins = "gpio28"; + function = "fct3"; + }; + uart0e { + pins = "gpio29"; + function = "fct3"; + }; + uart0f { + pins = "gpio30"; + function = "fct3"; + }; + uart0g { + pins = "gpio33"; + function = "fct3"; + }; + uart0h { + pins = "gpio34"; + function = "fct3"; + }; + }; + + pinctrl_uart1: uart1 { + uart1a { + pins = "gpio20"; + function = "fct3"; + }; + uart1b { + pins = "gpio22"; + function = "fct3"; + }; + }; + + pinctrl_uart1_modem: uart1_modem { + uart1c { + pins = "gpio8"; + function = "fct3"; + }; + uart1d { + pins = "gpio9"; + function = "fct3"; + }; + uart1e { + pins = "gpio23"; + function = "fct3"; + }; + uart1f { + pins = "gpio24"; + function = "fct3"; + }; + uart1g { + pins = "gpio25"; + function = "fct3"; + }; + uart1h { + pins = "gpio26"; + function = "fct3"; + }; + }; + + pinctrl_uart2: uart2 { + uart2a { + pins = "gpio6"; + function = "fct3"; + }; + uart2b { + pins = "gpio7"; + function = "fct3"; + }; + }; + + pinctrl_uart2_modem: uart2_modem { + uart2c { + pins = "gpio0"; + function = "fct3"; + }; + uart2d { + pins = "gpio1"; + function = "fct3"; + }; + uart2e { + pins = "gpio2"; + function = "fct3"; + }; + uart2f { + pins = "gpio3"; + function = "fct3"; + }; + uart2g { + pins = "gpio4"; + function = "fct3"; + }; + uart2h { + pins = "gpio5"; + function = "fct3"; + }; + }; + }; + + gpio0: gpio@000000 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x000000 0x100000>; + interrupts = <21>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <32>; + oxsemi,gpio-bank = <0>; + gpio-ranges = <&pinctrl 0 0 32>; + }; + + gpio1: gpio@100000 { + compatible = "oxsemi,ox810se-gpio"; + reg = <0x100000 0x100000>; + interrupts = <22>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + ngpios = <3>; + oxsemi,gpio-bank = <1>; + gpio-ranges = <&pinctrl 0 32 3>; + }; + + uart0: serial@200000 { + compatible = "ns16550a"; + reg = <0x200000 0x100000>; + clocks = <&sysclk>; + interrupts = <23>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 17>; + }; + + uart1: serial@300000 { + compatible = "ns16550a"; + reg = <0x300000 0x100000>; + clocks = <&sysclk>; + interrupts = <24>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 18>; + }; + + uart2: serial@900000 { + compatible = "ns16550a"; + reg = <0x900000 0x100000>; + clocks = <&sysclk>; + interrupts = <29>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 22>; + }; + + uart3: serial@a00000 { + compatible = "ns16550a"; + reg = <0xa00000 0x100000>; + clocks = <&sysclk>; + interrupts = <30>; + reg-shift = <0>; + fifo-size = <16>; + reg-io-width = <1>; + current-speed = <115200>; + no-loopback-test; + status = "disabled"; + resets = <&reset 23>; + }; + }; + + apb-bridge@45000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x45000000 0x1000000>; + + sys: sys-ctrl@000000 { + compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; + reg = <0x000000 0x100000>; + + reset: reset-controller { + compatible = "oxsemi,ox810se-reset"; + #reset-cells = <1>; + }; + + stdclk: stdclk { + compatible = "oxsemi,ox810se-stdclk"; + #clock-cells = <1>; + }; + }; + + rps@300000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0 0x300000 0x100000>; + + intc: interrupt-controller@0 { + compatible = "oxsemi,ox810se-rps-irq"; + interrupt-controller; + reg = <0 0x200>; + #interrupt-cells = <1>; + valid-mask = <0xFFFFFFFF>; + clear-mask = <0>; + }; + + timer0: timer@200 { + compatible = "oxsemi,ox810se-rps-timer"; + reg = <0x200 0x40>; + clocks = <&rpsclk>; + interrupts = <4 5>; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts deleted file mode 100644 index a00d7ce7802b..000000000000 --- a/arch/arm/boot/dts/phy3250.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * PHYTEC phyCORE-LPC3250 board - * - * Copyright 2012 Roland Stigge <stigge@antcom.de> - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ - -/dts-v1/; -#include "lpc32xx.dtsi" - -/ { - model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; - compatible = "phytec,phy3250", "nxp,lpc3250"; - #address-cells = <1>; - #size-cells = <1>; - - memory { - device_type = "memory"; - reg = <0x80000000 0x4000000>; - }; - - regulators { - backlight_reg: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "backlight_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 4 0>; - enable-active-high; - regulator-boot-on; - }; - - lcd_reg: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "lcd_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 0 0>; - enable-active-high; - regulator-boot-on; - }; - - sd_reg: regulator@2 { - compatible = "regulator-fixed"; - regulator-name = "sd_reg"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - gpio = <&gpio 5 5 0>; - enable-active-high; - }; - }; - - ahb { - mac: ethernet@31060000 { - phy-mode = "rmii"; - use-iram; - }; - - clcd@31040000 { - status = "okay"; - }; - - /* 64MB Flash via SLC NAND controller */ - slc: flash@20020000 { - status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - - nxp,wdr-clks = <14>; - nxp,wwidth = <40000000>; - nxp,whold = <100000000>; - nxp,wsetup = <100000000>; - nxp,rdr-clks = <14>; - nxp,rwidth = <40000000>; - nxp,rhold = <66666666>; - nxp,rsetup = <100000000>; - nand-on-flash-bbt; - gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ - - mtd0@00000000 { - label = "phy3250-boot"; - reg = <0x00000000 0x00064000>; - read-only; - }; - - mtd1@00064000 { - label = "phy3250-uboot"; - reg = <0x00064000 0x00190000>; - read-only; - }; - - mtd2@001f4000 { - label = "phy3250-ubt-prms"; - reg = <0x001f4000 0x00010000>; - }; - - mtd3@00204000 { - label = "phy3250-kernel"; - reg = <0x00204000 0x00400000>; - }; - - mtd4@00604000 { - label = "phy3250-rootfs"; - reg = <0x00604000 0x039fc000>; - }; - }; - - apb { - uart5: serial@40090000 { - status = "okay"; - }; - - uart3: serial@40080000 { - status = "okay"; - }; - - i2c1: i2c@400A0000 { - clock-frequency = <100000>; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; - - uda1380: uda1380@18 { - compatible = "nxp,uda1380"; - reg = <0x18>; - power-gpio = <&gpio 0x59 0>; - reset-gpio = <&gpio 0x51 0>; - dac-clk = "wspll"; - }; - }; - - i2c2: i2c@400A8000 { - clock-frequency = <100000>; - }; - - ssp0: ssp@20084000 { - #address-cells = <1>; - #size-cells = <0>; - num-cs = <1>; - cs-gpios = <&gpio 3 5 0>; - - eeprom: at25@0 { - pl022,interface = <0>; - pl022,com-mode = <0>; - pl022,rx-level-trig = <1>; - pl022,tx-level-trig = <1>; - pl022,ctrl-len = <11>; - pl022,wait-state = <0>; - pl022,duplex = <0>; - - at25,byte-len = <0x8000>; - at25,addr-mode = <2>; - at25,page-size = <64>; - - compatible = "atmel,at25"; - reg = <0>; - spi-max-frequency = <5000000>; - }; - }; - - sd@20098000 { - wp-gpios = <&gpio 3 0 0>; - cd-gpios = <&gpio 3 1 0>; - cd-inverted; - bus-width = <4>; - vmmc-supply = <&sd_reg>; - status = "okay"; - }; - }; - - fab { - uart2: serial@40018000 { - status = "okay"; - }; - - tsc@40048000 { - status = "okay"; - }; - - key@40050000 { - status = "okay"; - keypad,num-rows = <1>; - keypad,num-columns = <1>; - nxp,debounce-delay-ms = <3>; - nxp,scan-delay-ms = <34>; - linux,keymap = <0x00000002>; - }; - }; - }; - - leds { - compatible = "gpio-leds"; - - led0 { /* red */ - gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ - default-state = "off"; - }; - - led1 { /* green */ - gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ - linux,default-trigger = "heartbeat"; - }; - }; -}; - -/* Here, choose exactly one from: ohci, usbd */ -&ohci /* &usbd */ { - transceiver = <&isp1301>; - status = "okay"; -}; - -&i2cusb { - clock-frequency = <100000>; - - isp1301: usb-transceiver@2c { - compatible = "nxp,isp1301"; - reg = <0x2c>; - }; -}; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi new file mode 100644 index 000000000000..a3efb9704fcd --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi @@ -0,0 +1,52 @@ +&tlmm_pinmux { + card_detect: card-detect { + mux { + pins = "gpio26"; + function = "gpio"; + bias-disable; + }; + }; + + pcie_pins: pcie-pinmux { + mux { + pins = "gpio27"; + function = "gpio"; + }; + conf { + pins = "gpio27"; + drive-strength = <12>; + bias-disable; + }; + }; + + user_leds: user-leds { + mux { + pins = "gpio3", "gpio7", "gpio10", "gpio11"; + function = "gpio"; + }; + + conf { + pins = "gpio3", "gpio7", "gpio10", "gpio11"; + function = "gpio"; + output-low; + }; + }; + + magneto_pins: magneto-pins { + mux { + pins = "gpio31", "gpio48"; + function = "gpio"; + bias-disable; + }; + }; +}; + +&pm8921_mpps { + mpp_leds: mpp-leds { + pinconf { + pins = "mpp7", "mpp8"; + function = "digital"; + output-low; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts new file mode 100644 index 000000000000..e01b27ea7fba --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts @@ -0,0 +1,349 @@ +#include "qcom-apq8064-v2.0.dtsi" +#include "qcom-apq8064-arrow-db600c-pins.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Arrow Electronics, APQ8064 DB600c"; + compatible = "arrow,db600c", "qcom,apq8064"; + + aliases { + serial0 = &gsbi7_serial; + serial1 = &gsbi1_serial; + i2c0 = &gsbi2_i2c; + i2c1 = &gsbi3_i2c; + i2c2 = &gsbi4_i2c; + i2c3 = &gsbi7_i2c; + spi0 = &gsbi5_spi; + }; + + regulators { + compatible = "simple-bus"; + vph: regulator-fixed@1 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <4500000>; + regulator-max-microvolt = <4500000>; + regulator-name = "VPH"; + regulator-type = "voltage"; + regulator-boot-on; + }; + + /* on board fixed 3.3v supply */ + vcc3v3: vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + }; + + soc { + rpm@108000 { + regulators { + vdd_s1-supply = <&vph>; + vdd_s2-supply = <&vph>; + vdd_s3-supply = <&vph>; + vdd_s4-supply = <&vph>; + vdd_s5-supply = <&vph>; + vdd_s6-supply = <&vph>; + vdd_s7-supply = <&vph>; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + vdd_l3_l15_l17-supply = <&vph>; + vdd_l4_l14-supply = <&vph>; + vdd_l5_l8_l16-supply = <&vph>; + vdd_l6_l7-supply = <&vph>; + vdd_l9_l11-supply = <&vph>; + vdd_l10_l22-supply = <&vph>; + vdd_l21_l23_l29-supply = <&vph>; + vdd_l24-supply = <&pm8921_s1>; + vdd_l25-supply = <&pm8921_s1>; + vdd_l26-supply = <&pm8921_s7>; + vdd_l27-supply = <&pm8921_s7>; + vdd_l28-supply = <&pm8921_s7>; + vin_lvs1_3_6-supply = <&pm8921_s4>; + vin_lvs2-supply = <&pm8921_s1>; + vin_lvs4_5_7-supply = <&pm8921_s4>; + + s1 { + regulator-always-on; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + }; + + s3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + qcom,switch-mode-frequency = <4800000>; + }; + + s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,switch-mode-frequency = <3200000>; + bias-pull-down; + regulator-always-on; + }; + + s7 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + qcom,switch-mode-frequency = <3200000>; + }; + + l3 { + regulator-min-microvolt = <3050000>; + regulator-max-microvolt = <3300000>; + bias-pull-down; + }; + + l4 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1800000>; + bias-pull-down; + }; + + l5 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <3000000>; + bias-pull-down; + regulator-boot-on; + regulator-always-on; + }; + + l6 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + bias-pull-down; + }; + + l23 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + bias-pull-down; + }; + + lvs6 { + bias-pull-down; + }; + + lvs7 { + bias-pull-down; + }; + }; + }; + + gsbi@12440000 { + status = "okay"; + qcom,mode = <GSBI_PROT_UART_W_FC>; + serial@12450000 { + label = "LS-UART1"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gsbi1_uart_4pins>; + }; + }; + + gsbi@12480000 { + status = "okay"; + qcom,mode = <GSBI_PROT_I2C>; + i2c@124a0000 { + /* On Low speed expansion and Sensors */ + label = "LS-I2C0"; + status = "okay"; + lis3mdl_mag@1e { + compatible = "st,lis3mdl-magn"; + reg = <0x1e>; + vdd-supply = <&vcc3v3>; + vddio-supply = <&pm8921_s4>; + pinctrl-names = "default"; + pinctrl-0 = <&magneto_pins>; + interrupt-parent = <&tlmm_pinmux>; + + st,drdy-int-pin = <2>; + interrupts = <48 IRQ_TYPE_EDGE_RISING>, /* DRDY line */ + <31 IRQ_TYPE_EDGE_RISING>; /* INT */ + }; + }; + }; + + gsbi@16200000 { + status = "okay"; + qcom,mode = <GSBI_PROT_I2C>; + i2c@16280000 { + /* On Low speed expansion */ + status = "okay"; + label = "LS-I2C1"; + clock-frequency = <200000>; + eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <64>; + }; + }; + }; + + gsbi@16300000 { + status = "okay"; + qcom,mode = <GSBI_PROT_I2C>; + i2c@16380000 { + /* On High speed expansion */ + label = "HS-CAM-I2C3"; + status = "okay"; + }; + }; + + gsbi@1a200000 { + status = "okay"; + spi@1a280000 { + /* On Low speed expansion */ + label = "LS-SPI0"; + status = "okay"; + }; + }; + + /* DEBUG UART */ + gsbi@16600000 { + status = "okay"; + qcom,mode = <GSBI_PROT_I2C_UART>; + serial@16640000 { + label = "LS-UART0"; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&gsbi7_uart_2pins>; + }; + + i2c@16680000 { + /* On High speed expansion */ + status = "okay"; + label = "HS-CAM-I2C2"; + }; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&user_leds>, <&mpp_leds>; + + compatible = "gpio-leds"; + + user-led0 { + label = "user0-led"; + gpios = <&tlmm_pinmux 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user-led1 { + label = "user1-led"; + gpios = <&tlmm_pinmux 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + user-led2 { + label = "user2-led"; + gpios = <&tlmm_pinmux 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc1"; + default-state = "off"; + }; + + user-led3 { + label = "user3-led"; + gpios = <&tlmm_pinmux 11 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + wifi-led { + label = "WiFi-led"; + gpios = <&pm8921_mpps 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + bt-led { + label = "BT-led"; + gpios = <&pm8921_mpps 8 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pci@1b500000 { + status = "okay"; + vdda-supply = <&pm8921_s3>; + vdda_phy-supply = <&pm8921_lvs6>; + vdda_refclk-supply = <&vcc3v3>; + pinctrl-0 = <&pcie_pins>; + pinctrl-names = "default"; + perst-gpio = <&tlmm_pinmux 27 GPIO_ACTIVE_LOW>; + }; + + phy@1b400000 { + status = "okay"; + }; + + sata@29000000 { + status = "okay"; + target-supply = <&pm8921_lvs7>; + }; + + /* OTG */ + phy@12500000 { + status = "okay"; + dr_mode = "peripheral"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l4>; + }; + + phy@12520000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + phy@12530000 { + status = "okay"; + vddcx-supply = <&pm8921_s3>; + v3p3-supply = <&pm8921_l3>; + v1p8-supply = <&pm8921_l23>; + }; + + gadget@12500000 { + status = "okay"; + }; + + /* OTG */ + usb@12500000 { + status = "okay"; + }; + + usb@12520000 { + status = "okay"; + }; + + usb@12530000 { + status = "okay"; + }; + + amba { + /* eMMC */ + sdcc@12400000 { + status = "okay"; + vmmc-supply = <&pm8921_l5>; + vqmmc-supply = <&pm8921_s4>; + }; + + /* External micro SD card */ + sdcc@12180000 { + status = "okay"; + vmmc-supply = <&pm8921_l6>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index c535b3f0e5cf..32fedfa149d0 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -224,6 +224,12 @@ reg = <0x52>; pagesize = <32>; }; + + bq27541@55 { + compatible = "ti,bq27541"; + reg = <0x55>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi index b57c59d5bc00..4102a98f475b 100644 --- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi @@ -39,6 +39,20 @@ }; }; + gsbi1_uart_2pins: gsbi1_uart_2pins { + mux { + pins = "gpio18", "gpio19"; + function = "gsbi1"; + }; + }; + + gsbi1_uart_4pins: gsbi1_uart_4pins { + mux { + pins = "gpio18", "gpio19", "gpio20", "gpio21"; + function = "gsbi1"; + }; + }; + i2c2_pins: i2c2 { mux { pins = "gpio24", "gpio25"; @@ -205,4 +219,29 @@ function = "gsbi7"; }; }; + + i2c7_pins: i2c7 { + mux { + pins = "gpio84", "gpio85"; + function = "gsbi7"; + }; + + pinconf { + pins = "gpio84", "gpio85"; + drive-strength = <16>; + bias-disable; + }; + }; + + i2c7_pins_sleep: i2c7_pins_sleep { + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + pinconf { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable = <0>; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 04f541bffbdd..df96ccdc9bb4 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -124,6 +124,95 @@ hwlocks = <&sfpb_mutex 3>; }; + smd { + compatible = "qcom,smd"; + + modem@0 { + interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&l2cc 8 3>; + qcom,smd-edge = <0>; + + status = "disabled"; + }; + + q6@1 { + interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&l2cc 8 15>; + qcom,smd-edge = <1>; + + status = "disabled"; + }; + + dsps@3 { + interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&sps_sic_non_secure 0x4080 0>; + qcom,smd-edge = <3>; + + status = "disabled"; + }; + + riva@6 { + interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&l2cc 8 25>; + qcom,smd-edge = <6>; + + status = "disabled"; + }; + }; + + smsm { + compatible = "qcom,smsm"; + + #address-cells = <1>; + #size-cells = <0>; + + qcom,ipc-1 = <&l2cc 8 4>; + qcom,ipc-2 = <&l2cc 8 14>; + qcom,ipc-3 = <&l2cc 8 23>; + qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; + + apps_smsm: apps@0 { + reg = <0>; + #qcom,state-cells = <1>; + }; + + modem_smsm: modem@1 { + reg = <1>; + interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + q6_smsm: q6@2 { + reg = <2>; + interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + wcnss_smsm: wcnss@3 { + reg = <3>; + interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + dsps_smsm: dsps@4 { + reg = <4>; + interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -212,6 +301,11 @@ regulator; }; + sps_sic_non_secure: sps-sic-non-secure@12100000 { + compatible = "syscon"; + reg = <0x12100000 0x10000>; + }; + gsbi1: gsbi@12440000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; @@ -225,9 +319,20 @@ syscon-tcsr = <&tcsr>; + gsbi1_serial: serial@12450000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12450000 0x100>, + <0x12400000 0x03>; + interrupts = <0 193 0x0>; + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + gsbi1_i2c: i2c@12460000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c1_pins &i2c1_pins_sleep>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_pins_sleep>; pinctrl-names = "default", "sleep"; reg = <0x12460000 0x1000>; interrupts = <0 194 IRQ_TYPE_NONE>; @@ -255,7 +360,8 @@ gsbi2_i2c: i2c@124a0000 { compatible = "qcom,i2c-qup-v1.1.1"; reg = <0x124a0000 0x1000>; - pinctrl-0 = <&i2c2_pins &i2c2_pins_sleep>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_pins_sleep>; pinctrl-names = "default", "sleep"; interrupts = <0 196 IRQ_TYPE_NONE>; clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; @@ -277,7 +383,8 @@ ranges; gsbi3_i2c: i2c@16280000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c3_pins &i2c3_pins_sleep>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-1 = <&i2c3_pins_sleep>; pinctrl-names = "default", "sleep"; reg = <0x16280000 0x1000>; interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; @@ -302,7 +409,8 @@ gsbi4_i2c: i2c@16380000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c4_pins &i2c4_pins_sleep>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_pins_sleep>; pinctrl-names = "default", "sleep"; reg = <0x16380000 0x1000>; interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; @@ -337,7 +445,8 @@ compatible = "qcom,spi-qup-v1.1.1"; reg = <0x1a280000 0x1000>; interrupts = <0 155 0>; - pinctrl-0 = <&spi5_default &spi5_sleep>; + pinctrl-0 = <&spi5_default>; + pinctrl-1 = <&spi5_sleep>; pinctrl-names = "default", "sleep"; clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; clock-names = "core", "iface"; @@ -370,7 +479,8 @@ gsbi6_i2c: i2c@16580000 { compatible = "qcom,i2c-qup-v1.1.1"; - pinctrl-0 = <&i2c6_pins &i2c6_pins_sleep>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-1 = <&i2c6_pins_sleep>; pinctrl-names = "default", "sleep"; reg = <0x16580000 0x1000>; interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; @@ -401,6 +511,19 @@ clock-names = "core", "iface"; status = "disabled"; }; + + gsbi7_i2c: i2c@16680000 { + compatible = "qcom,i2c-qup-v1.1.1"; + pinctrl-0 = <&i2c7_pins>; + pinctrl-1 = <&i2c7_pins_sleep>; + pinctrl-names = "default", "sleep"; + reg = <0x16680000 0x1000>; + interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI7_QUP_CLK>, + <&gcc GSBI7_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; }; rng@1a500000 { diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts new file mode 100644 index 000000000000..0d92f1bc3a13 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dts @@ -0,0 +1,22 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "qcom-ipq4019-ap.dk01.1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ40xx/AP-DK01.1-C1"; + +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi new file mode 100644 index 000000000000..b9457dd21a69 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -0,0 +1,112 @@ +/* Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "qcom-ipq4019.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1"; + compatible = "qcom,ipq4019"; + + clocks { + xo: xo { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + }; + + soc { + + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 2 0xf08>, + <1 3 0xf08>, + <1 4 0xf08>, + <1 1 0xf08>; + clock-frequency = <48000000>; + }; + + pinctrl@0x01000000 { + serial_pins: serial_pinmux { + mux { + pins = "gpio60", "gpio61"; + function = "blsp_uart0"; + bias-disable; + }; + }; + + spi_0_pins: spi_0_pinmux { + pinmux { + function = "blsp_spi0"; + pins = "gpio55", "gpio56", "gpio57"; + }; + pinmux_cs { + function = "gpio"; + pins = "gpio54"; + }; + pinconf { + pins = "gpio55", "gpio56", "gpio57"; + drive-strength = <12>; + bias-disable; + }; + pinconf_cs { + pins = "gpio54"; + drive-strength = <2>; + bias-disable; + output-high; + }; + }; + }; + + blsp_dma: dma@7884000 { + status = "ok"; + }; + + spi_0: spi@78b5000 { + pinctrl-0 = <&spi_0_pins>; + pinctrl-names = "default"; + status = "ok"; + cs-gpios = <&tlmm 54 0>; + + mx25l25635e@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "mx25l25635e"; + spi-max-frequency = <24000000>; + }; + }; + + serial@78af000 { + pinctrl-0 = <&serial_pins>; + pinctrl-names = "default"; + status = "ok"; + }; + + cryptobam: dma@8e04000 { + status = "ok"; + }; + + crypto@8e3a000 { + status = "ok"; + }; + + watchdog@b017000 { + status = "ok"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi new file mode 100644 index 000000000000..5c08d19066c2 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2015, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "skeleton.dtsi" +#include <dt-bindings/clock/qcom,gcc-ipq4019.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "Qualcomm Technologies, Inc. IPQ4019"; + compatible = "qcom,ipq4019"; + interrupt-parent = <&intc>; + + aliases { + spi0 = &spi_0; + i2c0 = &i2c_0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + reg = <0x0>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; + operating-points = < + /* kHz uV (fixed) */ + 48000 1100000 + 200000 1100000 + 500000 1100000 + 666000 1100000 + >; + clock-latency = <256000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + reg = <0x1>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc2>; + qcom,saw = <&saw2>; + reg = <0x2>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + enable-method = "qcom,kpss-acc-v1"; + qcom,acc = <&acc3>; + qcom,saw = <&saw3>; + reg = <0x3>; + clocks = <&gcc GCC_APPS_CLK_SRC>; + clock-frequency = <0>; + }; + }; + + clocks { + sleep_clk: sleep_clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + intc: interrupt-controller@b000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x0b000000 0x1000>, + <0x0b002000 0x1000>; + }; + + gcc: clock-controller@1800000 { + compatible = "qcom,gcc-ipq4019"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0x1800000 0x60000>; + }; + + tlmm: pinctrl@0x01000000 { + compatible = "qcom,ipq4019-pinctrl"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 208 0>; + }; + + blsp_dma: dma@7884000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x07884000 0x23000>; + interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + status = "disabled"; + }; + + spi_0: spi@78b5000 { + compatible = "qcom,spi-qup-v2.2.1"; + reg = <0x78b5000 0x600>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_0: i2c@78b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x78b7000 0x6000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "iface", "core"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + + cryptobam: dma@8e04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x08e04000 0x20000>; + interrupts = <GIC_SPI 207 0>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <1>; + qcom,controlled-remotely; + status = "disabled"; + }; + + crypto@8e3a000 { + compatible = "qcom,crypto-v5.1"; + reg = <0x08e3a000 0x6000>; + clocks = <&gcc GCC_CRYPTO_AHB_CLK>, + <&gcc GCC_CRYPTO_AXI_CLK>, + <&gcc GCC_CRYPTO_CLK>; + clock-names = "iface", "bus", "core"; + dmas = <&cryptobam 2>, <&cryptobam 3>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + acc0: clock-controller@b088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b088000 0x1000>, <0xb008000 0x1000>; + }; + + acc1: clock-controller@b098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b098000 0x1000>, <0xb008000 0x1000>; + }; + + acc2: clock-controller@b0a8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>; + }; + + acc3: clock-controller@b0b8000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>; + }; + + saw0: regulator@b089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw1: regulator@b099000 { + compatible = "qcom,saw2"; + reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw2: regulator@b0a9000 { + compatible = "qcom,saw2"; + reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + saw3: regulator@b0b9000 { + compatible = "qcom,saw2"; + reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>; + regulator; + }; + + serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + interrupts = <0 107 0>; + status = "disabled"; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 1>, <&blsp_dma 0>; + dma-names = "rx", "tx"; + }; + + serial@78b0000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78b0000 0x200>; + interrupts = <0 108 0>; + status = "disabled"; + clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + dmas = <&blsp_dma 3>, <&blsp_dma 2>; + dma-names = "rx", "tx"; + }; + + watchdog@b017000 { + compatible = "qcom,kpss-standalone"; + reg = <0xb017000 0x40>; + clocks = <&sleep_clk>; + timeout-sec = <10>; + status = "disabled"; + }; + + restart@4ab000 { + compatible = "qcom,pshold"; + reg = <0x4ab000 0x4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 8193139d0d87..6f164266a010 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -49,8 +49,13 @@ no-map; }; - efs@0fd600000 { - reg = <0x0fd60000 0x1a0000>; + rfsa@0fd60000 { + reg = <0x0fd60000 0x20000>; + no-map; + }; + + rmtfs@0fd80000 { + reg = <0x0fd80000 0x180000>; no-map; }; @@ -163,6 +168,31 @@ hwlocks = <&tcsr_mutex 3>; }; + smp2p-modem { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + + interrupt-parent = <&intc>; + interrupts = <0 27 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 14>; + + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + smp2p-wcnss { compatible = "qcom,smp2p"; qcom,smem = <451>, <431>; @@ -440,6 +470,17 @@ interrupts = <0 208 0>; }; + i2c@f9924000 { + status = "disabled"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9924000 0x1000>; + interrupts = <0 96 IRQ_TYPE_NONE>; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + blsp_i2c8: i2c@f9964000 { status = "disabled"; compatible = "qcom,i2c-qup-v2.1.1"; @@ -482,6 +523,13 @@ smd { compatible = "qcom,smd"; + modem { + interrupts = <0 25 IRQ_TYPE_EDGE_RISING>; + + qcom,ipc = <&apcs 8 12>; + qcom,smd-edge = <0>; + }; + rpm { interrupts = <0 168 1>; qcom,ipc = <&apcs 8 0>; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 89e46ebef1bc..e8e2a5d71976 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -37,46 +37,41 @@ #size-cells = <1>; /* External clocks */ - extal_clk: extal_clk { + extal_clk: extal { #clock-cells = <0>; compatible = "fixed-clock"; /* If clk present, value must be set by board */ clock-frequency = <0>; - clock-output-names = "extal"; }; - usb_x1_clk: usb_x1_clk { + usb_x1_clk: usb_x1 { #clock-cells = <0>; compatible = "fixed-clock"; /* If clk present, value must be set by board */ clock-frequency = <0>; - clock-output-names = "usb_x1"; }; /* Fixed factor clocks */ - b_clk: b_clk { + b_clk: b { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R7S72100_CLK_PLL>; clock-mult = <1>; clock-div = <3>; - clock-output-names = "b"; }; - p1_clk: p1_clk { + p1_clk: p1 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R7S72100_CLK_PLL>; clock-mult = <1>; clock-div = <6>; - clock-output-names = "p1"; }; - p0_clk: p0_clk { + p0_clk: p0 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R7S72100_CLK_PLL>; clock-mult = <1>; clock-div = <12>; - clock-output-names = "p0"; }; /* Special CPG clocks */ diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts index 590257095700..93ace33e3e36 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts @@ -189,28 +189,28 @@ &pfc { scifa0_pins: serial0 { - renesas,groups = "scifa0_data"; - renesas,function = "scifa0"; + groups = "scifa0_data"; + function = "scifa0"; }; mmc0_pins: mmc { - renesas,groups = "mmc0_data8", "mmc0_ctrl"; - renesas,function = "mmc0"; + groups = "mmc0_data8", "mmc0_ctrl"; + function = "mmc0"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; + function = "sdhi0"; }; sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; }; keyboard_pins: keyboard { - renesas,pins = "PORT324", "PORT325", "PORT326", "PORT327", - "PORT328", "PORT329"; + pins = "PORT324", "PORT325", "PORT326", "PORT327", "PORT328", + "PORT329"; bias-pull-up; }; }; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index 6583a1dfca1f..6954912a3753 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -486,37 +486,32 @@ ranges; /* External root clocks */ - extalr_clk: extalr_clk { + extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; - clock-output-names = "extalr"; }; - extal1_clk: extal1_clk { + extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; - clock-output-names = "extal1"; }; - extal2_clk: extal2_clk { + extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; - clock-output-names = "extal2"; }; - fsiack_clk: fsiack_clk { + fsiack_clk: fsiack { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - clock-output-names = "fsiack"; }; - fsibck_clk: fsibck_clk { + fsibck_clk: fsibck { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - clock-output-names = "fsibck"; }; /* Special CPG clocks */ @@ -540,171 +535,151 @@ #clock-cells = <0>; clock-output-names = "zb"; }; - sdhi0_clk: sdhi0_clk@e6150074 { + sdhi0_clk: sdhi0ck@e6150074 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150074 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "sdhi0ck"; }; - sdhi1_clk: sdhi1_clk@e6150078 { + sdhi1_clk: sdhi1ck@e6150078 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "sdhi1ck"; }; - sdhi2_clk: sdhi2_clk@e615007c { + sdhi2_clk: sdhi2ck@e615007c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615007c 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "sdhi2ck"; }; - mmc0_clk: mmc0_clk@e6150240 { + mmc0_clk: mmc0@e6150240 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "mmc0"; }; - mmc1_clk: mmc1_clk@e6150244 { + mmc1_clk: mmc1@e6150244 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150244 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "mmc1"; }; - vclk1_clk: vclk1_clk@e6150008 { + vclk1_clk: vclk1@e6150008 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150008 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk1"; }; - vclk2_clk: vclk2_clk@e615000c { + vclk2_clk: vclk2@e615000c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615000c 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk2"; }; - vclk3_clk: vclk3_clk@e615001c { + vclk3_clk: vclk3@e615001c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615001c 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk3"; }; - vclk4_clk: vclk4_clk@e6150014 { + vclk4_clk: vclk4@e6150014 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150014 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk4"; }; - vclk5_clk: vclk5_clk@e6150034 { + vclk5_clk: vclk5@e6150034 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150034 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>, <&extal2_clk>, <&main_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk5"; }; - fsia_clk: fsia_clk@e6150018 { + fsia_clk: fsia@e6150018 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150018 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&fsiack_clk>, <0>; #clock-cells = <0>; - clock-output-names = "fsia"; }; - fsib_clk: fsib_clk@e6150090 { + fsib_clk: fsib@e6150090 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150090 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&fsibck_clk>, <0>; #clock-cells = <0>; - clock-output-names = "fsib"; }; - mp_clk: mp_clk@e6150080 { + mp_clk: mp@e6150080 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150080 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "mp"; }; - m4_clk: m4_clk@e6150098 { + m4_clk: m4@e6150098 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150098 0 4>; clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; #clock-cells = <0>; - clock-output-names = "m4"; }; - hsi_clk: hsi_clk@e615026c { + hsi_clk: hsi@e615026c { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; #clock-cells = <0>; - clock-output-names = "hsi"; }; - spuv_clk: spuv_clk@e6150094 { + spuv_clk: spuv@e6150094 { compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150094 0 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "spuv"; }; /* Fixed factor clocks */ - main_div2_clk: main_div2_clk { + main_div2_clk: main_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "main_div2"; }; - pll0_div2_clk: pll0_div2_clk { + pll0_div2_clk: pll0_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll0_div2"; }; - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - extal1_div2_clk: extal1_div2_clk { + extal1_div2_clk: extal1_div2 { compatible = "fixed-factor-clock"; clocks = <&extal1_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "extal1_div2"; }; /* Gate clocks */ diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index c548cabb102f..2c82dab2b6f4 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -228,44 +228,44 @@ pinctrl-names = "default"; ether_pins: ether { - renesas,groups = "gether_mii", "gether_int"; - renesas,function = "gether"; + groups = "gether_mii", "gether_int"; + function = "gether"; }; scifa1_pins: serial1 { - renesas,groups = "scifa1_data"; - renesas,function = "scifa1"; + groups = "scifa1_data"; + function = "scifa1"; }; st1232_pins: touchscreen { - renesas,groups = "intc_irq10"; - renesas,function = "intc"; + groups = "intc_irq10"; + function = "intc"; }; backlight_pins: backlight { - renesas,groups = "tpu0_to2_1"; - renesas,function = "tpu0"; + groups = "tpu0_to2_1"; + function = "tpu0"; }; mmc0_pins: mmc0 { - renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1"; - renesas,function = "mmc0"; + groups = "mmc0_data8_1", "mmc0_ctrl_1"; + function = "mmc0"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; + function = "sdhi0"; }; fsia_pins: sounda { - renesas,groups = "fsia_sclk_in", "fsia_mclk_out", - "fsia_data_in_1", "fsia_data_out_0"; - renesas,function = "fsia"; + groups = "fsia_sclk_in", "fsia_mclk_out", + "fsia_data_in_1", "fsia_data_out_0"; + function = "fsia"; }; lcd0_pins: lcd0 { - renesas,groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; - renesas,function = "lcd0"; + groups = "lcd0_data24_0", "lcd0_lclk_1", "lcd0_sync"; + function = "lcd0"; /* DBGMD/LCDC0/FSIA MUX */ gpio-hog; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index 995fbda74b7a..39b2f88ad151 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -422,53 +422,45 @@ ranges; /* External root clock */ - extalr_clk: extalr_clk { + extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; - clock-output-names = "extalr"; }; - extal1_clk: extal1_clk { + extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "extal1"; }; - extal2_clk: extal2_clk { + extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "extal2"; }; - dv_clk: dv_clk { + dv_clk: dv { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; - clock-output-names = "dv"; }; - fmsick_clk: fmsick_clk { + fmsick_clk: fmsick { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fmsick"; }; - fmsock_clk: fmsock_clk { + fmsock_clk: fmsock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fmsock"; }; - fsiack_clk: fsiack_clk { + fsiack_clk: fsiack { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fsiack"; }; - fsibck_clk: fsibck_clk { + fsibck_clk: fsibck { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fsibck"; }; /* Special CPG clocks */ @@ -486,7 +478,7 @@ }; /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1_clk@e6150008 { + vclk1_clk: vclk1@e6150008 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150008 4>; clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, @@ -494,9 +486,8 @@ <&extal1_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk1"; }; - vclk2_clk: vclk2_clk@e615000c { + vclk2_clk: vclk2@e615000c { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615000c 4>; clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>, @@ -504,77 +495,67 @@ <&extal1_div2_clk>, <&extalr_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "vclk2"; }; - fmsi_clk: fmsi_clk@e6150010 { + fmsi_clk: fmsi@e6150010 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150010 4>; clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "fmsi"; }; - fmso_clk: fmso_clk@e6150014 { + fmso_clk: fmso@e6150014 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150014 4>; clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "fmso"; }; - fsia_clk: fsia_clk@e6150018 { + fsia_clk: fsia@e6150018 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150018 4>; clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "fsia"; }; - sub_clk: sub_clk@e6150080 { + sub_clk: sub@e6150080 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150080 4>; clocks = <&pllc1_div2_clk>, <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "sub"; }; - spu_clk: spu_clk@e6150084 { + spu_clk: spu@e6150084 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150084 4>; clocks = <&pllc1_div2_clk>, <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "spu"; }; - vou_clk: vou_clk@e6150088 { + vou_clk: vou@e6150088 { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150088 4>; clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>, <0>; #clock-cells = <0>; - clock-output-names = "vou"; }; - stpro_clk: stpro_clk@e615009c { + stpro_clk: stpro@e615009c { compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; clocks = <&cpg_clocks R8A7740_CLK_PLLC0>; #clock-cells = <0>; - clock-output-names = "stpro"; }; /* Fixed factor clocks */ - pllc1_div2_clk: pllc1_div2_clk { + pllc1_div2_clk: pllc1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pllc1_div2"; }; - extal1_div2_clk: extal1_div2_clk { + extal1_div2_clk: extal1_div2 { compatible = "fixed-factor-clock"; clocks = <&extal1_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "extal1_div2"; }; /* Gate clocks */ diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts index 21e3b9dda2da..e0dab1464648 100644 --- a/arch/arm/boot/dts/r8a7778-bockw.dts +++ b/arch/arm/boot/dts/r8a7778-bockw.dts @@ -130,53 +130,53 @@ pinctrl-names = "default"; scif0_pins: serial0 { - renesas,groups = "scif0_data_a", "scif0_ctrl"; - renesas,function = "scif0"; + groups = "scif0_data_a", "scif0_ctrl"; + function = "scif0"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; mmc_pins: mmc { - renesas,groups = "mmc_data8", "mmc_ctrl"; - renesas,function = "mmc"; + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; }; sdhi0_pup_pins: sd0_pup { - renesas,groups = "sdhi0_cd", "sdhi0_wp"; - renesas,function = "sdhi0"; + groups = "sdhi0_cd", "sdhi0_wp"; + function = "sdhi0"; bias-pull-up; }; hspi0_pins: hspi0 { - renesas,groups = "hspi0_a"; - renesas,function = "hspi0"; + groups = "hspi0_a"; + function = "hspi0"; }; usb0_pins: usb0 { - renesas,groups = "usb0"; - renesas,function = "usb0"; + groups = "usb0"; + function = "usb0"; }; usb1_pins: usb1 { - renesas,groups = "usb1"; - renesas,function = "usb1"; + groups = "usb1"; + function = "usb1"; }; vin0_pins: vin0 { - renesas,groups = "vin0_data8", "vin0_clk"; - renesas,function = "vin0"; + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; }; vin1_pins: vin1 { - renesas,groups = "vin1_data8", "vin1_clk"; - renesas,function = "vin1"; + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; }; }; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index f83a348fc07a..fe787b4751d2 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -443,11 +443,10 @@ ranges; /* External input clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "extal"; }; /* External SCIF clock */ @@ -456,7 +455,6 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - status = "disabled"; }; /* Special CPG clocks */ @@ -474,59 +472,51 @@ audio_clk_a: audio_clk_a { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "audio_clk_a"; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "audio_clk_b"; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "audio_clk_c"; }; /* Fixed ratio clocks */ - g_clk: g_clk { + g_clk: g { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7778_CLK_PLLA>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "g"; }; - i_clk: i_clk { + i_clk: i { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7778_CLK_PLLA>; #clock-cells = <0>; clock-div = <1>; clock-mult = <1>; - clock-output-names = "i"; }; - s3_clk: s3_clk { + s3_clk: s3 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7778_CLK_PLLA>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "s3"; }; - s4_clk: s4_clk { + s4_clk: s4 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7778_CLK_PLLA>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "s4"; }; - z_clk: z_clk { + z_clk: z { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7778_CLK_PLLB>; #clock-cells = <0>; clock-div = <1>; clock-mult = <1>; - clock-output-names = "z"; }; /* Gate clocks */ diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index e111d35d02ae..b795da6f5503 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -170,49 +170,49 @@ du_pins: du { du0 { - renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0"; - renesas,function = "du0"; + groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0"; + function = "du0"; }; du1 { - renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; - renesas,function = "du1"; + groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; + function = "du1"; }; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk_b"; - renesas,function = "scif_clk"; + groups = "scif_clk_b"; + function = "scif_clk"; }; ethernet_pins: ethernet { intc { - renesas,groups = "intc_irq1_b"; - renesas,function = "intc"; + groups = "intc_irq1_b"; + function = "intc"; }; lbsc { - renesas,groups = "lbsc_ex_cs0"; - renesas,function = "lbsc"; + groups = "lbsc_ex_cs0"; + function = "lbsc"; }; }; scif2_pins: serial2 { - renesas,groups = "scif2_data_c"; - renesas,function = "scif2"; + groups = "scif2_data_c"; + function = "scif2"; }; scif4_pins: serial4 { - renesas,groups = "scif4_data"; - renesas,function = "scif4"; + groups = "scif4_data"; + function = "scif4"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd"; + function = "sdhi0"; }; hspi0_pins: hspi0 { - renesas,groups = "hspi0"; - renesas,function = "hspi0"; + groups = "hspi0"; + function = "hspi0"; }; }; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index a0cc08e6295b..0c82097daffc 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -67,7 +67,7 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xf0000600 0x20>; interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; clocks = <&cpg_clocks R8A7779_CLK_ZS>; }; @@ -445,12 +445,11 @@ ranges; /* External root clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; - clock-output-names = "extal"; }; /* External SCIF clock */ @@ -459,7 +458,6 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - status = "disabled"; }; /* Special CPG clocks */ @@ -474,37 +472,33 @@ }; /* Fixed factor clocks */ - i_clk: i_clk { + i_clk: i { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7779_CLK_PLLA>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "i"; }; - s3_clk: s3_clk { + s3_clk: s3 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7779_CLK_PLLA>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "s3"; }; - s4_clk: s4_clk { + s4_clk: s4 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7779_CLK_PLLA>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; - clock-output-names = "s4"; }; - g_clk: g_clk { + g_clk: g { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7779_CLK_PLLA>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; - clock-output-names = "g"; }; /* Gate clocks */ diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index aa6ca92a9485..749ba02b6a53 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -176,11 +176,10 @@ 1800000 0>; }; - audio_clock: clock { + audio_clock: audio_clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <11289600>; - clock-output-names = "audio_clock"; }; rsnd_ak4643: sound { @@ -314,119 +313,133 @@ pinctrl-names = "default"; du_pins: du { - renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; - renesas,function = "du"; + groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; + function = "du"; }; scif0_pins: serial0 { - renesas,groups = "scif0_data"; - renesas,function = "scif0"; + groups = "scif0_data"; + function = "scif0"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq0"; - renesas,function = "intc"; + groups = "intc_irq0"; + function = "intc"; }; scifa1_pins: serial1 { - renesas,groups = "scifa1_data"; - renesas,function = "scifa1"; + groups = "scifa1_data"; + function = "scifa1"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; }; sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; }; mmc1_pins: mmc1 { - renesas,groups = "mmc1_data8", "mmc1_ctrl"; - renesas,function = "mmc1"; + groups = "mmc1_data8", "mmc1_ctrl"; + function = "mmc1"; }; qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; msiof1_pins: spi2 { - renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", + groups = "msiof1_clk", "msiof1_sync", "msiof1_rx", "msiof1_tx"; - renesas,function = "msiof1"; + function = "msiof1"; }; i2c0_pins: i2c0 { - renesas,groups = "i2c0"; - renesas,function = "i2c0"; + groups = "i2c0"; + function = "i2c0"; }; iic0_pins: iic0 { - renesas,groups = "iic0"; - renesas,function = "iic0"; + groups = "iic0"; + function = "iic0"; }; iic1_pins: iic1 { - renesas,groups = "iic1"; - renesas,function = "iic1"; + groups = "iic1"; + function = "iic1"; }; iic2_pins: iic2 { - renesas,groups = "iic2"; - renesas,function = "iic2"; + groups = "iic2"; + function = "iic2"; }; iic3_pins: iic3 { - renesas,groups = "iic3"; - renesas,function = "iic3"; + groups = "iic3"; + function = "iic3"; }; hsusb_pins: hsusb { - renesas,groups = "usb0_ovc_vbus"; - renesas,function = "usb0"; + groups = "usb0_ovc_vbus"; + function = "usb0"; }; usb0_pins: usb0 { - renesas,groups = "usb0"; - renesas,function = "usb0"; + groups = "usb0"; + function = "usb0"; }; usb1_pins: usb1 { - renesas,groups = "usb1"; - renesas,function = "usb1"; + groups = "usb1"; + function = "usb1"; }; usb2_pins: usb2 { - renesas,groups = "usb2"; - renesas,function = "usb2"; + groups = "usb2"; + function = "usb2"; }; vin1_pins: vin { - renesas,groups = "vin1_data8", "vin1_clk"; - renesas,function = "vin1"; + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; }; sound_pins: sound { - renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - renesas,function = "ssi"; + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; }; sound_clk_pins: sound_clk { - renesas,groups = "audio_clk_a"; - renesas,function = "audio_clk"; + groups = "audio_clk_a"; + function = "audio_clk"; }; }; @@ -539,21 +552,25 @@ &sdhi0 { pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; }; &sdhi2 { pinctrl-0 = <&sdhi2_pins>; - pinctrl-names = "default"; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; vmmc-supply = <&vcc_sdhi2>; vqmmc-supply = <&vccq_sdhi2>; cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + sd-uhs-sdr50; status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 38b706399a6b..935064fe7b13 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -589,6 +589,7 @@ clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; dmas = <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx"; + max-frequency = <195000000>; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -600,6 +601,7 @@ clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; dmas = <&dmac1 0xc9>, <&dmac1 0xca>; dma-names = "tx", "rx"; + max-frequency = <195000000>; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -611,6 +613,7 @@ clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx"; + max-frequency = <97500000>; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -622,6 +625,7 @@ clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx"; + max-frequency = <97500000>; power-domains = <&cpg_clocks>; status = "disabled"; }; @@ -732,6 +736,20 @@ status = "disabled"; }; + scif2: serial@e6e56000 { + compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif", + "renesas,scif"; + reg = <0 0xe6e56000 0 64>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x2b>, <&dmac0 0x2c>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + hscif0: serial@e62c0000 { compatible = "renesas,hscif-r8a7790", "renesas,rcar-gen2-hscif", "renesas,hscif"; @@ -968,7 +986,7 @@ }; can0: can@e6e80000 { - compatible = "renesas,can-r8a7790"; + compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, @@ -979,7 +997,7 @@ }; can1: can@e6e88000 { - compatible = "renesas,can-r8a7790"; + compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, @@ -990,7 +1008,7 @@ }; jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7790"; + compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7790_CLK_JPU>; @@ -1003,21 +1021,18 @@ ranges; /* External root clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; - clock-output-names = "extal"; }; /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus_clk { + pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "pcie_bus"; - status = "disabled"; + clock-frequency = <0>; }; /* @@ -1028,19 +1043,16 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_a"; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_b"; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_c"; }; /* External SCIF clock */ @@ -1049,15 +1061,13 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - status = "disabled"; }; /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal_clk { + usb_extal_clk: usb_extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; - clock-output-names = "usb_extal"; }; /* External CAN clock */ @@ -1066,8 +1076,6 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - clock-output-names = "can_clk"; - status = "disabled"; }; /* Special CPG clocks */ @@ -1084,201 +1092,176 @@ }; /* Variable factor clocks */ - sd2_clk: sd2_clk@e6150078 { + sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; }; - sd3_clk: sd3_clk@e615026c { + sd3_clk: sd3@e615026c { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd3"; }; - mmc0_clk: mmc0_clk@e6150240 { + mmc0_clk: mmc0@e6150240 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "mmc0"; }; - mmc1_clk: mmc1_clk@e6150244 { + mmc1_clk: mmc1@e6150244 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150244 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "mmc1"; }; - ssp_clk: ssp_clk@e6150248 { + ssp_clk: ssp@e6150248 { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150248 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "ssp"; }; - ssprs_clk: ssprs_clk@e615024c { + ssprs_clk: ssprs@e615024c { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615024c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "ssprs"; }; /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - z2_clk: z2_clk { + z2_clk: z2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "z2"; }; - zg_clk: zg_clk { + zg_clk: zg { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zg"; }; - zx_clk: zx_clk { + zx_clk: zx { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zx"; }; - zs_clk: zs_clk { + zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; - clock-output-names = "zs"; }; - hp_clk: hp_clk { + hp_clk: hp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "hp"; }; - i_clk: i_clk { + i_clk: i { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "i"; }; - b_clk: b_clk { + b_clk: b { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "b"; }; - p_clk: p_clk { + p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; - clock-output-names = "p"; }; - cl_clk: cl_clk { + cl_clk: cl { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; - clock-output-names = "cl"; }; - m2_clk: m2_clk { + m2_clk: m2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "m2"; }; - imp_clk: imp_clk { + imp_clk: imp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "imp"; }; - rclk_clk: rclk_clk { + rclk_clk: rclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; - clock-output-names = "rclk"; }; - oscclk_clk: oscclk_clk { + oscclk_clk: oscclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL1>; #clock-cells = <0>; clock-div = <(12 * 1024)>; clock-mult = <1>; - clock-output-names = "oscclk"; }; - zb3_clk: zb3_clk { + zb3_clk: zb3 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL3>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "zb3"; }; - zb3d2_clk: zb3d2_clk { + zb3d2_clk: zb3d2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "zb3d2"; }; - ddr_clk: ddr_clk { + ddr_clk: ddr { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7790_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "ddr"; }; - mp_clk: mp_clk { + mp_clk: mp { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; - clock-output-names = "mp"; }; - cp_clk: cp_clk { + cp_clk: cp { compatible = "fixed-factor-clock"; clocks = <&extal_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "cp"; }; /* Gate clocks */ @@ -1334,19 +1317,19 @@ mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, + clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; clock-indices = < - R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 + R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 >; clock-output-names = - "iic2", "tpu0", "mmcif1", "sdhi3", + "iic2", "tpu0", "mmcif1", "scif2", "sdhi3", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "iic0", "pciec", "iic1", "ssusb", "cmt1", "usbdmac0", "usbdmac1"; @@ -1531,7 +1514,7 @@ }; xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7790"; + compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci"; reg = <0 0xee000000 0 0xc00>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index cc6e28f81fe4..da59c2844b8a 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -242,11 +242,10 @@ 1800000 0>; }; - audio_clock: clock { + audio_clock: audio_clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <11289600>; - clock-output-names = "audio_clock"; }; rsnd_ak4643: sound { @@ -324,89 +323,89 @@ pinctrl-names = "default"; i2c2_pins: i2c2 { - renesas,groups = "i2c2"; - renesas,function = "i2c2"; + groups = "i2c2"; + function = "i2c2"; }; du_pins: du { - renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - renesas,function = "du"; + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; }; scif0_pins: serial0 { - renesas,groups = "scif0_data_d"; - renesas,function = "scif0"; + groups = "scif0_data_d"; + function = "scif0"; }; scif1_pins: serial1 { - renesas,groups = "scif1_data_d"; - renesas,function = "scif1"; + groups = "scif1_data_d"; + function = "scif1"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq0"; - renesas,function = "intc"; + groups = "intc_irq0"; + function = "intc"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; }; sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; }; sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; }; qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; msiof0_pins: spi1 { - renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", + groups = "msiof0_clk", "msiof0_sync", "msiof0_rx", "msiof0_tx"; - renesas,function = "msiof0"; + function = "msiof0"; }; usb0_pins: usb0 { - renesas,groups = "usb0"; - renesas,function = "usb0"; + groups = "usb0"; + function = "usb0"; }; usb1_pins: usb1 { - renesas,groups = "usb1"; - renesas,function = "usb1"; + groups = "usb1"; + function = "usb1"; }; vin1_pins: vin1 { - renesas,groups = "vin1_data8", "vin1_clk"; - renesas,function = "vin1"; + groups = "vin1_data8", "vin1_clk"; + function = "vin1"; }; sound_pins: sound { - renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - renesas,function = "ssi"; + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; }; sound_clk_pins: sound_clk { - renesas,groups = "audio_clk_a"; - renesas,function = "audio_clk"; + groups = "audio_clk_a"; + function = "audio_clk"; }; }; diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index a9285d9a57cd..6a1bb1a8209b 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -113,11 +113,10 @@ clock-frequency = <74250000>; }; - x14_clk: x14-clock { + x14_clk: audio_clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <11289600>; - clock-output-names = "audio_clock"; }; sound { @@ -144,73 +143,73 @@ &pfc { scif0_pins: serial0 { - renesas,groups = "scif0_data_d"; - renesas,function = "scif0"; + groups = "scif0_data_d"; + function = "scif0"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq0"; - renesas,function = "intc"; + groups = "intc_irq0"; + function = "intc"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; }; sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; }; qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; i2c2_pins: i2c2 { - renesas,groups = "i2c2"; - renesas,function = "i2c2"; + groups = "i2c2"; + function = "i2c2"; }; usb0_pins: usb0 { - renesas,groups = "usb0"; - renesas,function = "usb0"; + groups = "usb0"; + function = "usb0"; }; usb1_pins: usb1 { - renesas,groups = "usb1"; - renesas,function = "usb1"; + groups = "usb1"; + function = "usb1"; }; vin0_pins: vin0 { - renesas,groups = "vin0_data8", "vin0_clk"; - renesas,function = "vin0"; + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; }; can0_pins: can0 { - renesas,groups = "can0_data"; - renesas,function = "can0"; + groups = "can0_data"; + function = "can0"; }; du_pins: du { - renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - renesas,function = "du"; + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; }; ssi_pins: sound { - renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - renesas,function = "ssi"; + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; }; audio_clk_pins: audio_clk { - renesas,groups = "audio_clk_a"; - renesas,function = "audio_clk"; + groups = "audio_clk_a"; + function = "audio_clk"; }; }; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 1cd1b6a3a72a..565c270e549d 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1013,7 +1013,7 @@ }; can0: can@e6e80000 { - compatible = "renesas,can-r8a7791"; + compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, @@ -1024,7 +1024,7 @@ }; can1: can@e6e88000 { - compatible = "renesas,can-r8a7791"; + compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, @@ -1035,7 +1035,7 @@ }; jpu: jpeg-codec@fe980000 { - compatible = "renesas,jpu-r8a7791"; + compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7791_CLK_JPU>; @@ -1048,12 +1048,11 @@ ranges; /* External root clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; - clock-output-names = "extal"; }; /* @@ -1064,27 +1063,23 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_a"; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_b"; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_c"; }; /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus_clk { + pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "pcie_bus"; }; /* External SCIF clock */ @@ -1096,11 +1091,10 @@ }; /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal_clk { + usb_extal_clk: usb_extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; - clock-output-names = "usb_extal"; }; /* External CAN clock */ @@ -1109,7 +1103,6 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - clock-output-names = "can_clk"; }; /* Special CPG clocks */ @@ -1126,178 +1119,156 @@ }; /* Variable factor clocks */ - sd2_clk: sd2_clk@e6150078 { + sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; }; - sd3_clk: sd3_clk@e615026c { + sd3_clk: sd3@e615026c { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd3"; }; - mmc0_clk: mmc0_clk@e6150240 { + mmc0_clk: mmc0@e6150240 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "mmc0"; }; - ssp_clk: ssp_clk@e6150248 { + ssp_clk: ssp@e6150248 { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150248 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "ssp"; }; - ssprs_clk: ssprs_clk@e615024c { + ssprs_clk: ssprs@e615024c { compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615024c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "ssprs"; }; /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - zg_clk: zg_clk { + zg_clk: zg { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zg"; }; - zx_clk: zx_clk { + zx_clk: zx { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zx"; }; - zs_clk: zs_clk { + zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; - clock-output-names = "zs"; }; - hp_clk: hp_clk { + hp_clk: hp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "hp"; }; - i_clk: i_clk { + i_clk: i { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "i"; }; - b_clk: b_clk { + b_clk: b { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "b"; }; - p_clk: p_clk { + p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; - clock-output-names = "p"; }; - cl_clk: cl_clk { + cl_clk: cl { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; - clock-output-names = "cl"; }; - m2_clk: m2_clk { + m2_clk: m2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "m2"; }; - rclk_clk: rclk_clk { + rclk_clk: rclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; - clock-output-names = "rclk"; }; - oscclk_clk: oscclk_clk { + oscclk_clk: oscclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL1>; #clock-cells = <0>; clock-div = <(12 * 1024)>; clock-mult = <1>; - clock-output-names = "oscclk"; }; - zb3_clk: zb3_clk { + zb3_clk: zb3 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL3>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "zb3"; }; - zb3d2_clk: zb3d2_clk { + zb3d2_clk: zb3d2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "zb3d2"; }; - ddr_clk: ddr_clk { + ddr_clk: ddr { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7791_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "ddr"; }; - mp_clk: mp_clk { + mp_clk: mp { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; - clock-output-names = "mp"; }; - cp_clk: cp_clk { + cp_clk: cp { compatible = "fixed-factor-clock"; clocks = <&extal_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "cp"; }; /* Gate clocks */ @@ -1546,7 +1517,7 @@ }; xhci: usb@ee000000 { - compatible = "renesas,xhci-r8a7791"; + compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci"; reg = <0 0xee000000 0 0xc00>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 87e89ec9dd47..0ebc3ee34923 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -158,11 +158,82 @@ }; }; - audio_clock: clock { + vcc_sdhi0: regulator@0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator@1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi1: regulator@2 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator@3 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi2: regulator@4 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI2 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi2: regulator@5 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI2 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + audio_clock: audio_clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <11289600>; - clock-output-names = "audio_clock"; }; rsnd_ak4643: sound { @@ -240,53 +311,68 @@ pinctrl-names = "default"; i2c2_pins: i2c2 { - renesas,groups = "i2c2"; - renesas,function = "i2c2"; + groups = "i2c2"; + function = "i2c2"; }; du_pins: du { - renesas,groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; - renesas,function = "du"; + groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; + function = "du"; }; scif0_pins: serial0 { - renesas,groups = "scif0_data_d"; - renesas,function = "scif0"; + groups = "scif0_data_d"; + function = "scif0"; }; scif1_pins: serial1 { - renesas,groups = "scif1_data_d"; - renesas,function = "scif1"; + groups = "scif1_data_d"; + function = "scif1"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq0"; - renesas,function = "intc"; + groups = "intc_irq0"; + function = "intc"; + }; + + sdhi0_pins: sd0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl"; + renesas,function = "sdhi0"; + }; + + sdhi1_pins: sd1 { + renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; + renesas,function = "sdhi1"; + }; + + sdhi2_pins: sd2 { + renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; + renesas,function = "sdhi2"; }; qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; sound_pins: sound { - renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; - renesas,function = "ssi"; + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; }; sound_clk_pins: sound_clk { - renesas,groups = "audio_clk_a"; - renesas,function = "audio_clk"; + groups = "audio_clk_a"; + function = "audio_clk"; }; }; @@ -329,6 +415,38 @@ status = "okay"; }; +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sdhi2 { + pinctrl-0 = <&sdhi2_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi2>; + vqmmc-supply = <&vccq_sdhi2>; + cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &qspi { pinctrl-0 = <&qspi_pins>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index b48215945241..cf6dc2aeef20 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -507,6 +507,39 @@ reg = <0 0xe6060000 0 0x250>; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7793"; + reg = <0 0xee100000 0 0x328>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_SDHI0>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7793"; + reg = <0 0xee140000 0 0x100>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_SDHI1>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7793"; + reg = <0 0xee160000 0 0x100>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7793_CLK_SDHI2>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7793", "renesas,rcar-gen2-scifa", "renesas,scifa"; @@ -806,18 +839,39 @@ }; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7793_CLK_RCAN0>, + <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7793_CLK_RCAN1>, + <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; ranges; /* External root clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - clock-output-names = "extal"; }; /* @@ -828,19 +882,31 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_a"; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_b"; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "audio_clk_c"; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; /* External SCIF clock */ @@ -849,7 +915,6 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - status = "disabled"; }; /* Special CPG clocks */ @@ -857,7 +922,7 @@ compatible = "renesas,r8a7793-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; + clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "z", @@ -866,111 +931,98 @@ }; /* Variable factor clocks */ - sd2_clk: sd2_clk@e6150078 { + sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7793-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; }; - sd3_clk: sd3_clk@e615026c { + sd3_clk: sd3@e615026c { compatible = "renesas,r8a7793-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd3"; }; - mmc0_clk: mmc0_clk@e6150240 { + mmc0_clk: mmc0@e6150240 { compatible = "renesas,r8a7793-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "mmc0"; }; /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - zg_clk: zg_clk { + zg_clk: zg { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <5>; clock-mult = <1>; - clock-output-names = "zg"; }; - zx_clk: zx_clk { + zx_clk: zx { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zx"; }; - zs_clk: zs_clk { + zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; - clock-output-names = "zs"; }; - hp_clk: hp_clk { + hp_clk: hp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "hp"; }; - p_clk: p_clk { + p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; - clock-output-names = "p"; }; - m2_clk: m2_clk { + m2_clk: m2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "m2"; }; - rclk_clk: rclk_clk { + rclk_clk: rclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7793_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; - clock-output-names = "rclk"; }; - mp_clk: mp_clk { + mp_clk: mp { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; - clock-output-names = "mp"; }; - cp_clk: cp_clk { + cp_clk: cp { compatible = "fixed-factor-clock"; clocks = <&extal_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "cp"; }; /* Gate clocks */ @@ -1098,6 +1150,7 @@ reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&p_clk>, <&p_clk>, <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; @@ -1107,7 +1160,8 @@ R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0 - R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5 + R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1 + R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0 @@ -1115,8 +1169,9 @@ clock-output-names = "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "qspi_mod", "i2c5", "i2c6", "i2c4", - "i2c3", "i2c2", "i2c1", "i2c0"; + "rcan1", "rcan0", "qspi_mod", "i2c5", + "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", + "i2c0"; }; mstp10_clks: mstp10_clks@e6150998 { compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index ca9bc4fff287..383ad791f1db 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -107,38 +107,38 @@ pinctrl-names = "default"; du_pins: du { - renesas,groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0"; - renesas,function = "du"; + groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0"; + function = "du"; }; scif2_pins: serial2 { - renesas,groups = "scif2_data"; - renesas,function = "scif2"; + groups = "scif2_data"; + function = "scif2"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq8"; - renesas,function = "intc"; + groups = "intc_irq8"; + function = "intc"; }; i2c1_pins: i2c1 { - renesas,groups = "i2c1"; - renesas,function = "i2c1"; + groups = "i2c1"; + function = "i2c1"; }; vin0_pins: vin0 { - renesas,groups = "vin0_data8", "vin0_clk"; - renesas,function = "vin0"; + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; }; }; @@ -148,8 +148,8 @@ &pfc { qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; }; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 66f077a3ca41..56d98d5b2185 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -130,58 +130,58 @@ pinctrl-names = "default"; scif2_pins: serial2 { - renesas,groups = "scif2_data"; - renesas,function = "scif2"; + groups = "scif2_data"; + function = "scif2"; }; scif_clk_pins: scif_clk { - renesas,groups = "scif_clk"; - renesas,function = "scif_clk"; + groups = "scif_clk"; + function = "scif_clk"; }; ether_pins: ether { - renesas,groups = "eth_link", "eth_mdio", "eth_rmii"; - renesas,function = "eth"; + groups = "eth_link", "eth_mdio", "eth_rmii"; + function = "eth"; }; phy1_pins: phy1 { - renesas,groups = "intc_irq8"; - renesas,function = "intc"; + groups = "intc_irq8"; + function = "intc"; }; i2c1_pins: i2c1 { - renesas,groups = "i2c1"; - renesas,function = "i2c1"; + groups = "i2c1"; + function = "i2c1"; }; mmcif0_pins: mmcif0 { - renesas,groups = "mmc_data8", "mmc_ctrl"; - renesas,function = "mmc"; + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; }; sdhi1_pins: sd1 { - renesas,groups = "sdhi1_data4", "sdhi1_ctrl"; - renesas,function = "sdhi1"; + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; }; qspi_pins: spi0 { - renesas,groups = "qspi_ctrl", "qspi_data4"; - renesas,function = "qspi"; + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; }; vin0_pins: vin0 { - renesas,groups = "vin0_data8", "vin0_clk"; - renesas,function = "vin0"; + groups = "vin0_data8", "vin0_clk"; + function = "vin0"; }; usb0_pins: usb0 { - renesas,groups = "usb0"; - renesas,function = "usb0"; + groups = "usb0"; + function = "usb0"; }; usb1_pins: usb1 { - renesas,groups = "usb1"; - renesas,function = "usb1"; + groups = "usb1"; + function = "usb1"; }; }; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index eacb2b291361..e45b23f31149 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -26,6 +26,8 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; spi0 = &qspi; vin0 = &vin0; vin1 = &vin1; @@ -629,6 +631,32 @@ status = "disabled"; }; + i2c6: i2c@e6500000 { + compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_IIC0>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@e6510000 { + compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_IIC1>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>; + dma-names = "tx", "rx"; + power-domains = <&cpg_clocks>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mmcif0: mmc@ee200000 { compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; @@ -830,18 +858,54 @@ }; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_RCAN0>, + <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7794_CLK_RCAN1>, + <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + clocks { #address-cells = <2>; #size-cells = <2>; ranges; /* External root clock */ - extal_clk: extal_clk { + extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overriden by the board. */ clock-frequency = <0>; - clock-output-names = "extal"; + }; + + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; /* External SCIF clock */ @@ -850,7 +914,6 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; - status = "disabled"; }; /* Special CPG clocks */ @@ -858,180 +921,160 @@ compatible = "renesas,r8a7794-cpg-clocks", "renesas,rcar-gen2-cpg-clocks"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>; + clocks = <&extal_clk &usb_extal_clk>; #clock-cells = <1>; clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z"; + "lb", "qspi", "sdh", "sd0", "z", + "rcan"; #power-domain-cells = <0>; }; /* Variable factor clocks */ - sd2_clk: sd2_clk@e6150078 { + sd2_clk: sd2@e6150078 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150078 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd2"; }; - sd3_clk: sd3_clk@e615026c { + sd3_clk: sd3@e615026c { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "sd3"; }; - mmc0_clk: mmc0_clk@e6150240 { + mmc0_clk: mmc0@e6150240 { compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; reg = <0 0xe6150240 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; - clock-output-names = "mmc0"; }; /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - zg_clk: zg_clk { + zg_clk: zg { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; - clock-output-names = "zg"; }; - zx_clk: zx_clk { + zx_clk: zx { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <3>; clock-mult = <1>; - clock-output-names = "zx"; }; - zs_clk: zs_clk { + zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <6>; clock-mult = <1>; - clock-output-names = "zs"; }; - hp_clk: hp_clk { + hp_clk: hp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "hp"; }; - i_clk: i_clk { + i_clk: i { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "i"; }; - b_clk: b_clk { + b_clk: b { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <12>; clock-mult = <1>; - clock-output-names = "b"; }; - p_clk: p_clk { + p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <24>; clock-mult = <1>; - clock-output-names = "p"; }; - cl_clk: cl_clk { + cl_clk: cl { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; - clock-output-names = "cl"; }; - m2_clk: m2_clk { + m2_clk: m2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "m2"; }; - rclk_clk: rclk_clk { + rclk_clk: rclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <(48 * 1024)>; clock-mult = <1>; - clock-output-names = "rclk"; }; - oscclk_clk: oscclk_clk { + oscclk_clk: oscclk { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <(12 * 1024)>; clock-mult = <1>; - clock-output-names = "oscclk"; }; - zb3_clk: zb3_clk { + zb3_clk: zb3 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "zb3"; }; - zb3d2_clk: zb3d2_clk { + zb3d2_clk: zb3d2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "zb3d2"; }; - ddr_clk: ddr_clk { + ddr_clk: ddr { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL3>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; - clock-output-names = "ddr"; }; - mp_clk: mp_clk { + mp_clk: mp { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-div = <15>; clock-mult = <1>; - clock-output-names = "mp"; }; - cp_clk: cp_clk { + cp_clk: cp { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7794_CLK_PLL1>; #clock-cells = <0>; clock-div = <48>; clock-mult = <1>; - clock-output-names = "cp"; }; - acp_clk: acp_clk { + acp_clk: acp { compatible = "fixed-factor-clock"; clocks = <&extal_clk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "acp"; }; /* Gate clocks */ @@ -1082,16 +1125,19 @@ compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, - <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; + <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>, + <&hp_clk>, <&hp_clk>; #clock-cells = <1>; clock-indices = < R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 - R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1 + R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0 + R8A7794_CLK_IIC1 R8A7794_CLK_CMT1 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 >; clock-output-names = "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "cmt1", "usbdmac0", "usbdmac1"; + "mmcif0", "i2c6", "i2c7", + "cmt1", "usbdmac0", "usbdmac1"; }; mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -1137,20 +1183,22 @@ compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; + <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, + <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>, + <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, + <&hp_clk>, <&hp_clk>; #clock-cells = <1>; clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1 - R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD + R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1 + R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>; clock-output-names = "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", - "gpio1", "gpio0", "qspi_mod", + "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; mstp11_clks: mstp11_clks@e615099c { diff --git a/arch/arm/boot/dts/rk3036-evb.dts b/arch/arm/boot/dts/rk3036-evb.dts index b3d6ec87f615..8db9e9b197a2 100644 --- a/arch/arm/boot/dts/rk3036-evb.dts +++ b/arch/arm/boot/dts/rk3036-evb.dts @@ -45,6 +45,11 @@ / { model = "Rockchip RK3036 Evaluation board"; compatible = "rockchip,rk3036-evb", "rockchip,rk3036"; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; }; &emac { diff --git a/arch/arm/boot/dts/rk3036-kylin.dts b/arch/arm/boot/dts/rk3036-kylin.dts index 6251d109eff4..1df1557a46c3 100644 --- a/arch/arm/boot/dts/rk3036-kylin.dts +++ b/arch/arm/boot/dts/rk3036-kylin.dts @@ -46,6 +46,11 @@ model = "Rockchip RK3036 KylinBoard"; compatible = "rockchip,rk3036-kylin", "rockchip,rk3036"; + memory { + device_type = "memory"; + reg = <0x60000000 0x20000000>; + }; + leds: gpio-leds { compatible = "gpio-leds"; @@ -130,6 +135,10 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + &i2c1 { clock-frequency = <400000>; @@ -341,7 +350,6 @@ &sdio { status = "okay"; - broken-cd; bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; @@ -385,6 +393,14 @@ status = "okay"; }; +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + &pinctrl { leds { led_ctl: led-ctl { diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index d0f4bb7e1e50..843d2be2e4e9 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -63,11 +63,6 @@ spi = &spi; }; - memory { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -119,6 +114,11 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; + display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + timer { compatible = "arm,armv7-timer"; arm,cpu-registers-not-fw-configured; @@ -149,6 +149,36 @@ }; }; + vop: vop@10118000 { + compatible = "rockchip,rk3036-vop"; + reg = <0x10118000 0x19c>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + }; + }; + + vop_mmu: iommu@10118300 { + compatible = "rockchip,iommu"; + reg = <0x10118300 0x100>; + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vop_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@10139000 { compatible = "arm,gic-400"; interrupt-controller; @@ -237,7 +267,6 @@ compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x1021c000 0x4000>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; - broken-cd; bus-width = <8>; cap-mmc-highspeed; clock-frequency = <37500000>; @@ -297,6 +326,27 @@ status = "disabled"; }; + hdmi: hdmi@20034000 { + compatible = "rockchip,rk3036-inno-hdmi"; + reg = <0x20034000 0x4000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_HDMI>; + clock-names = "pclk"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_ctl>; + status = "disabled"; + + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + timer: timer@20044000 { compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>; @@ -644,6 +694,15 @@ }; }; + hdmi { + hdmi_ctl: hdmi-ctl { + rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>, + <1 9 RK_FUNC_1 &pcfg_pull_none>, + <1 10 RK_FUNC_1 &pcfg_pull_none>, + <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>, diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index 6d2a5b3a84a8..bc674ee206ec 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -42,6 +42,7 @@ */ /dts-v1/; +#include <dt-bindings/input/input.h> #include "rk3066a.dtsi" / { @@ -77,21 +78,19 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + power { gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */ - linux,code = <116>; + linux,code = <KEY_POWER>; label = "GPIO Key Power"; linux,input-type = <1>; wakeup-source; debounce-interval = <100>; }; - button@1 { + volume-down { gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ - linux,code = <104>; + linux,code = <KEY_VOLUMEDOWN>; label = "GPIO Key Vol-"; linux,input-type = <1>; debounce-interval = <100>; diff --git a/arch/arm/boot/dts/rk3066a-rayeager.dts b/arch/arm/boot/dts/rk3066a-rayeager.dts index 05533005a809..6e7f2187a0e3 100644 --- a/arch/arm/boot/dts/rk3066a-rayeager.dts +++ b/arch/arm/boot/dts/rk3066a-rayeager.dts @@ -41,6 +41,7 @@ */ /dts-v1/; +#include <dt-bindings/input/input.h> #include "rk3066a.dtsi" / { @@ -61,14 +62,12 @@ keys: gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + power { wakeup-source; gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; label = "GPIO Power"; - linux,code = <116>; + linux,code = <KEY_POWER>; pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; }; @@ -182,7 +181,6 @@ }; &emmc { - broken-cd; bus-width = <8>; cap-mmc-highspeed; disable-wp; @@ -348,7 +346,6 @@ }; &mmc1 { - broken-cd; bus-width = <4>; disable-wp; non-removable; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index cb0a552e0b18..c0ba86c3a2ab 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -169,7 +169,7 @@ clocks = <&cru PCLK_EFUSE>; clock-names = "pclk_efuse"; - cpu_leakage: cpu_leakage { + cpu_leakage: cpu_leakage@17 { reg = <0x17 0x1>; }; }; @@ -207,7 +207,7 @@ #size-cells = <0>; status = "disabled"; - usbphy0: usb-phy0 { + usbphy0: usb-phy@17c { #phy-cells = <0>; reg = <0x17c>; clocks = <&cru SCLK_OTGPHY0>; @@ -215,7 +215,7 @@ #clock-cells = <0>; }; - usbphy1: usb-phy1 { + usbphy1: usb-phy@188 { #phy-cells = <0>; reg = <0x188>; clocks = <&cru SCLK_OTGPHY1>; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 0b6924c97b6b..1da46d138029 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -41,6 +41,7 @@ */ /dts-v1/; +#include <dt-bindings/input/input.h> #include "rk3188.dtsi" / { @@ -54,13 +55,11 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; - button@0 { + power { gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = <KEY_POWER>; label = "GPIO Key Power"; linux,input-type = <1>; wakeup-source; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index 9271833958f9..31f81b265cef 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -154,7 +154,7 @@ clocks = <&cru PCLK_EFUSE>; clock-names = "pclk_efuse"; - cpu_leakage: cpu_leakage { + cpu_leakage: cpu_leakage@17 { reg = <0x17 0x1>; }; }; @@ -166,7 +166,7 @@ #size-cells = <0>; status = "disabled"; - usbphy0: usb-phy0 { + usbphy0: usb-phy@10c { #phy-cells = <0>; reg = <0x10c>; clocks = <&cru SCLK_OTGPHY0>; @@ -174,7 +174,7 @@ #clock-cells = <0>; }; - usbphy1: usb-phy1 { + usbphy1: usb-phy@11c { #phy-cells = <0>; reg = <0x11c>; clocks = <&cru SCLK_OTGPHY1>; diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts index e3898b810150..5956e8246abe 100644 --- a/arch/arm/boot/dts/rk3228-evb.dts +++ b/arch/arm/boot/dts/rk3228-evb.dts @@ -53,7 +53,6 @@ }; &emmc { - broken-cd; cap-mmc-highspeed; mmc-ddr-1_8v; disable-wp; @@ -61,6 +60,13 @@ status = "okay"; }; +&tsadc { + status = "okay"; + + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +}; + &uart2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk3228.dtsi index 4dae42a01509..e23a22e29155 100644 --- a/arch/arm/boot/dts/rk3228.dtsi +++ b/arch/arm/boot/dts/rk3228.dtsi @@ -43,6 +43,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3228-cru.h> +#include <dt-bindings/thermal/thermal.h> #include "skeleton.dtsi" / { @@ -69,6 +70,7 @@ /* KHz uV */ 816000 1000000 >; + #cooling-cells = <2>; /* min followed by max */ clock-latency = <40000>; clocks = <&cru ARMCLK>; }; @@ -185,6 +187,58 @@ status = "disabled"; }; + i2c0: i2c@11050000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11050000 0x1000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + i2c1: i2c@11060000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11060000 0x1000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c2: i2c@11070000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11070000 0x1000>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + i2c3: i2c@11080000 { + compatible = "rockchip,rk3228-i2c"; + reg = <0x11080000 0x1000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + pwm0: pwm@110b0000 { compatible = "rockchip,rk3288-pwm"; reg = <0x110b0000 0x10>; @@ -247,6 +301,63 @@ assigned-clock-rates = <594000000>; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@11150000 { + compatible = "rockchip,rk3228-tsadc"; + reg = <0x11150000 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + #thermal-sensor-cells = <0>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + emmc: dwmmc@30020000 { compatible = "rockchip,rk3288-dw-mshc"; reg = <0x30020000 0x4000>; @@ -370,6 +481,34 @@ }; }; + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>, + <0 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>, + <0 3 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>, + <2 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>, + <0 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + pwm0 { pwm0_pin: pwm0-pin { rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>; @@ -394,6 +533,16 @@ }; }; + tsadc { + otp_gpio: otp-gpio { + rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>, diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 78d47f7d2938..963365d12208 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -38,6 +38,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/input/input.h> #include <dt-bindings/pwm/pwm.h> #include "rk3288.dtsi" @@ -98,16 +99,14 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - button@0 { + power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = <KEY_POWER>; label = "GPIO Key Power"; linux,input-type = <1>; wakeup-source; @@ -172,7 +171,6 @@ }; &emmc { - broken-cd; bus-width = <8>; cap-mmc-highspeed; disable-wp; diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi index 98c586a43c73..d6cf9ada13c9 100644 --- a/arch/arm/boot/dts/rk3288-firefly.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly.dtsi @@ -40,6 +40,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/input/input.h> #include "rk3288.dtsi" / { @@ -87,14 +88,12 @@ keys: gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - button@0 { + power { wakeup-source; gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; label = "GPIO Power"; - linux,code = <116>; + linux,code = <KEY_POWER>; pinctrl-names = "default"; pinctrl-0 = <&pwr_key>; }; @@ -208,7 +207,6 @@ }; &emmc { - broken-cd; bus-width = <8>; cap-mmc-highspeed; disable-wp; @@ -509,7 +507,6 @@ }; &sdio0 { - broken-cd; bus-width = <4>; disable-wp; non-removable; diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts new file mode 100644 index 000000000000..8643103d8cd8 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-miqi.dts @@ -0,0 +1,472 @@ +/* + * Copyright (c) 2016 Heiko Stuebner <heiko@sntech.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include "rk3288.dtsi" + +/ { + model = "mqmaker MiQi"; + compatible = "mqmaker,miqi", "rockchip,rk3288"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + io_domains: io-domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + + audio-supply = <&vcca_33>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_18>; + }; + + leds { + compatible = "gpio-leds"; + + work { + gpios = <&gpio7 4 GPIO_ACTIVE_LOW>; + label = "miqi:green:user"; + linux,default-trigger = "default-on"; + pinctrl-names = "default"; + pinctrl-0 = <&led_ctl>; + }; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-ramp-delay = <8000>; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_vsel>; + system-power-controller; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_sys>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "vcc_ddr"; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "vcc_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_18: REG7 { + regulator-name = "vcca_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcca_33: REG8 { + regulator-name = "vcca_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_lan: REG9 { + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_10: REG10 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + act8846 { + pmic_int: pmic-int { + rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_sleep: pmic-sleep { + rockchip,pins = <0 0 RK_FUNC_GPIO &pcfg_output_low>; + }; + + pmic_vsel: pmic-vsel { + rockchip,pins = <7 1 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + leds { + led_ctl: led-ctl { + rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + /* + * The otg controller is the only system power source, + * so needs to always stay in device mode. + */ + dr_mode = "peripheral"; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index 2ff9689d2e1b..720717bb3614 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -41,7 +41,7 @@ */ /dts-v1/; - +#include <dt-bindings/input/input.h> #include "rk3288.dtsi" / { @@ -62,16 +62,14 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - button@0 { + power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = <KEY_POWER>; label = "GPIO Key Power"; linux,input-type = <1>; wakeup-source; @@ -162,7 +160,6 @@ }; &emmc { - broken-cd; bus-width = <8>; cap-mmc-highspeed; disable-wp; diff --git a/arch/arm/boot/dts/rk3288-r89.dts b/arch/arm/boot/dts/rk3288-r89.dts index 510a1d0d7abb..4b8a8adb243c 100644 --- a/arch/arm/boot/dts/rk3288-r89.dts +++ b/arch/arm/boot/dts/rk3288-r89.dts @@ -41,6 +41,7 @@ */ /dts-v1/; +#include <dt-bindings/input/input.h> #include <dt-bindings/pwm/pwm.h> #include "rk3288.dtsi" @@ -61,16 +62,14 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; autorepeat; pinctrl-names = "default"; pinctrl-0 = <&pwrbtn>; - button@0 { + power { gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - linux,code = <116>; + linux,code = <KEY_POWER>; label = "GPIO Key Power"; linux,input-type = <1>; wakeup-source; diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi index 610769d99522..2958c36d12a0 100644 --- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi @@ -54,6 +54,50 @@ i2c20 = &i2c_tunnel; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + backlight-boot-off; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm0 0 1000000 0>; + pwm-delay-us = <10000>; + }; + gpio-charger { compatible = "gpio-charger"; charger-type = "mains"; @@ -62,6 +106,21 @@ pinctrl-0 = <&ac_present_ap>; }; + panel: panel { + compatible ="innolux,n116bge", "simple-panel"; + status = "okay"; + power-supply = <&vcc33_lcd>; + backlight = <&backlight>; + + ports { + panel_in: port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; + /* A non-regulated voltage from power supply or battery */ vccsys: vccsys { compatible = "regulator-fixed"; @@ -103,6 +162,29 @@ }; }; +&edp { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + edp_out_panel: endpoint { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + &gpio_keys { pinctrl-0 = <&pwr_key_l &ap_lid_int_l>; lid { @@ -115,6 +197,10 @@ }; }; +&pwm0 { + status = "okay"; +}; + &rk808 { vcc11-supply = <&vcc_5v>; @@ -168,6 +254,14 @@ }; }; +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + &pinctrl { pinctrl-0 = < /* Common for sleep and wake, but no owners */ @@ -184,6 +278,12 @@ &suspend_l_sleep >; + backlight { + bl_en: bl-en { + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + buttons { ap_lid_int_l: ap-lid-int-l { rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts index c2f52cfb4d06..3748abf562b1 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts @@ -61,6 +61,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lcd_enable_h>; regulator-name = "panel_regulator"; + startup-delay-us = <100000>; vin-supply = <&vcc33_sys>; }; @@ -88,6 +89,48 @@ }; }; +&backlight { + /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */ + brightness-levels = < + 0 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + power-supply = <&backlight_regulator>; +}; + +&panel { + power-supply = <&panel_regulator>; +}; + &rk808 { pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; @@ -142,12 +185,6 @@ }; }; - edp { - edp_hpd: edp_hpd { - rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; - }; - }; - hdmi { vcc50_hdmi_en: vcc50-hdmi-en { rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; diff --git a/arch/arm/boot/dts/rk3288-veyron-jerry.dts b/arch/arm/boot/dts/rk3288-veyron-jerry.dts index 60bd6e91e308..f6b2eaaebb9a 100644 --- a/arch/arm/boot/dts/rk3288-veyron-jerry.dts +++ b/arch/arm/boot/dts/rk3288-veyron-jerry.dts @@ -60,6 +60,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lcd_enable_h>; regulator-name = "panel_regulator"; + startup-delay-us = <100000>; vin-supply = <&vcc33_sys>; }; @@ -87,6 +88,14 @@ }; }; +&backlight { + power-supply = <&backlight_regulator>; +}; + +&panel { + power-supply= <&panel_regulator>; +}; + &rk808 { pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; diff --git a/arch/arm/boot/dts/rk3288-veyron-minnie.dts b/arch/arm/boot/dts/rk3288-veyron-minnie.dts index 699beb0a9481..f72d616d1bf8 100644 --- a/arch/arm/boot/dts/rk3288-veyron-minnie.dts +++ b/arch/arm/boot/dts/rk3288-veyron-minnie.dts @@ -70,6 +70,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lcd_enable_h>; regulator-name = "panel_regulator"; + startup-delay-us = <100000>; vin-supply = <&vcc33_sys>; }; @@ -86,6 +87,44 @@ }; }; +&backlight { + /* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */ + brightness-levels = < + 0 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + power-supply = <&backlight_regulator>; +}; + &emmc { /delete-property/mmc-hs200-1_8v; }; @@ -135,6 +174,11 @@ }; }; +&panel { + compatible = "auo,b101ean01", "simple-panel"; + power-supply= <&panel_regulator>; +}; + &rk808 { pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; diff --git a/arch/arm/boot/dts/rk3288-veyron-pinky.dts b/arch/arm/boot/dts/rk3288-veyron-pinky.dts index 94b56e33d947..d44351ec2333 100644 --- a/arch/arm/boot/dts/rk3288-veyron-pinky.dts +++ b/arch/arm/boot/dts/rk3288-veyron-pinky.dts @@ -65,6 +65,13 @@ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>; }; +&edp { + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + + force-hpd; +}; + &gpio_keys { pinctrl-0 = <&pwr_key_h &ap_lid_int_l>; diff --git a/arch/arm/boot/dts/rk3288-veyron-speedy.dts b/arch/arm/boot/dts/rk3288-veyron-speedy.dts index b34a7b5b3f62..a0d033f6fe52 100644 --- a/arch/arm/boot/dts/rk3288-veyron-speedy.dts +++ b/arch/arm/boot/dts/rk3288-veyron-speedy.dts @@ -61,6 +61,7 @@ pinctrl-names = "default"; pinctrl-0 = <&lcd_enable_h>; regulator-name = "panel_regulator"; + startup-delay-us = <100000>; vin-supply = <&vcc33_sys>; }; @@ -88,6 +89,10 @@ }; }; +&backlight { + power-supply = <&backlight_regulator>; +}; + &cpu_alert0 { temperature = <65000>; }; @@ -96,6 +101,17 @@ temperature = <70000>; }; +&edp { + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; + + force-hpd; +}; + +&panel { + power-supply= <&panel_regulator>; +}; + &rk808 { pinctrl-names = "default"; pinctrl-0 = <&pmic_int_l>; diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 412809c60d01..b2557bf5a58f 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -141,12 +141,27 @@ &cpu0 { cpu0-supply = <&vdd_cpu>; + operating-points = < + /* KHz uV */ + 1800000 1400000 + 1704000 1350000 + 1608000 1300000 + 1512000 1250000 + 1416000 1200000 + 1200000 1100000 + 1008000 1050000 + 816000 1000000 + 696000 950000 + 600000 900000 + 408000 900000 + 216000 900000 + 126000 900000 + >; }; &emmc { status = "okay"; - broken-cd; bus-width = <8>; cap-mmc-highspeed; rockchip,default-sample-phase = <158>; @@ -347,7 +362,6 @@ &sdio0 { status = "okay"; - broken-cd; bus-width = <4>; cap-sd-highspeed; cap-sdio-irq; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 31f7e20ef418..3b44ef3cff12 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -445,7 +445,78 @@ }; thermal-zones { - #include "rk3288-thermal.dtsi" + reserve_thermal: reserve_thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + }; + + cpu_thermal: cpu_thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT 6>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu_thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 2>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; }; tsadc: tsadc@ff280000 { @@ -659,7 +730,7 @@ * *_HDMI HDMI * *_MIPI_* MIPI */ - pd_vio { + pd_vio@RK3288_PD_VIO { reg = <RK3288_PD_VIO>; clocks = <&cru ACLK_IEP>, <&cru ACLK_ISP>, @@ -692,7 +763,7 @@ * Note: The following 3 are HEVC(H.265) clocks, * and on the ACLK_HEVC_NIU (NOC). */ - pd_hevc { + pd_hevc@RK3288_PD_HEVC { reg = <RK3288_PD_HEVC>; clocks = <&cru ACLK_HEVC>, <&cru SCLK_HEVC_CABAC>, @@ -704,7 +775,7 @@ * (video endecoder & decoder) clocks that on the * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC). */ - pd_video { + pd_video@RK3288_PD_VIDEO { reg = <RK3288_PD_VIDEO>; clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; @@ -714,7 +785,7 @@ * Note: ACLK_GPU is the GPU clock, * and on the ACLK_GPU_NIU (NOC). */ - pd_gpu { + pd_gpu@RK3288_PD_GPU { reg = <RK3288_PD_GPU>; clocks = <&cru ACLK_GPU>; }; @@ -745,8 +816,16 @@ }; grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon"; + compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; reg = <0xff770000 0x1000>; + + edp_phy: edp-phy { + compatible = "rockchip,rk3288-dp-phy"; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + #phy-cells = <0>; + status = "disabled"; + }; }; wdt: watchdog@ff800000 { @@ -765,7 +844,7 @@ clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>; dmas = <&dmac_bus_s 3>; dma-names = "tx"; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&spdif_tx>; rockchip,grf = <&grf>; @@ -775,7 +854,7 @@ i2s: i2s@ff890000 { compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; reg = <0xff890000 0x10000>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; @@ -821,6 +900,12 @@ reg = <0>; remote-endpoint = <&hdmi_in_vopb>; }; + + vopb_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopb>; + }; + vopb_out_mipi: endpoint@2 { reg = <2>; remote-endpoint = <&mipi_in_vopb>; @@ -858,6 +943,12 @@ reg = <0>; remote-endpoint = <&hdmi_in_vopl>; }; + + vopl_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopl>; + }; + vopl_out_mipi: endpoint@2 { reg = <2>; remote-endpoint = <&mipi_in_vopl>; @@ -878,19 +969,16 @@ mipi_dsi: mipi@ff960000 { compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"; reg = <0xff960000 0x4000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>; clock-names = "ref", "pclk"; + power-domains = <&power RK3288_PD_VIO>; rockchip,grf = <&grf>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; ports { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - mipi_in: port { #address-cells = <1>; #size-cells = <0>; @@ -906,6 +994,38 @@ }; }; + edp: dp@ff970000 { + compatible = "rockchip,rk3288-dp"; + reg = <0xff970000 0x4000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>; + clock-names = "dp", "pclk"; + phys = <&edp_phy>; + phy-names = "dp"; + resets = <&cru SRST_EDP>; + reset-names = "dp"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + hdmi: hdmi@ff980000 { compatible = "rockchip,rk3288-dw-hdmi"; reg = <0xff980000 0x20000>; @@ -966,7 +1086,7 @@ #size-cells = <0>; status = "disabled"; - usbphy0: usb-phy0 { + usbphy0: usb-phy@320 { #phy-cells = <0>; reg = <0x320>; clocks = <&cru SCLK_OTGPHY0>; @@ -974,7 +1094,7 @@ #clock-cells = <0>; }; - usbphy1: usb-phy1 { + usbphy1: usb-phy@334 { #phy-cells = <0>; reg = <0x334>; clocks = <&cru SCLK_OTGPHY1>; @@ -982,7 +1102,7 @@ #clock-cells = <0>; }; - usbphy2: usb-phy2 { + usbphy2: usb-phy@348 { #phy-cells = <0>; reg = <0x348>; clocks = <&cru SCLK_OTGPHY2>; @@ -1158,6 +1278,12 @@ }; }; + edp { + edp_hpd: edp-hpd { + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>, diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 54fcc3fc82e2..9eb6aff3e38f 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -197,7 +197,7 @@ display-timings { native-mode = <&timing0>; - timing0: timing@0 { + timing0: timing { /* 800x480@60Hz */ clock-frequency = <24373920>; hactive = <800>; diff --git a/arch/arm/boot/dts/sama5d2-pinfunc.h b/arch/arm/boot/dts/sama5d2-pinfunc.h index b0c912feaa2f..8a394f336003 100644 --- a/arch/arm/boot/dts/sama5d2-pinfunc.h +++ b/arch/arm/boot/dts/sama5d2-pinfunc.h @@ -837,8 +837,8 @@ #define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) #define PIN_PD24 120 #define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) -#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD23, 1, 2) -#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD23, 3, 3) +#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD24, 1, 2) +#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD24, 3, 3) #define PIN_PD25 121 #define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) #define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 9817090c1b73..2827e7ab5ebc 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -319,6 +319,32 @@ #size-cells = <1>; ranges; + hlcdc: hlcdc@f0000000 { + compatible = "atmel,sama5d2-hlcdc"; + reg = <0xf0000000 0x2000>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + status = "disabled"; + + hlcdc-display-controller { + compatible = "atmel,hlcdc-display-controller"; + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + }; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + #pwm-cells = <3>; + }; + }; + ramc0: ramc@f000c000 { compatible = "atmel,sama5d3-ddramc"; reg = <0xf000c000 0x200>; @@ -973,6 +999,11 @@ status = "disabled"; }; + sfr: sfr@f8030000 { + compatible = "atmel,sama5d2-sfr", "syscon"; + reg = <0xf8030000 0x98>; + }; + flx0: flexcom@f8034000 { compatible = "atmel,sama5d2-flexcom"; reg = <0xf8034000 0x200>; @@ -999,6 +1030,15 @@ clocks = <&clk32k>; }; + shdwc@f8048010 { + compatible = "atmel,sama5d2-shdwc"; + reg = <0xf8048010 0x10>; + clocks = <&clk32k>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + }; + pit: timer@f8048030 { compatible = "atmel,at91sam9260-pit"; reg = <0xf8048030 0x10>; @@ -1010,6 +1050,7 @@ compatible = "atmel,sama5d4-wdt"; reg = <0xf8048040 0x10>; interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; status = "disabled"; }; @@ -1127,6 +1168,13 @@ status = "disabled"; }; + trng@fc01c000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xfc01c000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&trng_clk>; + }; + aic: interrupt-controller@fc020000 { #interrupt-cells = <3>; compatible = "atmel,sama5d2-aic"; @@ -1193,6 +1241,11 @@ clock-names = "tdes_clk"; status = "okay"; }; + + chipid@fc069000 { + compatible = "atmel,sama5d2-chipid"; + reg = <0xfc069000 0x8>; + }; }; }; }; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index a53279160f98..36301bd9a14a 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -426,6 +426,13 @@ clock-names = "tdes_clk"; }; + trng@f8040000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xf8040000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&trng_clk>; + }; + dma0: dma-controller@ffffe600 { compatible = "atmel,at91sam9g45-dma"; reg = <0xffffe600 0x200>; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi index db1151c18466..4e2cc30d6615 100644 --- a/arch/arm/boot/dts/sama5d4.dtsi +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -1202,6 +1202,13 @@ status = "disabled"; }; + trng@fc030000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xfc030000 0x100>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&trng_clk>; + }; + adc0: adc@fc034000 { compatible = "atmel,at91sam9x5-adc"; reg = <0xfc034000 0x100>; @@ -1302,6 +1309,7 @@ watchdog@fc068640 { compatible = "atmel,sama5d4-wdt"; reg = <0xfc068640 0x10>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; clocks = <&clk32k>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts index aa8bae3b8fcf..c2d8a080e392 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts @@ -149,6 +149,13 @@ label = "SW1"; wakeup-source; }; + + wakeup-key { + gpios = <&pfc 159 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + label = "NMI"; + wakeup-source; + }; }; sound { @@ -329,41 +336,41 @@ &pfc { i2c3_pins: i2c3 { - renesas,groups = "i2c3_1"; - renesas,function = "i2c3"; + groups = "i2c3_1"; + function = "i2c3"; }; mmcif_pins: mmc { mux { - renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0"; - renesas,function = "mmc0"; + groups = "mmc0_data8_0", "mmc0_ctrl_0"; + function = "mmc0"; }; cfg { - renesas,groups = "mmc0_data8_0"; - renesas,pins = "PORT279"; + groups = "mmc0_data8_0"; + pins = "PORT279"; bias-pull-up; }; }; scifa4_pins: serial4 { - renesas,groups = "scifa4_data", "scifa4_ctrl"; - renesas,function = "scifa4"; + groups = "scifa4_data", "scifa4_ctrl"; + function = "scifa4"; }; sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; - renesas,function = "sdhi0"; + groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp"; + function = "sdhi0"; }; sdhi2_pins: sd2 { - renesas,groups = "sdhi2_data4", "sdhi2_ctrl"; - renesas,function = "sdhi2"; + groups = "sdhi2_data4", "sdhi2_ctrl"; + function = "sdhi2"; }; fsia_pins: sounda { - renesas,groups = "fsia_mclk_in", "fsia_sclk_in", - "fsia_data_in", "fsia_data_out"; - renesas,function = "fsia"; + groups = "fsia_mclk_in", "fsia_sclk_in", + "fsia_data_in", "fsia_data_out"; + function = "fsia"; }; }; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index bf825ca4f6f7..c4f434cdec60 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -43,7 +43,7 @@ timer@f0000600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xf0000600 0x20>; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; clocks = <&twd_clk>; }; @@ -602,39 +602,33 @@ ranges; /* External root clocks */ - extalr_clk: extalr_clk { + extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; - clock-output-names = "extalr"; }; - extal1_clk: extal1_clk { + extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <26000000>; - clock-output-names = "extal1"; }; - extal2_clk: extal2_clk { + extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "extal2"; }; - extcki_clk: extcki_clk { + extcki_clk: extcki { compatible = "fixed-clock"; #clock-cells = <0>; - clock-output-names = "extcki"; }; - fsiack_clk: fsiack_clk { + fsiack_clk: fsiack { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fsiack"; }; - fsibck_clk: fsibck_clk { + fsibck_clk: fsibck { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; - clock-output-names = "fsibck"; }; /* Special CPG clocks */ @@ -650,7 +644,7 @@ }; /* Variable factor clocks (DIV6) */ - vclk1_clk: vclk1_clk@e6150008 { + vclk1_clk: vclk1@e6150008 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150008 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, @@ -658,9 +652,8 @@ <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, <0>; #clock-cells = <0>; - clock-output-names = "vclk1"; }; - vclk2_clk: vclk2_clk@e615000c { + vclk2_clk: vclk2@e615000c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615000c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, @@ -668,9 +661,8 @@ <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, <0>; #clock-cells = <0>; - clock-output-names = "vclk2"; }; - vclk3_clk: vclk3_clk@e615001c { + vclk3_clk: vclk3@e615001c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615001c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, @@ -678,7 +670,6 @@ <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, <0>; #clock-cells = <0>; - clock-output-names = "vclk3"; }; zb_clk: zb_clk@e6150010 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; @@ -688,168 +679,148 @@ #clock-cells = <0>; clock-output-names = "zb"; }; - flctl_clk: flctl_clk@e6150014 { + flctl_clk: flctlck@e6150014 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150014 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "flctlck"; }; - sdhi0_clk: sdhi0_clk@e6150074 { + sdhi0_clk: sdhi0ck@e6150074 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150074 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div13_clk>, <0>; #clock-cells = <0>; - clock-output-names = "sdhi0ck"; }; - sdhi1_clk: sdhi1_clk@e6150078 { + sdhi1_clk: sdhi1ck@e6150078 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150078 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div13_clk>, <0>; #clock-cells = <0>; - clock-output-names = "sdhi1ck"; }; - sdhi2_clk: sdhi2_clk@e615007c { + sdhi2_clk: sdhi2ck@e615007c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615007c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div13_clk>, <0>; #clock-cells = <0>; - clock-output-names = "sdhi2ck"; }; - fsia_clk: fsia_clk@e6150018 { + fsia_clk: fsia@e6150018 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150018 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&fsiack_clk>, <&fsiack_clk>; #clock-cells = <0>; - clock-output-names = "fsia"; }; - fsib_clk: fsib_clk@e6150090 { + fsib_clk: fsib@e6150090 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150090 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&fsibck_clk>, <&fsibck_clk>; #clock-cells = <0>; - clock-output-names = "fsib"; }; - sub_clk: sub_clk@e6150080 { + sub_clk: sub@e6150080 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150080 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "sub"; }; - spua_clk: spua_clk@e6150084 { + spua_clk: spua@e6150084 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150084 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "spua"; }; - spuv_clk: spuv_clk@e6150094 { + spuv_clk: spuv@e6150094 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150094 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&extal2_clk>, <&extal2_clk>; #clock-cells = <0>; - clock-output-names = "spuv"; }; - msu_clk: msu_clk@e6150088 { + msu_clk: msu@e6150088 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150088 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "msu"; }; - hsi_clk: hsi_clk@e615008c { + hsi_clk: hsi@e615008c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615008c 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&pll1_div7_clk>, <0>; #clock-cells = <0>; - clock-output-names = "hsi"; }; - mfg1_clk: mfg1_clk@e6150098 { + mfg1_clk: mfg1@e6150098 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150098 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "mfg1"; }; - mfg2_clk: mfg2_clk@e615009c { + mfg2_clk: mfg2@e615009c { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe615009c 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "mfg2"; }; - dsit_clk: dsit_clk@e6150060 { + dsit_clk: dsit@e6150060 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150060 4>; clocks = <&pll1_div2_clk>, <0>, <&cpg_clocks SH73A0_CLK_PLL2>, <0>; #clock-cells = <0>; - clock-output-names = "dsit"; }; - dsi0p_clk: dsi0p_clk@e6150064 { + dsi0p_clk: dsi0pck@e6150064 { compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; reg = <0xe6150064 4>; clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, <&extcki_clk>, <0>, <0>, <0>; #clock-cells = <0>; - clock-output-names = "dsi0pck"; }; /* Fixed factor clocks */ - main_div2_clk: main_div2_clk { + main_div2_clk: main_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_MAIN>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "main_div2"; }; - pll1_div2_clk: pll1_div2_clk { + pll1_div2_clk: pll1_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_PLL1>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; - clock-output-names = "pll1_div2"; }; - pll1_div7_clk: pll1_div7_clk { + pll1_div7_clk: pll1_div7 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_PLL1>; #clock-cells = <0>; clock-div = <7>; clock-mult = <1>; - clock-output-names = "pll1_div7"; }; - pll1_div13_clk: pll1_div13_clk { + pll1_div13_clk: pll1_div13 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_PLL1>; #clock-cells = <0>; clock-div = <13>; clock-mult = <1>; - clock-output-names = "pll1_div13"; }; - twd_clk: twd_clk { + twd_clk: twd { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks SH73A0_CLK_Z>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; - clock-output-names = "twd"; }; /* Gate clocks */ diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index b89cbde3b289..9f48141270b8 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -831,6 +831,8 @@ interrupts = <0 125 4>; clocks = <&usb_mp_clk>; clock-names = "otg"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -842,6 +844,8 @@ interrupts = <0 128 4>; clocks = <&usb_mp_clk>; clock-names = "otg"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 1c5e139e4d05..17e81dc9213e 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -78,10 +78,13 @@ <0 87 IRQ_TYPE_LEVEL_HIGH>, <0 88 IRQ_TYPE_LEVEL_HIGH>, <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; + <0 90 IRQ_TYPE_LEVEL_HIGH>, + <0 91 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + clocks = <&l4_main_clk>; + clock-names = "apb_pclk"; }; }; @@ -362,6 +365,7 @@ compatible = "altr,socfpga-a10-gate-clk"; clocks = <&sdmmc_free_clk>; clk-gate = <0xC8 5>; + clk-phase = <0 135>; }; qspi_clk: qspi_clk { @@ -589,7 +593,7 @@ reg = <0xff808000 0x1000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; fifo-depth = <0x400>; - clocks = <&l4_mp_clk>, <&sdmmc_free_clk>; + clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; status = "disabled"; }; @@ -599,6 +603,26 @@ reg = <0xffe00000 0x40000>; }; + eccmgr: eccmgr@ffd06000 { + compatible = "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 0 IRQ_TYPE_LEVEL_HIGH>; + ranges; + + l2-ecc@ffd06010 { + compatible = "altr,socfpga-a10-l2-ecc"; + reg = <0xffd06010 0x4>; + }; + + ocram-ecc@ff8c3000 { + compatible = "altr,socfpga-a10-ocram-ecc"; + reg = <0xff8c3000 0x400>; + }; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; @@ -689,6 +713,8 @@ interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usb_clk>; clock-names = "otg"; + resets = <&rst USB0_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; @@ -700,6 +726,8 @@ interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; clocks = <&usb_clk>; clock-names = "otg"; + resets = <&rst USB1_RESET>; + reset-names = "dwc2"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts index dbbb751ac1ba..8a7dfa473e98 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts @@ -21,6 +21,7 @@ &mmc { status = "okay"; num-slots = <1>; + cap-sd-highspeed; broken-cd; bus-width = <4>; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 06db951e06f8..a05e3df23103 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -38,12 +38,6 @@ cap-sd-highspeed; }; - ethernet@ff702000 { - phy-mode = "rgmii"; - phy-addr = <0xffffffff>; /* probe for phy addr */ - status = "okay"; - }; - sysmgr@ffd08000 { cpu1-start-addr = <0xffd080c4>; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index b61f22f9ac9f..02e22f554ef0 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -39,6 +39,90 @@ ethernet0 = &gmac1; }; + leds { + compatible = "gpio-leds"; + + hps_led0 { + label = "hps:blue:led0"; + gpios = <&portb 24 0>; /* HPS_GPIO53 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led1 { + label = "hps:blue:led1"; + gpios = <&portb 25 0>; /* HPS_GPIO54 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led2 { + label = "hps:blue:led2"; + gpios = <&portb 26 0>; /* HPS_GPIO55 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led3 { + label = "hps:blue:led3"; + gpios = <&portb 27 0>; /* HPS_GPIO56 */ + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + hps_sw0 { + label = "hps_sw0"; + gpios = <&portc 20 0>; /* HPS_GPI7 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x0>; /* SW_LID */ + }; + + hps_sw1 { + label = "hps_sw1"; + gpios = <&portc 19 0>; /* HPS_GPI6 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0x5>; /* SW_DOCK */ + }; + + hps_sw2 { + label = "hps_sw2"; + gpios = <&portc 18 0>; /* HPS_GPI5 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0xa>; /* SW_KEYPAD_SLIDE */ + }; + + hps_sw3 { + label = "hps_sw3"; + gpios = <&portc 17 0>; /* HPS_GPI4 */ + linux,input-type = <5>; /* EV_SW */ + linux,code = <0xc>; /* SW_ROTATE_LOCK */ + }; + + hps_hkey0 { + label = "hps_hkey0"; + gpios = <&portc 21 1>; /* HPS_GPI8 */ + linux,code = <187>; /* KEY_F17 */ + }; + + hps_hkey1 { + label = "hps_hkey1"; + gpios = <&portc 22 1>; /* HPS_GPI9 */ + linux,code = <188>; /* KEY_F18 */ + }; + + hps_hkey2 { + label = "hps_hkey2"; + gpios = <&portc 23 1>; /* HPS_GPI10 */ + linux,code = <189>; /* KEY_F19 */ + }; + + hps_hkey3 { + label = "hps_hkey3"; + gpios = <&portc 24 1>; /* HPS_GPI11 */ + linux,code = <190>; /* KEY_F20 */ + }; + }; + regulator_3_3v: vcc3p3-regulator { compatible = "regulator-fixed"; regulator-name = "VCC3P3"; @@ -61,7 +145,15 @@ rxc-skew-ps = <2000>; }; -&gpio2 { +&gpio0 { /* GPIO 0..29 */ + status = "okay"; +}; + +&gpio1 { /* GPIO 30..57 */ + status = "okay"; +}; + +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts index 019dd2fea208..e1a61f20873f 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts @@ -36,6 +36,7 @@ }; &gmac1 { + phy-mode = "rgmii"; status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts new file mode 100644 index 000000000000..a3601e4c0a2e --- /dev/null +++ b/arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2015 Marek Vasut <marex@denx.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "socfpga_cyclone5.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "samtec VIN|ING FPGA"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + aliases { + /* + * This allow the ethaddr uboot environment variable contents + * to be added to the gmac1 device tree blob. + */ + ethernet0 = &gmac1; + }; + + leds { + compatible = "gpio-leds"; + + hps_led0 { + label = "hps:green:led0"; /* ALIVE_LED_GR */ + gpios = <&portb 19 0>; /* HPS_GPIO48 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led1 { + label = "hps:red:led0"; /* ALIVE_LED_RD */ + gpios = <&portb 24 0>; /* HPS_GPIO53 */ + linux,default-trigger = "none"; + }; + + hps_led2 { + label = "hps:green:led1"; /* LINK2HOST_LED_GR */ + gpios = <&portb 25 0>; /* HPS_GPIO54 */ + linux,default-trigger = "heartbeat"; + }; + + hps_led3 { + label = "hps:red:led1"; /* LINK2HOST_LED_RD */ + gpios = <&portc 7 0>; /* HPS_GPIO65 */ + linux,default-trigger = "none"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + hps_temp0 { + label = "BTN_0"; /* TEMP_OS */ + gpios = <&portc 18 GPIO_ACTIVE_LOW>; /* HPS_GPIO60 */ + linux,code = <BTN_0>; + }; + + hps_hkey0 { + label = "BTN_1"; /* DIS_PWR */ + gpios = <&portc 19 GPIO_ACTIVE_LOW>; /* HPS_GPIO61 */ + linux,code = <BTN_1>; + }; + + hps_hkey1 { + label = "hps_hkey1"; /* POWER_DOWN */ + gpios = <&portc 20 GPIO_ACTIVE_LOW>; /* HPS_GPIO62 */ + linux,code = <KEY_POWER>; + }; + }; + + regulator-usb-nrst { + compatible = "regulator-fixed"; + regulator-name = "usb_nrst"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portb 5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <70000>; + enable-active-high; + regulator-always-on; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + snps,reset-gpio = <&porta 0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <10000 10000 10000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@1 { + reg = <1>; + rxd0-skew-ps = <0>; + rxd1-skew-ps = <0>; + rxd2-skew-ps = <0>; + rxd3-skew-ps = <0>; + txen-skew-ps = <0>; + txc-skew-ps = <2600>; + rxdv-skew-ps = <0>; + rxc-skew-ps = <2000>; + }; + }; +}; + +&gpio0 { /* GPIO 0..29 */ + status = "okay"; +}; + +&gpio1 { /* GPIO 30..57 */ + status = "okay"; +}; + +&gpio2 { /* GPIO 58..66 (HLGPI 0..13 at offset 13) */ + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gpio: pca9557@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; + + temp: lm75@48 { + compatible = "lm75"; + reg = <0x48>; + }; + + at24@50 { + compatible = "at24,24c01"; + pagesize = <8>; + reg = <0x50>; + }; + + i2cswitch@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + eeprom@51 { + compatible = "at,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + eeprom@51 { + compatible = "at,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + eeprom@51 { + compatible = "at,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + eeprom@51 { + compatible = "at,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + eeprom@51 { + compatible = "at,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + eeprom@51 { + compatible = "at,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + eeprom@51 { + compatible = "at,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + eeprom@51 { + compatible = "at,24c01"; + pagesize = <8>; + reg = <0x51>; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <8>; + reg = <0x50>; + }; +}; + +&usb0 { + dr_mode = "host"; + status = "okay"; +}; + +&usb1 { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ste-ccu9540.dts b/arch/arm/boot/dts/ste-ccu9540.dts index c8b815819cfe..b3b9bb8e1aa8 100644 --- a/arch/arm/boot/dts/ste-ccu9540.dts +++ b/arch/arm/boot/dts/ste-ccu9540.dts @@ -49,7 +49,7 @@ cap-mmc-highspeed; vmmc-supply = <&ab8500_ldo_aux3_reg>; - cd-gpios = <&gpio7 6 0x4>; // 230 + cd-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>; // 230 cd-inverted; status = "okay"; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 341f5b7ed242..6ae56838bd3a 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -10,8 +10,10 @@ */ #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mfd/dbx500-prcmu.h> #include <dt-bindings/arm/ux500_pm_domains.h> +#include <dt-bindings/gpio/gpio.h> #include "skeleton.dtsi" / { @@ -203,14 +205,14 @@ L2: l2-cache { compatible = "arm,pl310-cache"; reg = <0xa0412000 0x1000>; - interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; cache-unified; cache-level = <2>; }; pmu { compatible = "arm,cortex-a9-pmu"; - interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; }; pm_domains: pm_domains0 { @@ -253,7 +255,7 @@ /* Nomadik System Timer */ compatible = "st,nomadik-mtu"; reg = <0xa03c6000 0x1000>; - interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>; clock-names = "timclk", "apb_pclk"; @@ -262,7 +264,7 @@ timer@a0410600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xa0410600 0x20>; - interrupts = <1 13 0x304>; /* IRQ level high per-CPU */ + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&smp_twd_clk>; }; @@ -270,14 +272,14 @@ watchdog@a0410620 { compatible = "arm,cortex-a9-twd-wdt"; reg = <0xa0410620 0x20>; - interrupts = <1 14 0x304>; + interrupts = <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&smp_twd_clk>; }; rtc@80154000 { compatible = "arm,rtc-pl031", "arm,primecell"; reg = <0x80154000 0x1000>; - interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rtc_clk>; clock-names = "apb_pclk"; @@ -287,7 +289,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8012e000 0x80>; - interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -302,7 +304,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8012e080 0x80>; - interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -317,7 +319,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8000e000 0x80>; - interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -332,7 +334,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8000e080 0x80>; - interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -347,7 +349,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8000e100 0x80>; - interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -362,7 +364,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8000e180 0x80>; - interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -377,7 +379,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8011e000 0x80>; - interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -392,7 +394,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0x8011e080 0x80>; - interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -407,7 +409,7 @@ compatible = "stericsson,db8500-gpio", "st,nomadik-gpio"; reg = <0xa03fe000 0x80>; - interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; st,supports-sleepmode; @@ -429,7 +431,7 @@ usb_per5@a03e0000 { compatible = "stericsson,db8500-musb"; reg = <0xa03e0000 0x10000>; - interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "mc"; dr_mode = "otg"; @@ -467,7 +469,7 @@ compatible = "stericsson,db8500-dma40", "stericsson,dma40"; reg = <0x801C0000 0x1000 0x40010000 0x800>; reg-names = "base", "lcpa"; - interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <3>; memcpy-channels = <56 57 58 59 60>; @@ -479,7 +481,7 @@ compatible = "stericsson,db8500-prcmu"; reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>; reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm"; - interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <1>; interrupt-controller; @@ -597,7 +599,7 @@ ab8500 { compatible = "stericsson,ab8500"; interrupt-parent = <&intc>; - interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; @@ -785,7 +787,7 @@ i2c@80004000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80004000 0x1000>; - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -800,7 +802,7 @@ i2c@80122000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80122000 0x1000>; - interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -816,7 +818,7 @@ i2c@80128000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80128000 0x1000>; - interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -832,7 +834,7 @@ i2c@80110000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x80110000 0x1000>; - interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -848,7 +850,7 @@ i2c@8012a000 { compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; reg = <0x8012a000 0x1000>; - interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; @@ -864,7 +866,7 @@ ssp@80002000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x80002000 0x1000>; - interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; @@ -878,7 +880,7 @@ ssp@80003000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x80003000 0x1000>; - interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; @@ -892,7 +894,7 @@ spi@8011a000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x8011a000 0x1000>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; /* Same clock wired to kernel and pclk */ @@ -907,7 +909,7 @@ spi@80112000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x80112000 0x1000>; - interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; /* Same clock wired to kernel and pclk */ @@ -922,7 +924,7 @@ spi@80111000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x80111000 0x1000>; - interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; /* Same clock wired to kernel and pclk */ @@ -937,7 +939,7 @@ spi@80129000 { compatible = "arm,pl022", "arm,primecell"; reg = <0x80129000 0x1000>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; #address-cells = <1>; #size-cells = <0>; /* Same clock wired to kernel and pclk */ @@ -952,7 +954,7 @@ ux500_serial0: uart@80120000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80120000 0x1000>; - interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ <&dma 13 0 0x0>; /* Logical - MemToDev */ @@ -967,7 +969,7 @@ ux500_serial1: uart@80121000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80121000 0x1000>; - interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */ <&dma 12 0 0x0>; /* Logical - MemToDev */ @@ -982,7 +984,7 @@ ux500_serial2: uart@80007000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x80007000 0x1000>; - interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */ <&dma 11 0 0x0>; /* Logical - MemToDev */ @@ -997,7 +999,7 @@ sdi0_per1@80126000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80126000 0x1000>; - interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */ <&dma 29 0 0x0>; /* Logical - MemToDev */ @@ -1013,7 +1015,7 @@ sdi1_per2@80118000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80118000 0x1000>; - interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */ <&dma 32 0 0x0>; /* Logical - MemToDev */ @@ -1029,7 +1031,7 @@ sdi2_per3@80005000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80005000 0x1000>; - interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */ <&dma 28 0 0x0>; /* Logical - MemToDev */ @@ -1045,7 +1047,7 @@ sdi3_per2@80119000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80119000 0x1000>; - interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */ <&dma 41 0 0x0>; /* Logical - MemToDev */ @@ -1061,7 +1063,7 @@ sdi4_per2@80114000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80114000 0x1000>; - interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */ <&dma 42 0 0x0>; /* Logical - MemToDev */ @@ -1077,7 +1079,7 @@ sdi5_per3@80008000 { compatible = "arm,pl18x", "arm,primecell"; reg = <0x80008000 0x1000>; - interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */ <&dma 43 0 0x0>; /* Logical - MemToDev */ @@ -1093,7 +1095,7 @@ msp0: msp@80123000 { compatible = "stericsson,ux500-msp-i2s"; reg = <0x80123000 0x1000>; - interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */ @@ -1109,7 +1111,7 @@ msp1: msp@80124000 { compatible = "stericsson,ux500-msp-i2s"; reg = <0x80124000 0x1000>; - interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; /* This DMA channel only exist on DB8500 v1 */ @@ -1126,7 +1128,7 @@ msp2: msp@80117000 { compatible = "stericsson,ux500-msp-i2s"; reg = <0x80117000 0x1000>; - interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; dmas = <&dma 14 0 0x12>, /* Logical - DevToMem - HighPrio */ @@ -1143,7 +1145,7 @@ msp3: msp@80125000 { compatible = "stericsson,ux500-msp-i2s"; reg = <0x80125000 0x1000>; - interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; /* This DMA channel only exist on DB8500 v2 */ @@ -1176,7 +1178,7 @@ <0xa0351000 0x1000>, /* DSI link 1 */ <0xa0352000 0x1000>, /* DSI link 2 */ <0xa0353000 0x1000>; /* DSI link 3 */ - interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */ <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */ <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */ @@ -1190,7 +1192,7 @@ cryp@a03cb000 { compatible = "stericsson,ux500-cryp"; reg = <0xa03cb000 0x1000>; - interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; v-ape-supply = <&db8500_vape_reg>; clocks = <&prcc_pclk 6 1>; diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index c3987ad06d79..6f720756057d 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -22,13 +22,13 @@ button@139 { /* Proximity sensor */ - gpios = <&gpio6 25 0x4>; + gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; linux,code = <11>; /* SW_FRONT_PROXIMITY */ label = "SFH7741 Proximity Sensor"; }; button@145 { /* Hall sensor */ - gpios = <&gpio4 17 0x4>; + gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; linux,code = <0>; /* SW_LID */ label = "HED54XXU11 Hall Effect Sensor"; }; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index 55f9d0cc90f3..fc5e8ce700c3 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -24,13 +24,13 @@ button@139 { /* Proximity sensor */ - gpios = <&gpio6 25 0x4>; + gpios = <&gpio6 25 GPIO_ACTIVE_HIGH>; linux,code = <11>; /* SW_FRONT_PROXIMITY */ label = "SFH7741 Proximity Sensor"; }; button@145 { /* Hall sensor */ - gpios = <&gpio4 17 0x4>; + gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; linux,code = <0>; /* SW_LID */ label = "HED54XXU11 Hall Effect Sensor"; }; @@ -93,14 +93,15 @@ /* Accelerometer */ compatible = "st,lsm303dlh-accel"; st,drdy-int-pin = <1>; + drive-open-drain; reg = <0x18>; vdd-supply = <&ab8500_ldo_aux1_reg>; vddio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; pinctrl-0 = <&accel_tvk_mode>; interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>, - <19 IRQ_TYPE_EDGE_RISING>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>, + <19 IRQ_TYPE_EDGE_FALLING>; }; lsm303dlh@1e { /* @@ -118,14 +119,15 @@ /* Accelerometer */ compatible = "st,lis331dl-accel"; st,drdy-int-pin = <1>; + drive-open-drain; reg = <0x1c>; vdd-supply = <&ab8500_ldo_aux1_reg>; vddio-supply = <&db8500_vsmps2_reg>; pinctrl-names = "default"; pinctrl-0 = <&accel_tvk_mode>; interrupt-parent = <&gpio2>; - interrupts = <18 IRQ_TYPE_EDGE_RISING>, - <19 IRQ_TYPE_EDGE_RISING>; + interrupts = <18 IRQ_TYPE_EDGE_FALLING>, + <19 IRQ_TYPE_EDGE_FALLING>; }; ak8974@0f { /* Magnetometer */ @@ -216,7 +218,7 @@ /* Accelerometer interrupt lines 1 & 2 */ tvk_cfg { pins = "GPIO82_C1", "GPIO83_D3"; - ste,config = <&gpio_in_pd>; + ste,config = <&gpio_in_pu>; }; }; }; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index b0278f4c486c..ece222d51717 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -18,7 +18,7 @@ / { gpio_keys { button@1 { - gpios = <&tc3589x_gpio 7 0x4>; + gpios = <&tc3589x_gpio 7 GPIO_ACTIVE_HIGH>; }; }; @@ -68,12 +68,12 @@ // External Micro SD slot sdi0_per1@80126000 { - cd-gpios = <&tc3589x_gpio 3 0x4>; + cd-gpios = <&tc3589x_gpio 3 GPIO_ACTIVE_HIGH>; }; vmmci: regulator-gpio { - gpios = <&tc3589x_gpio 18 0x4>; - enable-gpio = <&tc3589x_gpio 17 0x4>; + gpios = <&tc3589x_gpio 18 GPIO_ACTIVE_HIGH>; + enable-gpio = <&tc3589x_gpio 17 GPIO_ACTIVE_HIGH>; }; pinctrl { diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index 149a72e7e37a..45d7af326718 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -20,12 +20,12 @@ soc { // External Micro SD slot sdi0_per1@80126000 { - cd-gpios = <&gpio2 31 0x4>; // 95 + cd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95 }; vmmci: regulator-gpio { - gpios = <&gpio0 5 0x4>; - enable-gpio = <&gpio5 9 0x4>; + gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + enable-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; }; pinctrl { diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index 4a21c6492dbb..d35aa88791ad 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -57,8 +57,15 @@ }; }; }; + lis3lv02dl { + lis3lv02dl_nhk_mode: lis3lv02dl_nhk { + nhk_cfg1 { + pins = "GPIO82_C10"; // IRQ line + ste,input = <0>; + }; + }; + }; }; - src@101e0000 { /* These chrystal outputs are not used on this board */ disable-sxtalo; @@ -86,6 +93,10 @@ lis3lv02dl@1d { /* Accelerometer */ compatible = "st,lis3lv02dl-accel"; + interrupt-parent = <&gpio2>; + interrupts = <18 IRQ_TYPE_EDGE_RISING>; // GPIO 82 + pinctrl-0 = <&lis3lv02dl_nhk_mode>; + pinctrl-names = "default"; reg = <0x1d>; }; stmpe0: stmpe2401@43 { diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index e2be53343064..d2d532a9d783 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -748,6 +748,9 @@ clocks = <&uart0clk>, <&pclkuart0>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; + dmas = <&dmac0 14 1>, + <&dmac0 15 1>; + dma-names = "rx", "tx"; }; uart1: uart@101fb000 { @@ -759,6 +762,9 @@ clock-names = "uartclk", "apb_pclk"; pinctrl-names = "default"; pinctrl-0 = <&uart1_default_mux>; + dmas = <&dmac1 22 1>, + <&dmac1 23 1>; + dma-names = "rx", "tx"; }; uart2: uart@101f2000 { @@ -769,6 +775,9 @@ clocks = <&uart2clk>, <&pclkuart2>; clock-names = "uartclk", "apb_pclk"; status = "disabled"; + dmas = <&dmac1 30 1>, + <&dmac1 31 1>; + dma-names = "rx", "tx"; }; rng: rng@101b0000 { @@ -813,5 +822,34 @@ pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; vmmc-supply = <&vmmc_regulator>; }; + + dmac0: dma-controller@10130000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10130000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <15>; + clocks = <&hclkdma0>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; + dmac1: dma-controller@10150000 { + compatible = "arm,pl080", "arm,primecell"; + reg = <0x10150000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <13>; + clocks = <&hclkdma1>; + clock-names = "apb_pclk"; + lli-bus-interface-ahb1; + lli-bus-interface-ahb2; + mem-bus-interface-ahb2; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; }; }; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 08f82077b64d..36e84efc401c 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -50,35 +50,35 @@ wakeup-source; linux,code = <2>; label = "userpb"; - gpios = <&gpio1 0 0x4>; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; }; button@2 { debounce_interval = <50>; wakeup-source; linux,code = <3>; label = "extkb1"; - gpios = <&gpio4 23 0x4>; + gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>; }; button@3 { debounce_interval = <50>; wakeup-source; linux,code = <4>; label = "extkb2"; - gpios = <&gpio4 24 0x4>; + gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; }; button@4 { debounce_interval = <50>; wakeup-source; linux,code = <5>; label = "extkb3"; - gpios = <&gpio5 1 0x4>; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; }; button@5 { debounce_interval = <50>; wakeup-source; linux,code = <6>; label = "extkb4"; - gpios = <&gpio5 2 0x4>; + gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; }; }; @@ -88,7 +88,7 @@ pinctrl-0 = <&gpioled_snowball_mode>; used-led { label = "user_led"; - gpios = <&gpio4 14 0x4>; + gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; default-state = "on"; linux,default-trigger = "heartbeat"; }; @@ -155,8 +155,8 @@ vmmci: regulator-gpio { compatible = "regulator-gpio"; - gpios = <&gpio7 4 0x4>; - enable-gpio = <&gpio6 25 0x4>; + gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + enable-gpio = <&gpio6 25 GPIO_ACTIVE_HIGH>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <2900000>; @@ -182,8 +182,7 @@ pinctrl-0 = <&sdi0_default_mode>; pinctrl-1 = <&sdi0_sleep_mode>; - cd-gpios = <&gpio6 26 0x4>; // 218 - cd-inverted; + cd-gpios = <&gpio6 26 GPIO_ACTIVE_LOW>; // 218 status = "okay"; }; diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 81f81214cdf9..ad8ba10764a3 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -15,6 +15,36 @@ #address-cells = <1>; #size-cells = <1>; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gp0_reserved: rproc@40000000 { + compatible = "shared-dma-pool"; + reg = <0x40000000 0x01000000>; + no-map; + }; + + gp1_reserved: rproc@41000000 { + compatible = "shared-dma-pool"; + reg = <0x41000000 0x01000000>; + no-map; + }; + + audio_reserved: rproc@42000000 { + compatible = "shared-dma-pool"; + reg = <0x42000000 0x01000000>; + no-map; + }; + + dmu_reserved: rproc@43000000 { + compatible = "shared-dma-pool"; + reg = <0x43000000 0x01000000>; + no-map; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -22,15 +52,35 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + + /* kHz uV */ + operating-points = <1500000 0 + 1200000 0 + 800000 0 + 500000 0>; + + clocks = <&clk_m_a9>; + clock-names = "cpu"; + clock-latency = <100000>; + cpu0-supply = <&pwm_regulator>; + st,syscfg = <&syscfg_core 0x8e0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + + /* kHz uV */ + operating-points = <1500000 0 + 1200000 0 + 800000 0 + 500000 0>; }; }; @@ -534,7 +584,7 @@ reg = <0x8788000 0x1000>; interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; clocks = <&clk_s_d3_flexgen CLK_LPC_1>; - st,lpc-mode = <ST_LPC_MODE_RTC>; + st,lpc-mode = <ST_LPC_MODE_CLKSRC>; }; sata0: sata@9b20000 { @@ -694,5 +744,79 @@ clocks = <&clk_sysin>; status = "okay"; }; + + mailbox0: mailbox@8f00000 { + compatible = "st,stih407-mailbox"; + reg = <0x8f00000 0x1000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_NONE>; + #mbox-cells = <2>; + mbox-name = "a9"; + status = "okay"; + }; + + mailbox1: mailbox@8f01000 { + compatible = "st,stih407-mailbox"; + reg = <0x8f01000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_gp_1"; + status = "okay"; + }; + + mailbox2: mailbox@8f02000 { + compatible = "st,stih407-mailbox"; + reg = <0x8f02000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_gp_0"; + status = "okay"; + }; + + mailbox3: mailbox@8f03000 { + compatible = "st,stih407-mailbox"; + reg = <0x8f03000 0x1000>; + #mbox-cells = <2>; + mbox-name = "st231_audio_video"; + status = "okay"; + }; + + st231_gp0: remote-processor { + compatible = "st,st231-rproc"; + memory-region = <&gp0_reserved>; + resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x22c>; + }; + + + st231_gp1: remote-processor { + compatible = "st,st231-rproc"; + memory-region = <&gp1_reserved>; + resets = <&softreset STIH407_ST231_GP1_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_GP_1>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x220>; + }; + + st231_audio: remote-processor { + compatible = "st,st231-rproc"; + memory-region = <&audio_reserved>; + resets = <&softreset STIH407_ST231_AUD_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_AUD_0>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x228>; + }; + + st231_dmu: remote-processor { + compatible = "st,st231-rproc"; + memory-region = <&dmu_reserved>; + resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; + reset-names = "sw_reset"; + clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; + clock-frequency = <600000000>; + st,syscfg = <&syscfg_core 0x224>; + }; }; }; diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index 97570cb7f2fc..c92a1ae33a1e 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -87,6 +87,24 @@ enable-active-high; gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; }; &ahci { @@ -188,6 +206,12 @@ status = "okay"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pins_a>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts new file mode 100644 index 000000000000..893497e397da --- /dev/null +++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts @@ -0,0 +1,281 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun4i-a10.dtsi" +#include "sunxi-common-regulators.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Dserve DSRV9703C"; + compatible = "dserve,dsrv9703c", "allwinner,sun4i-a10"; + + aliases { + serial0 = &uart0; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en_pin_dsrv9703c>; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + haptics { + compatible = "regulator-haptic"; + haptic-supply = <®_motor>; + min-microvolt = <3000000>; + max-microvolt = <3000000>; + }; + + reg_motor: reg_motor { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&motor_pins>; + regulator-name = "vcc-motor"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + enable-active-high; + gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + }; +}; + +&codec { + pinctrl-names = "default"; + pinctrl-0 = <&codec_pa_pin>; + allwinner,pa-gpios = <&pio 7 15 GPIO_ACTIVE_HIGH>; /* PH15 */ + status = "okay"; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + /* pull-ups and devices require AXP209 LDO3 */ + status = "failed"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + + ft5406ee8: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <7 21 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + reset-gpios = <&pio 1 13 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <768>; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; + + button@800 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <800000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-inverted; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + bl_en_pin_dsrv9703c: bl_en_pin@0 { + allwinner,pins = "PH7"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + codec_pa_pin: codec_pa_pin@0 { + allwinner,pins = "PH15"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + motor_pins: motor_pins@0 { + allwinner,pins = "PB3"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + touchscreen_pins: touchscreen_pins@0 { + allwinner,pins = "PB13"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PH4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PH5"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-dll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_usb0_vbus { + status = "okay"; +}; + +®_usb2_vbus { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */ + usb0_vbus_det-gpio = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 2c8f5e6ad905..a03e56fb5dbc 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -96,7 +96,7 @@ allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>, - <&dram_gates 25>, <&dram_gates 26>; + <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>; status = "disabled"; }; }; @@ -184,6 +184,15 @@ clock-output-names = "osc24M"; }; + osc3M: osc3M_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc3M"; + }; + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -208,6 +217,23 @@ "pll2-4x", "pll2-8x"; }; + pll3: clk@01c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll3"; + }; + + pll3x2: pll3x2_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll3>; + clock-output-names = "pll3-2x"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk"; @@ -232,6 +258,23 @@ clock-output-names = "pll6_sata", "pll6_other", "pll6"; }; + pll7: clk@01c20030 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20030 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll7"; + }; + + pll7x2: pll7x2_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll7>; + clock-output-names = "pll7-2x"; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; @@ -477,6 +520,17 @@ clock-output-names = "ir1"; }; + spdif_clk: clk@01c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "spdif"; + }; + usb_clk: clk@01c200cc { #clock-cells = <1>; #reset-cells = <1>; @@ -1006,6 +1060,13 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + spdif_tx_pins_a: spdif@0 { + allwinner,pins = "PB13"; + allwinner,function = "spdif"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; }; timer@01c20c00 { @@ -1034,6 +1095,19 @@ status = "disabled"; }; + spdif: spdif@01c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-spdif"; + reg = <0x01c21000 0x400>; + interrupts = <13>; + clocks = <&apb0_gates 1>, <&spdif_clk>; + clock-names = "apb", "spdif"; + dmas = <&dma SUN4I_DMA_NORMAL 2>, + <&dma SUN4I_DMA_NORMAL 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + ir0: ir@01c21800 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 6>, <&ir0_clk>; diff --git a/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts b/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts new file mode 100644 index 000000000000..6546fa02901d --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts @@ -0,0 +1,226 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sunxi-common-regulators.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Difrnce DIT4350"; + compatible = "difrnce,dit4350", "allwinner,sun5i-a13"; + + aliases { + serial0 = &uart1; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + /* TODO: backlight uses axp gpio1 as enable pin */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + reg = <0x34>; + interrupts = <0>; + }; +}; + +#include "axp209.dtsi" + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; +}; + +&lradc { + vref-supply = <®_ldo2>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ + cd-inverted; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&pio { + mmc0_cd_pin_d709: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + status = "okay"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd-int-pll"; +}; + +®_ldo1 { + regulator-name = "vdd-rtc"; +}; + +®_ldo2 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; +}; + +®_ldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_usb0_vbus { + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb0_vbus_pin_a { + allwinner,pins = "PG12"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; + usb1_vbus-supply = <®_ldo3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts index 7fbb0b0558a9..6efbba6d40a9 100644 --- a/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-d709.dts @@ -123,7 +123,7 @@ &mmc0 { pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ @@ -131,27 +131,12 @@ status = "okay"; }; -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; - - mmccard: mmccard@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; - &otg_sram { status = "okay"; }; &pio { - mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 { + mmc0_cd_pin_d709: mmc0_cd_pin@0 { allwinner,pins = "PG0"; allwinner,function = "gpio_in"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; diff --git a/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts b/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts index 6fa54b661423..1b11ec95ae53 100644 --- a/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts +++ b/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts @@ -123,21 +123,6 @@ status = "okay"; }; -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_a>; - vmmc-supply = <®_vcc3v3>; - bus-width = <8>; - non-removable; - status = "okay"; - - mmccard: mmccard@0 { - reg = <0>; - compatible = "mmc-card"; - broken-hpi; - }; -}; - &otg_sram { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index ad84fe4276c9..081329e2b80b 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -109,6 +109,10 @@ status = "okay"; }; +&otg_sram { + status = "okay"; +}; + &pio { mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 { allwinner,pins = "PG0"; @@ -124,6 +128,27 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PG2"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { + allwinner,pins = "PG1"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>; + }; + + usb0_vbus_pin_olinuxinom: usb0_vbus_pin@0 { + allwinner,pins = "PG12"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + usb1_vbus_pin_olinuxinom: usb1_vbus_pin@0 { allwinner,pins = "PG11"; allwinner,function = "gpio_out"; @@ -132,6 +157,12 @@ }; }; +®_usb0_vbus { + pinctrl-0 = <&usb0_vbus_pin_olinuxinom>; + gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + ®_usb1_vbus { pinctrl-0 = <&usb1_vbus_pin_olinuxinom>; gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; @@ -144,7 +175,17 @@ status = "okay"; }; +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; + usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ + usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index d910d3a6c41c..263d46dbc7e6 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -61,7 +61,8 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0"; - clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; + clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>, + <&tcon_ch0_clk>, <&dram_gates 26>; status = "disabled"; }; }; @@ -110,8 +111,8 @@ <10>, <13>, <14>, <20>, <21>, <22>, - <28>, <32>, <36>, - <40>, <44>, + <28>, <32>, <34>, + <36>, <40>, <44>, <46>, <51>, <52>; clock-output-names = "ahb_usbotg", "ahb_ehci", @@ -120,8 +121,8 @@ "ahb_mmc2", "ahb_nand", "ahb_sdram", "ahb_spi0", "ahb_spi1", "ahb_spi2", - "ahb_stimer", "ahb_ve", "ahb_lcd", - "ahb_csi", "ahb_de_be", + "ahb_stimer", "ahb_ve", "ahb_tve", + "ahb_lcd", "ahb_csi", "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400"; }; @@ -149,6 +150,61 @@ "apb1_i2c2", "apb1_uart1", "apb1_uart3"; }; + + dram_gates: clk@01c20100 { + #clock-cells = <1>; + compatible = "allwinner,sun5i-a13-dram-gates-clk", + "allwinner,sun4i-a10-gates-clk"; + reg = <0x01c20100 0x4>; + clocks = <&pll5 0>; + clock-indices = <0>, + <1>, + <25>, + <26>, + <29>, + <31>; + clock-output-names = "dram_ve", + "dram_csi", + "dram_de_fe", + "dram_de_be", + "dram_ace", + "dram_iep"; + }; + + de_be_clk: clk@01c20104 { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c20104 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-be"; + }; + + de_fe_clk: clk@01c2010c { + #clock-cells = <0>; + #reset-cells = <0>; + compatible = "allwinner,sun4i-a10-display-clk"; + reg = <0x01c2010c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; + clock-output-names = "de-fe"; + }; + + tcon_ch0_clk: clk@01c20118 { + #clock-cells = <0>; + #reset-cells = <1>; + compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; + reg = <0x01c20118 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch0-sclk"; + }; + + tcon_ch1_clk: clk@01c2012c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; + reg = <0x01c2012c 0x4>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; + clock-output-names = "tcon-ch1-sclk"; + }; }; soc@01c00000 { diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index f6898c6b84d4..a8d8b4582397 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -66,6 +66,10 @@ }; }; +&be0 { + status = "okay"; +}; + &codec { status = "okay"; }; @@ -188,6 +192,14 @@ status = "okay"; }; +&tcon0 { + status = "okay"; +}; + +&tve0 { + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_b>; diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi index 0ef865601ac9..c04cf690b858 100644 --- a/arch/arm/boot/dts/sun5i-r8.dtsi +++ b/arch/arm/boot/dts/sun5i-r8.dtsi @@ -51,9 +51,147 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>; + clocks = <&ahb_gates 34>, <&ahb_gates 36>, + <&ahb_gates 44>, <&de_be_clk>, + <&tcon_ch1_clk>, <&dram_gates 26>; status = "disabled"; }; }; + + soc@01c00000 { + tve0: tv-encoder@01c0a000 { + compatible = "allwinner,sun4i-a10-tv-encoder"; + reg = <0x01c0a000 0x1000>; + clocks = <&ahb_gates 34>; + resets = <&tcon_ch0_clk 0>; + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + tve0_in_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_out_tve0>; + }; + }; + }; + + tcon0: lcd-controller@01c0c000 { + compatible = "allwinner,sun5i-a13-tcon"; + reg = <0x01c0c000 0x1000>; + interrupts = <44>; + resets = <&tcon_ch0_clk 1>; + reset-names = "lcd"; + clocks = <&ahb_gates 36>, + <&tcon_ch0_clk>, + <&tcon_ch1_clk>; + clock-names = "ahb", + "tcon-ch0", + "tcon-ch1"; + clock-output-names = "tcon-pixel-clock"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + tcon0_in_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_out_tcon0>; + }; + }; + + tcon0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + tcon0_out_tve0: endpoint@1 { + reg = <1>; + remote-endpoint = <&tve0_in_tcon0>; + }; + }; + }; + }; + + fe0: display-frontend@01e00000 { + compatible = "allwinner,sun5i-a13-display-frontend"; + reg = <0x01e00000 0x20000>; + interrupts = <47>; + clocks = <&ahb_gates 46>, <&de_fe_clk>, + <&dram_gates 25>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_fe_clk>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + fe0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + fe0_out_be0: endpoint@0 { + reg = <0>; + remote-endpoint = <&be0_in_fe0>; + }; + }; + }; + }; + + be0: display-backend@01e60000 { + compatible = "allwinner,sun5i-a13-display-backend"; + reg = <0x01e60000 0x10000>; + clocks = <&ahb_gates 44>, <&de_be_clk>, + <&dram_gates 26>; + clock-names = "ahb", "mod", + "ram"; + resets = <&de_be_clk>; + status = "disabled"; + + assigned-clocks = <&de_be_clk>; + assigned-clock-rates = <300000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + be0_in: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + be0_in_fe0: endpoint@0 { + reg = <0>; + remote-endpoint = <&fe0_out_be0>; + }; + }; + + be0_out: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + be0_out_tcon0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon0_in_be0>; + }; + }; + }; + }; + }; + + display-engine { + compatible = "allwinner,sun5i-a13-display-engine"; + allwinner,pipelines = <&fe0>; + }; }; diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi index 59a9426e3bd4..0840612b5ed6 100644 --- a/arch/arm/boot/dts/sun5i.dtsi +++ b/arch/arm/boot/dts/sun5i.dtsi @@ -88,6 +88,15 @@ clock-output-names = "osc24M"; }; + osc3M: osc3M_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc3M"; + }; + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -112,6 +121,23 @@ "pll2-4x", "pll2-8x"; }; + pll3: clk@01c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll3"; + }; + + pll3x2: pll3x2_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll3>; + clock-output-names = "pll3-2x"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-pll1-clk"; @@ -136,6 +162,23 @@ clock-output-names = "pll6_sata", "pll6_other", "pll6"; }; + pll7: clk@01c20030 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20030 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll7"; + }; + + pll7x2: pll7x2_clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <2>; + clocks = <&pll7>; + clock-output-names = "pll7-2x"; + }; + /* dummy is 200M */ cpu: cpu@01c20054 { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts new file mode 100644 index 000000000000..e182eec6d878 --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts @@ -0,0 +1,208 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Colorfly E708 Q1 tablet"; + compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&ehci0 { + /* rtl8188etv wifi is connected here */ + status = "okay"; +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button@1000 { + label = "Home"; + linux,code = <KEY_HOMEPAGE>; + channel = <0>; + voltage = <1000000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + cd-inverted; + status = "okay"; +}; + +&pio { + mma8452_int_e708_q1: mma8452_int_pin@0 { + allwinner,pins = "PA9"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; + + mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { + allwinner,pins = "PA8"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; /* This is an educated guess */ +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_dldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pg"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; + vcc-pg-supply = <®_dldo2>; +}; + +/* + * FIXME for now we only support host mode and rely on u-boot to have + * turned on Vbus which is controlled by the axp221 pmic on the board. + * + * Once we have axp221 power-supply and vbus-usb support we should switch + * to fully supporting otg. + */ +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_dldo1>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index 8da939ab8350..83f39b0362cb 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -94,6 +94,24 @@ pinctrl-0 = <&mmc3_pwrseq_pin_cubietruck>; reset-gpios = <&pio 7 9 GPIO_ACTIVE_LOW>; /* PH9 WIFI_EN */ }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; }; &ahci { @@ -301,6 +319,12 @@ status = "okay"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pins_a>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>; diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts index 661c21d9bdbd..10d48cbf81ff 100644 --- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts +++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts @@ -65,6 +65,24 @@ default-state = "on"; }; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "On-board SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + }; }; &ahci { @@ -123,3 +141,9 @@ ®_ahci_5v { status = "okay"; }; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts new file mode 100644 index 000000000000..5ea4915f6d75 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2-emmc.dts @@ -0,0 +1,82 @@ + /* + * Copyright 2015 - Ultimaker B.V. + * Author Olliver Schinagl <oliver@schinagl.nl> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sun7i-a20-olinuxino-lime2.dts" + +/ { + model = "Olimex A20-OLinuXino-LIME2-eMMC"; + compatible = "olimex,a20-olinuxino-lime2-emmc", "allwinner,sun7i-a20"; + + mmc2_pwrseq: pwrseq { + pinctrl-0 = <&mmc2_pins_nrst>; + pinctrl-names = "default"; + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&pio 2 16 GPIO_ACTIVE_LOW>; + }; +}; + +&pio { + mmc2_pins_nrst: mmc2@0 { + allwinner,pins = "PC16"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + vqmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + mmc-pwrseq = <&mmc2_pwrseq>; + status = "okay"; + + emmc: emmc@0 { + reg = <0>; + compatible = "mmc-card"; + broken-hpi; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 0940a788f824..febdf4c72fb0 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -85,8 +85,9 @@ compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; allwinner,pipeline = "de_be0-lcd0-tve0"; - clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, - <&ahb_gates 44>, <&dram_gates 26>; + clocks = <&pll5 1>, + <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>, + <&dram_gates 5>, <&dram_gates 26>; status = "disabled"; }; }; @@ -186,6 +187,15 @@ clock-output-names = "osc24M"; }; + osc3M: osc3M_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <8>; + clock-mult = <1>; + clocks = <&osc24M>; + clock-output-names = "osc3M"; + }; + osc32k: clk@0 { #clock-cells = <0>; compatible = "fixed-clock"; @@ -210,6 +220,22 @@ "pll2-4x", "pll2-8x"; }; + pll3: clk@01c20010 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20010 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll3"; + }; + + pll3x2: pll3x2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <2>; + clock-output-names = "pll3-2x"; + }; + pll4: clk@01c20018 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; @@ -235,6 +261,22 @@ "pll6_div_4"; }; + pll7: clk@01c20030 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-pll3-clk"; + reg = <0x01c20030 0x4>; + clocks = <&osc3M>; + clock-output-names = "pll7"; + }; + + pll7x2: pll7x2_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <2>; + clock-output-names = "pll7-2x"; + }; + pll8: clk@01c20040 { #clock-cells = <0>; compatible = "allwinner,sun7i-a20-pll4-clk"; @@ -476,6 +518,17 @@ clock-output-names = "ir1"; }; + spdif_clk: clk@01c200c0 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod1-clk"; + reg = <0x01c200c0 0x4>; + clocks = <&pll2 SUN4I_A10_PLL2_8X>, + <&pll2 SUN4I_A10_PLL2_4X>, + <&pll2 SUN4I_A10_PLL2_2X>, + <&pll2 SUN4I_A10_PLL2_1X>; + clock-output-names = "spdif"; + }; + keypad_clk: clk@01c200c4 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; @@ -1193,6 +1246,13 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + spdif_tx_pins_a: spdif@0 { + allwinner,pins = "PB13"; + allwinner,function = "spdif"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; }; timer@01c20c00 { @@ -1226,6 +1286,19 @@ status = "disabled"; }; + spdif: spdif@01c21000 { + #sound-dai-cells = <0>; + compatible = "allwinner,sun4i-a10-spdif"; + reg = <0x01c21000 0x400>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&apb0_gates 1>, <&spdif_clk>; + clock-names = "apb", "spdif"; + dmas = <&dma SUN4I_DMA_NORMAL 2>, + <&dma SUN4I_DMA_NORMAL 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + ir0: ir@01c21800 { compatible = "allwinner,sun4i-a10-ir"; clocks = <&apb0_gates 6>, <&ir0_clk>; diff --git a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts index 1aeb06c649b9..b2ce284a65a2 100644 --- a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts +++ b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts @@ -47,15 +47,26 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/pwm/pwm.h> / { - model = "Allwinner GT90H Quad Core Tablet (v4)"; - compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a33"; + model = "Allwinner GT90H Dual Core Tablet (v4)"; + compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23"; aliases { serial0 = &r_uart; }; + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en_pin_gt90h>; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -106,8 +117,7 @@ &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gt90h>; - /* FIXME this really is aldo1, correct once we've pmic support */ - vmmc-supply = <®_vcc3v0>; + vmmc-supply = <®_aldo1>; bus-width = <4>; cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ cd-inverted; @@ -115,6 +125,13 @@ }; &pio { + bl_en_pin_gt90h: bl_en_pin@0 { + allwinner,pins = "PH6"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + mmc0_cd_pin_gt90h: mmc0_cd_pin@0 { allwinner,pins = "PB4"; allwinner,function = "gpio_in"; @@ -123,12 +140,106 @@ }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + }; +}; + &r_uart { pinctrl-names = "default"; pinctrl-0 = <&r_uart_pins_a>; status = "okay"; }; +#include "axp22x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + /* * FIXME for now we only support host mode and rely on u-boot to have * turned on Vbus which is controlled by the axp223 pmic on the board. @@ -141,5 +252,6 @@ }; &usbphy { + usb1_vbus-supply = <®_dldo1>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts new file mode 100644 index 000000000000..cb5daafcb7c2 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -0,0 +1,243 @@ +/* + * Copyright 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a23.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Polaroid MID2809PXE04 tablet"; + compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23"; + + aliases { + serial0 = &r_uart; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en_pin_mid2809>; + pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; + brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; + default-brightness-level = <8>; + enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <200000>; + }; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <400000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mid2809>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&pio { + bl_en_pin_mid2809: bl_en_pin@0 { + allwinner,pins = "PH6"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + mmc0_cd_pin_mid2809: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>; + status = "okay"; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + }; +}; + +&r_uart { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; + status = "okay"; +}; + +#include "axp22x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pll-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +/* + * FIXME for now we only support host mode and rely on u-boot to have + * turned on Vbus which is controlled by the axp223 pmic on the board. + * + * Once we have axp223 support we should switch to fully supporting otg. + */ +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts new file mode 100644 index 000000000000..f93f5d1695c4 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi 2"; + compatible = "xunlong,orangepi-2", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + r_gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_opc>; + + sw2 { + label = "sw2"; + linux,code = <BTN_1>; + gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; + }; + + sw4 { + label = "sw4"; + linux,code = <BTN_0>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_orangepi>; + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */ + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; +}; + +&pio { + leds_opc: led_pins@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_opc: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + sw_r_opc: key_pins@0 { + allwinner,pins = "PL3", "PL4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + wifi_pwrseq_pin_orangepi: wifi_pwrseq_pin@0 { + allwinner,pins = "PL7"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +®_usb1_vbus { + gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usb1_vbus_pin_a { + allwinner,pins = "PG13"; +}; + +&usbphy { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts new file mode 100644 index 000000000000..0adf932fd923 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi One"; + compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + r_gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_opc>; + + sw4 { + label = "sw4"; + linux,code = <BTN_0>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + leds_opc: led_pins@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_opc: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + sw_r_opc: key_pins@0 { + allwinner,pins = "PL3"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts new file mode 100644 index 000000000000..daf50b9a6657 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2015 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi PC"; + compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + r_gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_opc>; + + sw4 { + label = "sw4"; + linux,code = <BTN_0>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + leds_opc: led_pins@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_opc: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + sw_r_opc: key_pins@0 { + allwinner,pins = "PL3"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 79f40c3e6101..b0cb41787e09 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -40,95 +40,56 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +/* The Orange Pi Plus is an extended version of the Orange Pi 2 */ +#include "sun8i-h3-orangepi-2.dts" / { model = "Xunlong Orange Pi Plus"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - leds { - compatible = "gpio-leds"; + reg_usb3_vbus: usb3-vbus { + compatible = "regulator-fixed"; pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>, <&leds_r_opc>; - - status_led { - label = "orangepi-plus:red:status"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - - pwr_led { - label = "orangepi-plus:green:pwr"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; + pinctrl-0 = <&usb3_vbus_pin_a>; + regulator-name = "usb3-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + enable-active-high; + gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; }; +}; - r_gpio_keys { - compatible = "gpio-keys"; - input-name = "sw4"; - - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_opc>; +&ehci3 { + status = "okay"; +}; - sw4@0 { - label = "sw4"; - linux,code = <BTN_0>; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; }; -&pio { - leds_opc: led_pins@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + /* eMMC is missing pull-ups */ + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; -&r_pio { - leds_r_opc: led_pins@0 { - allwinner,pins = "PL10"; +&pio { + usb3_vbus_pin_a: usb3_vbus_pin@0 { + allwinner,pins = "PG11"; allwinner,function = "gpio_out"; allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; - - sw_r_opc: key_pins@0 { - allwinner,pins = "PL03"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; }; -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; +&usbphy { + usb3_vbus-supply = <®_usb3_vbus>; }; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index dadb7f60c062..4a4926b0b0ed 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -269,6 +269,18 @@ "mmc2_sample"; }; + usb_clk: clk@01c200cc { + #clock-cells = <1>; + #reset-cells = <1>; + compatible = "allwinner,sun8i-h3-usb-clk"; + reg = <0x01c200cc 0x4>; + clocks = <&osc24M>; + clock-output-names = "usb_phy0", "usb_phy1", + "usb_phy2", "usb_phy3", + "usb_ohci0", "usb_ohci1", + "usb_ohci2", "usb_ohci3"; + }; + mbus_clk: clk@01c2015c { #clock-cells = <0>; compatible = "allwinner,sun8i-a23-mbus-clk"; @@ -377,6 +389,107 @@ #size-cells = <0>; }; + usbphy: phy@01c19400 { + compatible = "allwinner,sun8i-h3-usb-phy"; + reg = <0x01c19400 0x2c>, + <0x01c1a800 0x4>, + <0x01c1b800 0x4>, + <0x01c1c800 0x4>, + <0x01c1d800 0x4>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1", + "pmu2", + "pmu3"; + clocks = <&usb_clk 8>, + <&usb_clk 9>, + <&usb_clk 10>, + <&usb_clk 11>; + clock-names = "usb0_phy", + "usb1_phy", + "usb2_phy", + "usb3_phy"; + resets = <&usb_clk 0>, + <&usb_clk 1>, + <&usb_clk 2>, + <&usb_clk 3>; + reset-names = "usb0_reset", + "usb1_reset", + "usb2_reset", + "usb3_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci1: usb@01c1b000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1b000 0x100>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 25>, <&bus_gates 29>; + resets = <&ahb_rst 25>, <&ahb_rst 29>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@01c1b400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1b400 0x100>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 29>, <&bus_gates 25>, + <&usb_clk 17>; + resets = <&ahb_rst 29>, <&ahb_rst 25>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci2: usb@01c1c000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1c000 0x100>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 26>, <&bus_gates 30>; + resets = <&ahb_rst 26>, <&ahb_rst 30>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci2: usb@01c1c400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1c400 0x100>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 30>, <&bus_gates 26>, + <&usb_clk 18>; + resets = <&ahb_rst 30>, <&ahb_rst 26>; + phys = <&usbphy 2>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci3: usb@01c1d000 { + compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; + reg = <0x01c1d000 0x100>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 27>, <&bus_gates 31>; + resets = <&ahb_rst 27>, <&ahb_rst 31>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci3: usb@01c1d400 { + compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; + reg = <0x01c1d400 0x100>; + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&bus_gates 31>, <&bus_gates 27>, + <&usb_clk 19>; + resets = <&ahb_rst 31>, <&ahb_rst 27>; + phys = <&usbphy 3>; + phy-names = "usb"; + status = "disabled"; + }; + pio: pinctrl@01c20800 { compatible = "allwinner,sun8i-h3-pinctrl"; reg = <0x01c20800 0x400>; @@ -417,6 +530,16 @@ allwinner,drive = <SUN4I_PINCTRL_30_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + mmc2_8bit_pins: mmc2_8bit { + allwinner,pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15", "PC16"; + allwinner,function = "mmc2"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; ahb_rst: reset@01c202c0 { diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi index ef665d21d317..dd7eb5f624d9 100644 --- a/arch/arm/boot/dts/tango4-common.dtsi +++ b/arch/arm/boot/dts/tango4-common.dtsi @@ -3,11 +3,13 @@ * https://github.com/mansr/linux-tangox */ -#define CPU_CLK 0 -#define SYS_CLK 1 - #include <dt-bindings/interrupt-controller/arm-gic.h> +#define CPU_CLK 0 +#define SYS_CLK 1 +#define USB_CLK 2 +#define SDIO_CLK 3 + / { interrupt-parent = <&gic>; #address-cells = <1>; @@ -70,7 +72,7 @@ clkgen: clkgen@10000 { compatible = "sigma,tango4-clkgen"; - reg = <0x10000 0x40>; + reg = <0x10000 0x100>; clocks = <&xtal>; #clock-cells = <1>; }; @@ -89,6 +91,12 @@ reg-shift = <2>; }; + watchdog@1fd00 { + compatible = "sigma,smp8759-wdt"; + reg = <0x1fd00 8>; + clocks = <&xtal>; + }; + eth0: ethernet@26000 { compatible = "sigma,smp8734-ethernet"; reg = <0x26000 0x800>; diff --git a/arch/arm/boot/dts/tango4-smp8758.dtsi b/arch/arm/boot/dts/tango4-smp8758.dtsi index 7ed88ee629fb..d2e65c46bcc7 100644 --- a/arch/arm/boot/dts/tango4-smp8758.dtsi +++ b/arch/arm/boot/dts/tango4-smp8758.dtsi @@ -1,4 +1,4 @@ -#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "tango4-common.dtsi" / { cpus { @@ -11,6 +11,9 @@ next-level-cache = <&l2cc>; device_type = "cpu"; reg = <0>; + clocks = <&clkgen CPU_CLK>; + clock-latency = <1>; + operating-points = <1215000 0 607500 0 405000 0 243000 0 135000 0>; }; cpu1: cpu@1 { @@ -28,4 +31,27 @@ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; }; + + soc { + cpu_temp: thermal@920100 { + #thermal-sensor-cells = <0>; + compatible = "sigma,smp8758-thermal"; + reg = <0x920100 12>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <997>; /* milliseconds */ + polling-delay-passive = <499>; /* milliseconds */ + thermal-sensors = <&cpu_temp>; + trips { + cpu_critical { + temperature = <120000>; + hysteresis = <2500>; + type = "critical"; + }; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/tango4-vantage-1172.dts b/arch/arm/boot/dts/tango4-vantage-1172.dts index 3e5b9c81a51c..4cab64cb581e 100644 --- a/arch/arm/boot/dts/tango4-vantage-1172.dts +++ b/arch/arm/boot/dts/tango4-vantage-1172.dts @@ -1,7 +1,6 @@ /dts-v1/; #include "tango4-smp8758.dtsi" -#include "tango4-common.dtsi" / { model = "Sigma Designs SMP8758 Vantage-1172 Rev E1"; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 8b7aa0dcdc6e..c970bf65c74c 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -18,6 +18,10 @@ serial0 = &uartd; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x80000000 0x40000000>; }; @@ -1164,7 +1168,7 @@ label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; - gpio-key,wakeup; + wakeup-source; }; volume_down { diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 38acf78d7815..9d868af97b8e 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -1047,7 +1047,7 @@ label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index f91c2c9b2f94..89047edb5c5f 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -292,7 +292,7 @@ label = "Power"; gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; - gpio-key,wakeup; + wakeup-source; }; volume_down { diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index d845bd1448b5..cb9393a53422 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -150,7 +150,7 @@ }; timer@60005000 { - compatible = "nvidia,tegra114-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; reg = <0x60005000 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, @@ -256,7 +256,7 @@ * driver and APB DMA based serial driver for higher baudrate * and performace. To enable the 8250 based driver, the compatible * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the comptible is + * the APB DMA based serial driver, the compatible is * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". */ uarta: serial@70006000 { diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 66b4451eb2ca..a99f07ad6312 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -12,7 +12,15 @@ aliases { rtc0 = "/i2c@0,7000d000/pmic@40"; rtc1 = "/rtc@0,7000e000"; + + /* This order keeps the mapping DB9 connector <-> ttyS0 */ serial0 = &uartd; + serial1 = &uarta; + serial2 = &uartb; + }; + + chosen { + stdout-path = "serial0:115200n8"; }; memory { @@ -1367,6 +1375,28 @@ }; }; + /* + * First high speed UART, exposed on the expansion connector J3A2 + * Pin 41: BR_UART1_TXD + * Pin 44: BR_UART1_RXD + */ + serial@70006000 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + status = "okay"; + }; + + /* + * Second high speed UART, exposed on the expansion connector J3A2 + * Pin 65: UART2_RXD + * Pin 68: UART2_TXD + * Pin 71: UART2_CTS_L + * Pin 74: UART2_RTS_L + */ + serial@70006040 { + compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; + status = "okay"; + }; + /* DB9 serial port */ serial@0,70006300 { status = "okay"; @@ -1761,7 +1791,7 @@ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; debounce-interval = <10>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index ec1aa64ded68..5f1fc1410bd0 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -8,6 +8,10 @@ serial0 = &uarta; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x0 0x80000000 0x0 0x80000000>; }; @@ -509,7 +513,7 @@ linux,input-type = <5>; linux,code = <KEY_RESERVED>; debounce-interval = <1>; - gpio-key,wakeup; + wakeup-source; }; power { @@ -517,7 +521,7 @@ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; debounce-interval = <30>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index cfbdf429b45d..0318258dde3e 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -13,6 +13,10 @@ serial0 = &uarta; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x0 0x80000000 0x0 0x80000000>; }; @@ -975,7 +979,7 @@ gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; debounce-interval = <10>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 68669f791c8b..e4eac1f01e64 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -208,7 +208,7 @@ }; timer@0,60005000 { - compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; + compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; reg = <0x0 0x60005000 0x0 0x400>; interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, @@ -322,7 +322,7 @@ * driver and APB DMA based serial driver for higher baudrate * and performace. To enable the 8250 based driver, the compatible * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the comptible is + * the APB DMA based serial driver, the compatible is * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". */ uarta: serial@0,70006000 { diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index b926a07b9443..d2e960cbc001 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -13,6 +13,10 @@ serial0 = &uartd; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x00000000 0x40000000>; }; @@ -655,7 +659,7 @@ label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts index 1dd7d7bfdfcc..bb56dfe9e10c 100644 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ b/arch/arm/boot/dts/tegra20-iris-512.dts @@ -11,6 +11,10 @@ serial1 = &uartd; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + host1x@50000000 { hdmi@54280000 { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index 9b87526ab0b7..34c6588e92ef 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -10,6 +10,10 @@ serial0 = &uartd; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + pwm@7000a000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index ed7e1009326c..33ed2b23026b 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -14,6 +14,10 @@ serial1 = &uartc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x00000000 0x20000000>; }; @@ -521,7 +525,7 @@ label = "Power"; gpios = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index aea8994b35f2..94b60a710dd8 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -13,6 +13,10 @@ serial0 = &uartd; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x00000000 0x40000000>; }; @@ -807,7 +811,7 @@ label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; - gpio-key,wakeup; + wakeup-source; }; lid { @@ -816,7 +820,7 @@ linux,input-type = <5>; /* EV_SW */ linux,code = <0>; /* SW_LID */ debounce-interval = <1>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 13d4e6185275..025e9e8037da 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -10,6 +10,10 @@ serial0 = &uartd; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x00000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index d99af4ef9c64..4a035f74043a 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -13,6 +13,10 @@ serial0 = &uarta; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x00000000 0x40000000>; }; @@ -392,7 +396,7 @@ label = "Power"; gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 04c58e9ca490..a28c060a839b 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -13,6 +13,10 @@ serial0 = &uartd; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x00000000 0x40000000>; }; @@ -601,7 +605,7 @@ label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; linux,code = <KEY_POWER>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 340d81108df1..073806d07b2b 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -13,6 +13,10 @@ serial0 = &uarta; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x00000000 0x20000000>; }; @@ -508,7 +512,7 @@ nvidia,repeat-delay-ms = <160>; nvidia,kbc-row-pins = <0 1 2>; nvidia,kbc-col-pins = <16 17>; - nvidia,wakeup-source; + wakeup-source; linux,keymap = <MATRIX_KEY(0x00, 0x00, KEY_POWER) MATRIX_KEY(0x01, 0x00, KEY_HOME) MATRIX_KEY(0x01, 0x01, KEY_BACK) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 33173e1bace9..2207c08e3fa3 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -145,7 +145,7 @@ interrupt-parent = <&intc>; reg = <0x50040600 0x20>; interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; clocks = <&tegra_car TEGRA20_CLK_TWD>; }; @@ -309,7 +309,7 @@ * driver and APB DMA based serial driver for higher baudrate * and performace. To enable the 8250 based driver, the compatible * is "nvidia,tegra20-uart" and to enable the APB DMA based serial - * driver, the comptible is "nvidia,tegra20-hsuart". + * driver, the compatible is "nvidia,tegra20-hsuart". */ uarta: serial@70006000 { compatible = "nvidia,tegra20-uart"; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index f2879cfcca62..99a69457dbf5 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -17,6 +17,10 @@ serial3 = &uartd; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + pcie-controller@00003000 { status = "okay"; @@ -196,7 +200,7 @@ gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; debounce-interval = <10>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 3dede3934446..1eca3b28ac64 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -12,6 +12,10 @@ serial0 = &uarta; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x80000000 0x7ff00000>; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index bb1ca158273c..4721c1c9c780 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -35,6 +35,10 @@ serial1 = &uartc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + memory { reg = <0x80000000 0x40000000>; }; @@ -626,7 +630,7 @@ interrupts = <2 0>; linux,code = <KEY_POWER>; debounce-interval = <100>; - gpio-key,wakeup; + wakeup-source; }; volume-down { diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 3ff019f47d00..76875c3160fe 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -15,6 +15,10 @@ serial2 = &uartd; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + host1x@50000000 { dc@54200000 { rgb { @@ -142,7 +146,7 @@ gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; debounce-interval = <10>; - gpio-key,wakeup; + wakeup-source; }; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 313e260529a3..5030065cbdfe 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -230,7 +230,7 @@ reg = <0x50040600 0x20>; interrupt-parent = <&intc>; interrupts = <GIC_PPI 13 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; clocks = <&tegra_car TEGRA30_CLK_TWD>; }; @@ -371,7 +371,7 @@ * driver and APB DMA based serial driver for higher baudrate * and performace. To enable the 8250 based driver, the compatible * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable - * the APB DMA based serial driver, the comptible is + * the APB DMA based serial driver, the compatible is * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". */ uarta: serial@70006000 { diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi index 55eb35f068fb..c45f97f37563 100644 --- a/arch/arm/boot/dts/twl6030.dtsi +++ b/arch/arm/boot/dts/twl6030.dtsi @@ -99,4 +99,10 @@ compatible = "ti,twl6030-pwmled"; #pwm-cells = <2>; }; + + gpadc { + compatible = "ti,twl6030-gpadc"; + interrupts = <3>; + #io-channel-cells = <1>; + }; }; diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi index 24592798a368..f2f3fbe2d517 100644 --- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi +++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi @@ -68,6 +68,16 @@ function = "i2c4"; }; + pinctrl_nand: nand_grp { + groups = "nand"; + function = "nand"; + }; + + pinctrl_nand2cs: nand2cs_grp { + groups = "nand", "nand_cs1"; + function = "nand"; + }; + pinctrl_uart0: uart0_grp { groups = "uart0"; function = "uart0"; diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index 7a556b92e55c..3086efacd00e 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -75,19 +75,19 @@ compatible = "arm,vexpress-sysreg"; reg = <0x010000 0x1000>; - v2m_led_gpios: sys_led@08 { + v2m_led_gpios: sys_led { compatible = "arm,vexpress-sysreg,sys_led"; gpio-controller; #gpio-cells = <2>; }; - v2m_mmc_gpios: sys_mci@48 { + v2m_mmc_gpios: sys_mci { compatible = "arm,vexpress-sysreg,sys_mci"; gpio-controller; #gpio-cells = <2>; }; - v2m_flash_gpios: sys_flash@4c { + v2m_flash_gpios: sys_flash { compatible = "arm,vexpress-sysreg,sys_flash"; gpio-controller; #gpio-cells = <2>; @@ -286,7 +286,7 @@ }; }; - v2m_fixed_3v3: fixedregulator@0 { + v2m_fixed_3v3: fixed-regulator-0 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; @@ -318,49 +318,49 @@ leds { compatible = "gpio-leds"; - user@1 { + user1 { label = "v2m:green:user1"; gpios = <&v2m_led_gpios 0 0>; linux,default-trigger = "heartbeat"; }; - user@2 { + user2 { label = "v2m:green:user2"; gpios = <&v2m_led_gpios 1 0>; linux,default-trigger = "mmc0"; }; - user@3 { + user3 { label = "v2m:green:user3"; gpios = <&v2m_led_gpios 2 0>; linux,default-trigger = "cpu0"; }; - user@4 { + user4 { label = "v2m:green:user4"; gpios = <&v2m_led_gpios 3 0>; linux,default-trigger = "cpu1"; }; - user@5 { + user5 { label = "v2m:green:user5"; gpios = <&v2m_led_gpios 4 0>; linux,default-trigger = "cpu2"; }; - user@6 { + user6 { label = "v2m:green:user6"; gpios = <&v2m_led_gpios 5 0>; linux,default-trigger = "cpu3"; }; - user@7 { + user7 { label = "v2m:green:user7"; gpios = <&v2m_led_gpios 6 0>; linux,default-trigger = "cpu4"; }; - user@8 { + user8 { label = "v2m:green:user8"; gpios = <&v2m_led_gpios 7 0>; linux,default-trigger = "cpu5"; @@ -371,7 +371,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - osc@0 { + oscclk0 { /* MCC static memory clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -380,7 +380,7 @@ clock-output-names = "v2m:oscclk0"; }; - v2m_oscclk1: osc@1 { + v2m_oscclk1: oscclk1 { /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -389,7 +389,7 @@ clock-output-names = "v2m:oscclk1"; }; - v2m_oscclk2: osc@2 { + v2m_oscclk2: oscclk2 { /* IO FPGA peripheral clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -398,7 +398,7 @@ clock-output-names = "v2m:oscclk2"; }; - volt@0 { + volt-vio { /* Logic level voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; @@ -407,34 +407,34 @@ label = "VIO"; }; - temp@0 { + temp-mcc { /* MCC internal operating temperature */ compatible = "arm,vexpress-temp"; arm,vexpress-sysreg,func = <4 0>; label = "MCC"; }; - reset@0 { + reset { compatible = "arm,vexpress-reset"; arm,vexpress-sysreg,func = <5 0>; }; - muxfpga@0 { + muxfpga { compatible = "arm,vexpress-muxfpga"; arm,vexpress-sysreg,func = <7 0>; }; - shutdown@0 { + shutdown { compatible = "arm,vexpress-shutdown"; arm,vexpress-sysreg,func = <8 0>; }; - reboot@0 { + reboot { compatible = "arm,vexpress-reboot"; arm,vexpress-sysreg,func = <9 0>; }; - dvimode@0 { + dvimode { compatible = "arm,vexpress-dvimode"; arm,vexpress-sysreg,func = <11 0>; }; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index 47e4a115adef..c6393d3f1719 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -74,19 +74,19 @@ compatible = "arm,vexpress-sysreg"; reg = <0x00000 0x1000>; - v2m_led_gpios: sys_led@08 { + v2m_led_gpios: sys_led { compatible = "arm,vexpress-sysreg,sys_led"; gpio-controller; #gpio-cells = <2>; }; - v2m_mmc_gpios: sys_mci@48 { + v2m_mmc_gpios: sys_mci { compatible = "arm,vexpress-sysreg,sys_mci"; gpio-controller; #gpio-cells = <2>; }; - v2m_flash_gpios: sys_flash@4c { + v2m_flash_gpios: sys_flash { compatible = "arm,vexpress-sysreg,sys_flash"; gpio-controller; #gpio-cells = <2>; @@ -285,7 +285,7 @@ }; }; - v2m_fixed_3v3: fixedregulator@0 { + v2m_fixed_3v3: fixed-regulator-0 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; @@ -317,49 +317,49 @@ leds { compatible = "gpio-leds"; - user@1 { + user1 { label = "v2m:green:user1"; gpios = <&v2m_led_gpios 0 0>; linux,default-trigger = "heartbeat"; }; - user@2 { + user2 { label = "v2m:green:user2"; gpios = <&v2m_led_gpios 1 0>; linux,default-trigger = "mmc0"; }; - user@3 { + user3 { label = "v2m:green:user3"; gpios = <&v2m_led_gpios 2 0>; linux,default-trigger = "cpu0"; }; - user@4 { + user4 { label = "v2m:green:user4"; gpios = <&v2m_led_gpios 3 0>; linux,default-trigger = "cpu1"; }; - user@5 { + user5 { label = "v2m:green:user5"; gpios = <&v2m_led_gpios 4 0>; linux,default-trigger = "cpu2"; }; - user@6 { + user6 { label = "v2m:green:user6"; gpios = <&v2m_led_gpios 5 0>; linux,default-trigger = "cpu3"; }; - user@7 { + user7 { label = "v2m:green:user7"; gpios = <&v2m_led_gpios 6 0>; linux,default-trigger = "cpu4"; }; - user@8 { + user8 { label = "v2m:green:user8"; gpios = <&v2m_led_gpios 7 0>; linux,default-trigger = "cpu5"; @@ -370,7 +370,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - osc@0 { + oscclk0 { /* MCC static memory clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -379,7 +379,7 @@ clock-output-names = "v2m:oscclk0"; }; - v2m_oscclk1: osc@1 { + v2m_oscclk1: oscclk1 { /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -388,7 +388,7 @@ clock-output-names = "v2m:oscclk1"; }; - v2m_oscclk2: osc@2 { + v2m_oscclk2: oscclk2 { /* IO FPGA peripheral clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -397,7 +397,7 @@ clock-output-names = "v2m:oscclk2"; }; - volt@0 { + volt-vio { /* Logic level voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; @@ -406,34 +406,34 @@ label = "VIO"; }; - temp@0 { + temp-mcc { /* MCC internal operating temperature */ compatible = "arm,vexpress-temp"; arm,vexpress-sysreg,func = <4 0>; label = "MCC"; }; - reset@0 { + reset { compatible = "arm,vexpress-reset"; arm,vexpress-sysreg,func = <5 0>; }; - muxfpga@0 { + muxfpga { compatible = "arm,vexpress-muxfpga"; arm,vexpress-sysreg,func = <7 0>; }; - shutdown@0 { + shutdown { compatible = "arm,vexpress-shutdown"; arm,vexpress-sysreg,func = <8 0>; }; - reboot@0 { + reboot { compatible = "arm,vexpress-reboot"; arm,vexpress-sysreg,func = <9 0>; }; - dvimode@0 { + dvimode { compatible = "arm,vexpress-dvimode"; arm,vexpress-sysreg,func = <11 0>; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts index 9420053acc14..102838fcc588 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts @@ -55,14 +55,14 @@ compatible = "arm,hdlcd"; reg = <0 0x2b000000 0 0x1000>; interrupts = <0 85 4>; - clocks = <&oscclk5>; + clocks = <&hdlcd_clk>; clock-names = "pxlclk"; }; memory-controller@2b0a0000 { compatible = "arm,pl341", "arm,primecell"; reg = <0 0x2b0a0000 0 0x1000>; - clocks = <&oscclk7>; + clocks = <&sys_pll>; clock-names = "apb_pclk"; }; @@ -71,7 +71,7 @@ status = "disabled"; reg = <0 0x2b060000 0 0x1000>; interrupts = <0 98 4>; - clocks = <&oscclk7>; + clocks = <&sys_pll>; clock-names = "apb_pclk"; }; @@ -92,7 +92,7 @@ reg = <0 0x7ffd0000 0 0x1000>; interrupts = <0 86 4>, <0 87 4>; - clocks = <&oscclk7>; + clocks = <&sys_pll>; clock-names = "apb_pclk"; }; @@ -104,7 +104,7 @@ <0 89 4>, <0 90 4>, <0 91 4>; - clocks = <&oscclk7>; + clocks = <&sys_pll>; clock-names = "apb_pclk"; }; @@ -126,7 +126,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - osc@0 { + oscclk0 { /* CPU PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -135,7 +135,7 @@ clock-output-names = "oscclk0"; }; - osc@4 { + oscclk4 { /* Multiplexed AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -144,7 +144,7 @@ clock-output-names = "oscclk4"; }; - oscclk5: osc@5 { + hdlcd_clk: oscclk5 { /* HDLCD PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; @@ -153,7 +153,7 @@ clock-output-names = "oscclk5"; }; - smbclk: osc@6 { + smbclk: oscclk6 { /* SMB clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 6>; @@ -162,7 +162,7 @@ clock-output-names = "oscclk6"; }; - oscclk7: osc@7 { + sys_pll: oscclk7 { /* SYS PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 7>; @@ -171,7 +171,7 @@ clock-output-names = "oscclk7"; }; - osc@8 { + oscclk8 { /* DDR2 PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 8>; @@ -180,7 +180,7 @@ clock-output-names = "oscclk8"; }; - volt@0 { + volt-cores { /* CPU core voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; @@ -191,28 +191,28 @@ label = "Cores"; }; - amp@0 { + amp-cores { /* Total current for the two cores */ compatible = "arm,vexpress-amp"; arm,vexpress-sysreg,func = <3 0>; label = "Cores"; }; - temp@0 { + temp-dcc { /* DCC internal temperature */ compatible = "arm,vexpress-temp"; arm,vexpress-sysreg,func = <4 0>; label = "DCC"; }; - power@0 { + power-cores { /* Total power */ compatible = "arm,vexpress-power"; arm,vexpress-sysreg,func = <12 0>; label = "Cores"; }; - energy@0 { + energy { /* Total energy */ compatible = "arm,vexpress-energy"; arm,vexpress-sysreg,func = <13 0>; @@ -220,7 +220,7 @@ }; }; - smb { + smb@08000000 { compatible = "simple-bus"; #address-cells = <2>; @@ -280,4 +280,17 @@ /include/ "vexpress-v2m-rs1.dtsi" }; + + site2: hsb@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x3fef0000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 3>; + interrupt-map = <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index 17f63f7dfd9e..0205c97efdef 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -109,7 +109,7 @@ compatible = "arm,hdlcd"; reg = <0 0x2b000000 0 0x1000>; interrupts = <0 85 4>; - clocks = <&oscclk5>; + clocks = <&hdlcd_clk>; clock-names = "pxlclk"; }; @@ -227,7 +227,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - osc@0 { + oscclk0 { /* A15 PLL 0 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -236,7 +236,7 @@ clock-output-names = "oscclk0"; }; - osc@1 { + oscclk1 { /* A15 PLL 1 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -245,7 +245,7 @@ clock-output-names = "oscclk1"; }; - osc@2 { + oscclk2 { /* A7 PLL 0 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -254,7 +254,7 @@ clock-output-names = "oscclk2"; }; - osc@3 { + oscclk3 { /* A7 PLL 1 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 3>; @@ -263,7 +263,7 @@ clock-output-names = "oscclk3"; }; - osc@4 { + oscclk4 { /* External AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -272,7 +272,7 @@ clock-output-names = "oscclk4"; }; - oscclk5: osc@5 { + hdlcd_clk: oscclk5 { /* HDLCD PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; @@ -281,7 +281,7 @@ clock-output-names = "oscclk5"; }; - smbclk: osc@6 { + smbclk: oscclk6 { /* Static memory controller clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 6>; @@ -290,7 +290,7 @@ clock-output-names = "oscclk6"; }; - osc@7 { + oscclk7 { /* SYS PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 7>; @@ -299,7 +299,7 @@ clock-output-names = "oscclk7"; }; - osc@8 { + oscclk8 { /* DDR2 PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 8>; @@ -308,7 +308,7 @@ clock-output-names = "oscclk8"; }; - volt@0 { + volt-a15 { /* A15 CPU core voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; @@ -319,7 +319,7 @@ label = "A15 Vcore"; }; - volt@1 { + volt-a7 { /* A7 CPU core voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 1>; @@ -330,49 +330,49 @@ label = "A7 Vcore"; }; - amp@0 { + amp-a15 { /* Total current for the two A15 cores */ compatible = "arm,vexpress-amp"; arm,vexpress-sysreg,func = <3 0>; label = "A15 Icore"; }; - amp@1 { + amp-a7 { /* Total current for the three A7 cores */ compatible = "arm,vexpress-amp"; arm,vexpress-sysreg,func = <3 1>; label = "A7 Icore"; }; - temp@0 { + temp-dcc { /* DCC internal temperature */ compatible = "arm,vexpress-temp"; arm,vexpress-sysreg,func = <4 0>; label = "DCC"; }; - power@0 { + power-a15 { /* Total power for the two A15 cores */ compatible = "arm,vexpress-power"; arm,vexpress-sysreg,func = <12 0>; label = "A15 Pcore"; }; - power@1 { + power-a7 { /* Total power for the three A7 cores */ compatible = "arm,vexpress-power"; arm,vexpress-sysreg,func = <12 1>; label = "A7 Pcore"; }; - energy@0 { + energy-a15 { /* Total energy for the two A15 cores */ compatible = "arm,vexpress-energy"; arm,vexpress-sysreg,func = <13 0>, <13 1>; label = "A15 Jcore"; }; - energy@2 { + energy-a7 { /* Total energy for the three A7 cores */ compatible = "arm,vexpress-energy"; arm,vexpress-sysreg,func = <13 2>, <13 3>; @@ -387,7 +387,7 @@ clocks = <&oscclk6a>; clock-names = "apb_pclk"; port { - etb_in_port: endpoint@0 { + etb_in_port: endpoint { slave-mode; remote-endpoint = <&replicator_out_port0>; }; @@ -401,7 +401,7 @@ clocks = <&oscclk6a>; clock-names = "apb_pclk"; port { - tpiu_in_port: endpoint@0 { + tpiu_in_port: endpoint { slave-mode; remote-endpoint = <&replicator_out_port1>; }; @@ -578,7 +578,7 @@ }; }; - smb { + smb@08000000 { compatible = "simple-bus"; #address-cells = <2>; @@ -638,4 +638,17 @@ /include/ "vexpress-v2m-rs1.dtsi" }; + + site2: hsb@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x40000000 0x3fef0000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 3>; + interrupt-map = <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts index d2709b73316b..1acecaf4b13d 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts @@ -57,14 +57,14 @@ compatible = "arm,hdlcd"; reg = <0x2a110000 0x1000>; interrupts = <0 85 4>; - clocks = <&oscclk3>; + clocks = <&hdlcd_clk>; clock-names = "pxlclk"; }; memory-controller@2a150000 { compatible = "arm,pl341", "arm,primecell"; reg = <0x2a150000 0x1000>; - clocks = <&oscclk1>; + clocks = <&axi_clk>; clock-names = "apb_pclk"; }; @@ -73,7 +73,7 @@ reg = <0x2a190000 0x1000>; interrupts = <0 86 4>, <0 87 4>; - clocks = <&oscclk1>; + clocks = <&axi_clk>; clock-names = "apb_pclk"; }; @@ -93,7 +93,7 @@ "arm,cortex-a9-global-timer"; reg = <0x2c000200 0x20>; interrupts = <1 11 0x304>; - clocks = <&oscclk0>; + clocks = <&cpu_clk>; }; watchdog@2c000620 { @@ -128,7 +128,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0: osc@0 { + cpu_clk: oscclk0 { /* CPU and internal AXI reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -137,7 +137,7 @@ clock-output-names = "oscclk0"; }; - oscclk1: osc@1 { + axi_clk: oscclk1 { /* Multiplexed AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -146,7 +146,7 @@ clock-output-names = "oscclk1"; }; - osc@2 { + oscclk2 { /* DDR2 */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -155,7 +155,7 @@ clock-output-names = "oscclk2"; }; - oscclk3: osc@3 { + hdlcd_clk: oscclk3 { /* HDLCD */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 3>; @@ -164,7 +164,7 @@ clock-output-names = "oscclk3"; }; - osc@4 { + oscclk4 { /* Test chip gate configuration */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -173,7 +173,7 @@ clock-output-names = "oscclk4"; }; - smbclk: osc@5 { + smbclk: oscclk5 { /* SMB clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; @@ -182,7 +182,7 @@ clock-output-names = "oscclk5"; }; - temp@0 { + temp-dcc { /* DCC internal operating temperature */ compatible = "arm,vexpress-temp"; arm,vexpress-sysreg,func = <4 0>; @@ -190,7 +190,7 @@ }; }; - smb { + smb@08000000 { compatible = "simple-bus"; #address-cells = <2>; @@ -250,4 +250,17 @@ /include/ "vexpress-v2m-rs1.dtsi" }; + + site2: hsb@40000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x40000000 0x40000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 3>; + interrupt-map = <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index d949facba376..b608a03ee02f 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -190,7 +190,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - osc@0 { + oscclk0: extsaxiclk { /* ACLK clock to the AXI master port on the test chip */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -199,7 +199,7 @@ clock-output-names = "extsaxiclk"; }; - oscclk1: osc@1 { + oscclk1: clcdclk { /* Reference clock for the CLCD */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -208,7 +208,7 @@ clock-output-names = "clcdclk"; }; - smbclk: oscclk2: osc@2 { + smbclk: oscclk2: tcrefclk { /* Reference clock for the test chip internal PLLs */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -217,7 +217,7 @@ clock-output-names = "tcrefclk"; }; - volt@0 { + volt-vd10 { /* Test Chip internal logic voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; @@ -226,7 +226,7 @@ label = "VD10"; }; - volt@1 { + volt-vd10-s2 { /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 1>; @@ -235,7 +235,7 @@ label = "VD10_S2"; }; - volt@2 { + volt-vd10-s3 { /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 2>; @@ -244,7 +244,7 @@ label = "VD10_S3"; }; - volt@3 { + volt-vcc1v8 { /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 3>; @@ -253,7 +253,7 @@ label = "VCC1V8"; }; - volt@4 { + volt-ddr2vtt { /* DDR2 SDRAM VTT termination voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 4>; @@ -262,7 +262,7 @@ label = "DDR2VTT"; }; - volt@5 { + volt-vcc3v3 { /* Local board supply for miscellaneous logic external to the Test Chip */ arm,vexpress-sysreg,func = <2 5>; compatible = "arm,vexpress-volt"; @@ -271,28 +271,28 @@ label = "VCC3V3"; }; - amp@0 { + amp-vd10-s2 { /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ compatible = "arm,vexpress-amp"; arm,vexpress-sysreg,func = <3 0>; label = "VD10_S2"; }; - amp@1 { + amp-vd10-s3 { /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ compatible = "arm,vexpress-amp"; arm,vexpress-sysreg,func = <3 1>; label = "VD10_S3"; }; - power@0 { + power-vd10-s2 { /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ compatible = "arm,vexpress-power"; arm,vexpress-sysreg,func = <12 0>; label = "PVD10_S2"; }; - power@1 { + power-vd10-s3 { /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ compatible = "arm,vexpress-power"; arm,vexpress-sysreg,func = <12 1>; @@ -300,7 +300,7 @@ }; }; - smb { + smb@04000000 { compatible = "simple-bus"; #address-cells = <2>; @@ -359,4 +359,17 @@ /include/ "vexpress-v2m.dtsi" }; + + site2: hsb@e0000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe0000000 0x20000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 3>; + interrupt-map = <0 0 &gic 0 36 4>, + <0 1 &gic 0 37 4>, + <0 2 &gic 0 38 4>, + <0 3 &gic 0 39 4>; + }; }; diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi index fda7f28101e1..226a86ffd3c9 100644 --- a/arch/arm/boot/dts/vf-colibri.dtsi +++ b/arch/arm/boot/dts/vf-colibri.dtsi @@ -40,6 +40,11 @@ */ / { + aliases { + ethernet0 = &fec1; + ethernet1 = &fec0; + }; + bl: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; @@ -125,8 +130,6 @@ }; &nfc { - assigned-clocks = <&clks VF610_CLK_NFC>; - assigned-clock-rates = <33000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_nfc>; status = "okay"; diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi index 3fe1f48c2aec..1a8a0efa19a6 100644 --- a/arch/arm/boot/dts/vf500-colibri.dtsi +++ b/arch/arm/boot/dts/vf500-colibri.dtsi @@ -69,6 +69,11 @@ }; }; +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <33000000>; +}; + &iomuxc { vf610-colibri { pinctrl_touchctrl_idle: touchctrl_idle { diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi index 9d372720ad3f..a3824e61bd72 100644 --- a/arch/arm/boot/dts/vf500.dtsi +++ b/arch/arm/boot/dts/vf500.dtsi @@ -81,6 +81,7 @@ compatible = "arm,cortex-a5-pmu"; interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&a5_cpu>; + reg = <0x40089000 0x1000>; }; }; diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi index ab4a29f95593..9ec9e337f5a8 100644 --- a/arch/arm/boot/dts/vf610-colibri.dtsi +++ b/arch/arm/boot/dts/vf610-colibri.dtsi @@ -50,3 +50,8 @@ reg = <0x80000000 0x10000000>; }; }; + +&nfc { + assigned-clocks = <&clks VF610_CLK_NFC>; + assigned-clock-rates = <50000000>; +}; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts new file mode 100644 index 000000000000..6c60b7f91104 --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -0,0 +1,734 @@ +/* + * Copyright (C) 2015, 2016 Zodiac Inflight Innovations + * + * Based on an original 'vf610-twr.dts' which is Copyright 2015, + * Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 Development Board, Rev B"; + compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + debug { + label = "zii:green:debug1"; + gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + mdio-mux { + compatible = "mdio-mux-gpio"; + pinctrl-0 = <&pinctrl_mdio_mux>; + pinctrl-names = "default"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH + &gpio0 9 GPIO_ACTIVE_HIGH + &gpio0 24 GPIO_ACTIVE_HIGH + &gpio0 25 GPIO_ACTIVE_HIGH>; + mdio-parent-bus = <&mdio1>; + #address-cells = <1>; + #size-cells = <0>; + + mdio_mux_1: mdio@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio_mux_2: mdio@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio_mux_4: mdio@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio_mux_8: mdio@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + dsa { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + dsa,ethernet = <&fec1>; + dsa,mii-bus = <&mdio_mux_1>; + + /* 6352 - Primary - 7 ports */ + switch0: switch@0-0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00 0>; + eeprom-length = <512>; + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + switch0port5: port@5 { + reg = <5>; + label = "dsa"; + phy-mode = "rgmii-txid"; + link = <&switch1port6 + &switch2port9>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "cpu"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + }; + + /* 6352 - Secondary - 7 ports */ + switch1: switch@0-1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00 1>; + eeprom-length = <512>; + mii-bus = <&mdio_mux_2>; + + port@0 { + reg = <0>; + label = "lan3"; + }; + + port@1 { + reg = <1>; + label = "lan4"; + }; + + port@2 { + reg = <2>; + label = "lan5"; + }; + + switch1port5: port@5 { + reg = <5>; + label = "dsa"; + link = <&switch2port9>; + phy-mode = "rgmii-txid"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + switch1port6: port@6 { + reg = <6>; + label = "dsa"; + phy-mode = "rgmii-txid"; + link = <&switch0port5>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + + /* 6185 - 10 ports */ + switch2: switch@0-2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x00 2>; + mii-bus = <&mdio_mux_4>; + + port@0 { + reg = <0>; + label = "lan6"; + }; + + port@1 { + reg = <1>; + label = "lan7"; + }; + + port@2 { + reg = <2>; + label = "lan8"; + }; + + port@3 { + reg = <3>; + label = "optical3"; + + fixed-link { + speed = <1000>; + full-duplex; + link-gpios = <&gpio6 2 + GPIO_ACTIVE_HIGH>; + }; + }; + + port@4 { + reg = <4>; + label = "optical4"; + + fixed-link { + speed = <1000>; + full-duplex; + link-gpios = <&gpio6 3 + GPIO_ACTIVE_HIGH>; + }; + }; + + switch2port9: port@9 { + reg = <9>; + label = "dsa"; + phy-mode = "rgmii-txid"; + link = <&switch1port5 + &switch0port5>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-0 = <&pinctrl_usb_vbus>; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 6 0>; + }; + + spi0 { + compatible = "spi-gpio"; + pinctrl-0 = <&pinctrl_gpio_spi0>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH + &gpio1 8 GPIO_ACTIVE_HIGH>; + num-chipselects = <2>; + + m25p128@0 { + compatible = "m25p128", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + at93c46d@1 { + compatible = "atmel,at93c46d"; + pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>; + pinctrl-names = "default"; + #address-cells = <0>; + #size-cells = <0>; + reg = <1>; + spi-max-frequency = <500000>; + spi-cs-high; + data-size = <16>; + select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_ad5>; + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&edma0 { + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec0 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec0>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + gpio5: pca9554@20 { + compatible = "nxp,pca9554"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + + }; + + gpio6: pca9554@22 { + compatible = "nxp,pca9554"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9554_22>; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio2>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + }; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + at24c04@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + }; + + at24c04@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; + + ds1682@6b { + compatible = "dallas,ds1682"; + reg = <0x6b>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + tca9548@70 { + compatible = "nxp,pca9548"; + pinctrl-0 = <&pinctrl_i2c_mux_reset>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + sfp1: at24c04@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + sfp2: at24c04@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + sfp3: at24c04@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + sfp4: at24c04@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbdev0 { + disable-over-current; + vbus-supply = <&usb0_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbmisc0 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_adc0_ad5: adc0ad5grp { + fsl,pins = < + VF610_PAD_PTC30__ADC0_SE5 0x00a1 + >; + }; + + pinctrl_dspi0: dspi0grp { + fsl,pins = < + VF610_PAD_PTB18__DSPI0_CS1 0x1182 + VF610_PAD_PTB19__DSPI0_CS0 0x1182 + VF610_PAD_PTB20__DSPI0_SIN 0x1181 + VF610_PAD_PTB21__DSPI0_SOUT 0x1182 + VF610_PAD_PTB22__DSPI0_SCK 0x1182 + >; + }; + + pinctrl_dspi2: dspi2grp { + fsl,pins = < + VF610_PAD_PTD31__DSPI2_CS1 0x1182 + VF610_PAD_PTD30__DSPI2_CS0 0x1182 + VF610_PAD_PTD29__DSPI2_SIN 0x1181 + VF610_PAD_PTD28__DSPI2_SOUT 0x1182 + VF610_PAD_PTD27__DSPI2_SCK 0x1182 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTA7__GPIO_134 0x219d + >; + }; + + pinctrl_fec0: fec0grp { + fsl,pins = < + VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d2 + VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d3 + VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1 + VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1 + VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1 + VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1 + VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2 + VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2 + VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 { + fsl,pins = < + VF610_PAD_PTE27__GPIO_132 0x33e2 + >; + }; + + pinctrl_gpio_spi0: pinctrl-gpio-spi0 { + fsl,pins = < + VF610_PAD_PTB22__GPIO_44 0x33e2 + VF610_PAD_PTB21__GPIO_43 0x33e2 + VF610_PAD_PTB20__GPIO_42 0x33e1 + VF610_PAD_PTB19__GPIO_41 0x33e2 + VF610_PAD_PTB18__GPIO_40 0x33e2 + >; + }; + + pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset { + fsl,pins = < + VF610_PAD_PTE14__GPIO_119 0x31c2 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + VF610_PAD_PTA22__I2C2_SCL 0x37ff + VF610_PAD_PTA23__I2C2_SDA 0x37ff + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + VF610_PAD_PTA30__I2C3_SCL 0x37ff + VF610_PAD_PTA31__I2C3_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD20__GPIO_74 0x31c2 + >; + }; + + pinctrl_mdio_mux: pinctrl-mdio-mux { + fsl,pins = < + VF610_PAD_PTA18__GPIO_8 0x31c2 + VF610_PAD_PTA19__GPIO_9 0x31c2 + VF610_PAD_PTB2__GPIO_24 0x31c2 + VF610_PAD_PTB3__GPIO_25 0x31c2 + >; + }; + + pinctrl_pca9554_22: pinctrl-pca95540-22 { + fsl,pins = < + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_pwm0: pwm0grp { + fsl,pins = < + VF610_PAD_PTB0__FTM0_CH0 0x1582 + VF610_PAD_PTB1__FTM0_CH1 0x1582 + VF610_PAD_PTB2__FTM0_CH2 0x1582 + VF610_PAD_PTB3__FTM0_CH3 0x1582 + >; + }; + + pinctrl_qspi0: qspi0grp { + fsl,pins = < + VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3 + VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff + VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3 + VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3 + VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3 + VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + >; + }; + + pinctrl_usb_vbus: pinctrl-usb-vbus { + fsl,pins = < + VF610_PAD_PTA16__GPIO_6 0x31c2 + >; + }; + + pinctrl_usb0_host: usb0-host-grp { + fsl,pins = < + VF610_PAD_PTD6__GPIO_85 0x0062 + >; + }; +}; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index 5c0975451d4e..04ef54d45a91 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -95,6 +95,7 @@ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; + reg = <0x40000000 0x00070000>; ranges; mscm_cpucfg: cpucfg@40001000 { @@ -481,6 +482,7 @@ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; #size-cells = <1>; + reg = <0x40080000 0x0007f000>; ranges; edma1: dma-controller@40098000 { diff --git a/arch/arm/boot/dts/wd-mbwe.dts b/arch/arm/boot/dts/wd-mbwe.dts new file mode 100644 index 000000000000..ac3250ae8fc4 --- /dev/null +++ b/arch/arm/boot/dts/wd-mbwe.dts @@ -0,0 +1,112 @@ +/* + * wd-mbwe.dtsi - Device tree file for Western Digital My Book World Edition + * + * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com> + * + * Licensed under GPLv2 or later + */ + +/dts-v1/; +#include "ox810se.dtsi" + +/ { + model = "Western Digital My Book World Edition"; + + compatible = "wd,mbwe", "oxsemi,ox810se"; + + chosen { + bootargs = "console=ttyS1,115200n8 earlyprintk=serial"; + }; + + memory { + /* 128Mbytes DDR */ + reg = <0x48000000 0x8000000>; + }; + + aliases { + serial1 = &uart1; + gpio0 = &gpio0; + gpio1 = &gpio1; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + + power { + label = "power"; + gpios = <&gpio0 0 1>; + linux,code = <0x198>; + }; + + recovery { + label = "recovery"; + gpios = <&gpio0 4 1>; + linux,code = <0xab>; + }; + }; + + leds { + compatible = "gpio-leds"; + + a0 { + label = "activity0"; + gpios = <&gpio0 25 0>; + default-state = "keep"; + }; + + a1 { + label = "activity1"; + gpios = <&gpio0 26 0>; + default-state = "keep"; + }; + + a2 { + label = "activity2"; + gpios = <&gpio0 5 0>; + default-state = "keep"; + }; + + a3 { + label = "activity3"; + gpios = <&gpio0 6 0>; + default-state = "keep"; + }; + + a4 { + label = "activity4"; + gpios = <&gpio0 7 0>; + default-state = "keep"; + }; + + a5 { + label = "activity5"; + gpios = <&gpio1 2 0>; + default-state = "keep"; + }; + }; + + i2c-gpio { + compatible = "i2c-gpio"; + gpios = <&gpio0 3 0 /* sda */ + &gpio0 2 0 /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + + rtc0: rtc@48 { + compatible = "st,m41t00"; + reg = <0x68>; + }; + }; +}; + +&uart1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index fac6d43e7fdb..754f478110b4 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -20,6 +20,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,davinci-i2c", 0x01c22000, "i2c_davinci.1", NULL), + OF_DEV_AUXDATA("ti,davinci-i2c", 0x01e28000, "i2c_davinci.2", NULL), OF_DEV_AUXDATA("ti,davinci-wdt", 0x01c21000, "davinci-wdt", NULL), OF_DEV_AUXDATA("ti,da830-mmc", 0x01c40000, "da830-mmc.0", NULL), OF_DEV_AUXDATA("ti,da850-ehrpwm", 0x01f00000, "ehrpwm", NULL), @@ -27,6 +28,7 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("ti,da850-ecap", 0x01f06000, "ecap", NULL), OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL), OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL), + OF_DEV_AUXDATA("ti,da830-spi", 0x01c41000, "spi_davinci.0", NULL), OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL), OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL), OF_DEV_AUXDATA("ns16550a", 0x01d0c000, "serial8250.1", NULL), diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 706d2426024f..eb0ce7b09617 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -115,6 +115,14 @@ clock-frequency = <0>; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + status = "disabled"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; @@ -514,6 +522,36 @@ #size-cells = <0>; }; + can0: can@e6c30000 { + compatible = "renesas,can-r8a7795", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&cpg>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a7795", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&cpg>; + status = "disabled"; + }; + hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a7795", "renesas,rcar-gen3-hscif", @@ -943,7 +981,7 @@ }; xhci0: usb@ee000000 { - compatible = "renesas,xhci-r8a7795"; + compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; reg = <0 0xee000000 0 0xc00>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 328>; @@ -952,7 +990,7 @@ }; xhci1: usb@ee0400000 { - compatible = "renesas,xhci-r8a7795"; + compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; reg = <0 0xee040000 0 0xc00>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg CPG_MOD 327>; diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c index fdd41b17a24f..16575ee874cb 100644 --- a/drivers/clk/samsung/clk-exynos3250.c +++ b/drivers/clk/samsung/clk-exynos3250.c @@ -302,10 +302,12 @@ static struct samsung_mux_clock mux_clks[] __initdata = { /* SRC_FSYS */ MUX(CLK_MOUT_TSADC, "mout_tsadc", group_sclk_p, SRC_FSYS, 28, 4), + MUX(CLK_MOUT_MMC2, "mout_mmc2", group_sclk_p, SRC_FSYS, 8, 4), MUX(CLK_MOUT_MMC1, "mout_mmc1", group_sclk_p, SRC_FSYS, 4, 4), MUX(CLK_MOUT_MMC0, "mout_mmc0", group_sclk_p, SRC_FSYS, 0, 4), /* SRC_PERIL0 */ + MUX(CLK_MOUT_UART2, "mout_uart2", group_sclk_p, SRC_PERIL0, 8, 4), MUX(CLK_MOUT_UART1, "mout_uart1", group_sclk_p, SRC_PERIL0, 4, 4), MUX(CLK_MOUT_UART0, "mout_uart0", group_sclk_p, SRC_PERIL0, 0, 4), @@ -389,7 +391,13 @@ static struct samsung_div_clock div_clks[] __initdata = { CLK_SET_RATE_PARENT, 0), DIV(CLK_DIV_MMC0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4), + /* DIV_FSYS2 */ + DIV_F(CLK_DIV_MMC2_PRE, "div_mmc2_pre", "div_mmc2", DIV_FSYS2, 8, 8, + CLK_SET_RATE_PARENT, 0), + DIV(CLK_DIV_MMC2, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4), + /* DIV_PERIL0 */ + DIV(CLK_DIV_UART2, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), DIV(CLK_DIV_UART1, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), DIV(CLK_DIV_UART0, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), @@ -538,6 +546,8 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_EBI, "sclk_ebi", "div_ebi", GATE_SCLK_FSYS, 6, CLK_SET_RATE_PARENT, 0), + GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc2_pre", + GATE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc1_pre", GATE_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc0_pre", @@ -552,6 +562,9 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE_SCLK_PERIL, 7, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_SPI0, "sclk_spi0", "div_spi0_pre", GATE_SCLK_PERIL, 6, CLK_SET_RATE_PARENT, 0), + + GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2", + GATE_SCLK_PERIL, 2, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1", GATE_SCLK_PERIL, 1, CLK_SET_RATE_PARENT, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", @@ -630,6 +643,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_USBOTG, "usbotg", "div_aclk_200", GATE_IP_FSYS, 13, 0, 0), GATE(CLK_USBHOST, "usbhost", "div_aclk_200", GATE_IP_FSYS, 12, 0, 0), GATE(CLK_SROMC, "sromc", "div_aclk_200", GATE_IP_FSYS, 11, 0, 0), + GATE(CLK_SDMMC2, "sdmmc2", "div_aclk_200", GATE_IP_FSYS, 7, 0, 0), GATE(CLK_SDMMC1, "sdmmc1", "div_aclk_200", GATE_IP_FSYS, 6, 0, 0), GATE(CLK_SDMMC0, "sdmmc0", "div_aclk_200", GATE_IP_FSYS, 5, 0, 0), GATE(CLK_PDMA1, "pdma1", "div_aclk_200", GATE_IP_FSYS, 1, 0, 0), @@ -649,6 +663,7 @@ static struct samsung_gate_clock gate_clks[] __initdata = { GATE(CLK_I2C2, "i2c2", "div_aclk_100", GATE_IP_PERIL, 8, 0, 0), GATE(CLK_I2C1, "i2c1", "div_aclk_100", GATE_IP_PERIL, 7, 0, 0), GATE(CLK_I2C0, "i2c0", "div_aclk_100", GATE_IP_PERIL, 6, 0, 0), + GATE(CLK_UART2, "uart2", "div_aclk_100", GATE_IP_PERIL, 2, 0, 0), GATE(CLK_UART1, "uart1", "div_aclk_100", GATE_IP_PERIL, 1, 0, 0), GATE(CLK_UART0, "uart0", "div_aclk_100", GATE_IP_PERIL, 0, 0, 0), }; diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c index a911d7de3377..6b5a309d9939 100644 --- a/drivers/clk/ti/clk-7xx.c +++ b/drivers/clk/ti/clk-7xx.c @@ -223,7 +223,7 @@ static struct ti_dt_clk dra7xx_clks[] = { DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "mcasp6_aux_gfclk_mux"), DT_CLK(NULL, "mcasp7_ahclkx_mux", "mcasp7_ahclkx_mux"), DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "mcasp7_aux_gfclk_mux"), - DT_CLK(NULL, "mcasp8_ahclk_mux", "mcasp8_ahclk_mux"), + DT_CLK(NULL, "mcasp8_ahclkx_mux", "mcasp8_ahclkx_mux"), DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "mcasp8_aux_gfclk_mux"), DT_CLK(NULL, "mmc1_fclk_mux", "mmc1_fclk_mux"), DT_CLK(NULL, "mmc1_fclk_div", "mmc1_fclk_div"), diff --git a/drivers/gpu/drm/vc4/vc4_drv.c b/drivers/gpu/drm/vc4/vc4_drv.c index b7d2ff0e6e1f..109b10651959 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.c +++ b/drivers/gpu/drm/vc4/vc4_drv.c @@ -153,6 +153,24 @@ static void vc4_match_add_drivers(struct device *dev, } } +static void vc4_kick_out_firmware_fb(void) +{ + struct apertures_struct *ap; + + ap = alloc_apertures(1); + if (!ap) + return; + + /* Since VC4 is a UMA device, the simplefb node may have been + * located anywhere in memory. + */ + ap->ranges[0].base = 0; + ap->ranges[0].size = ~0; + + remove_conflicting_framebuffers(ap, "vc4drmfb", false); + kfree(ap); +} + static int vc4_drm_bind(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); @@ -186,6 +204,8 @@ static int vc4_drm_bind(struct device *dev) if (ret) goto gem_destroy; + vc4_kick_out_firmware_fb(); + ret = drm_dev_register(drm, 0); if (ret < 0) goto unbind_all; diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index d0c3c3e085e3..03089ad2fc65 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -31,7 +31,6 @@ config ARCH_TEGRA_3x_SOC config ARCH_TEGRA_114_SOC bool "Enable support for Tegra114 family" select ARM_ERRATA_798181 if SMP - select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA114 select TEGRA_TIMER @@ -41,7 +40,6 @@ config ARCH_TEGRA_114_SOC config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" - select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER select PINCTRL_TEGRA124 select TEGRA_TIMER diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h index 63d01c15d2b3..c796ff02ceeb 100644 --- a/include/dt-bindings/clock/exynos3250.h +++ b/include/dt-bindings/clock/exynos3250.h @@ -79,6 +79,8 @@ #define CLK_MOUT_CORE 58 #define CLK_MOUT_APLL 59 #define CLK_MOUT_ACLK_266_SUB 60 +#define CLK_MOUT_UART2 61 +#define CLK_MOUT_MMC2 62 /* Dividers */ #define CLK_DIV_GPL 64 @@ -127,6 +129,9 @@ #define CLK_DIV_CORE 107 #define CLK_DIV_HPM 108 #define CLK_DIV_COPY 109 +#define CLK_DIV_UART2 110 +#define CLK_DIV_MMC2_PRE 111 +#define CLK_DIV_MMC2 112 /* Gates */ #define CLK_ASYNC_G3D 128 @@ -223,6 +228,8 @@ #define CLK_BLOCK_MFC 219 #define CLK_BLOCK_CAM 220 #define CLK_SMIES 221 +#define CLK_UART2 222 +#define CLK_SDMMC2 223 /* Special clocks */ #define CLK_SCLK_JPEG 224 @@ -249,12 +256,14 @@ #define CLK_SCLK_SPI0 245 #define CLK_SCLK_UART1 246 #define CLK_SCLK_UART0 247 +#define CLK_SCLK_UART2 248 +#define CLK_SCLK_MMC2 249 /* * Total number of clocks of main CMU. * NOTE: Must be equal to last clock ID increased by one. */ -#define CLK_NR_CLKS 248 +#define CLK_NR_CLKS 250 /* * CMU DMC diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index 7b1ad8922eec..fa5e8da809f2 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -66,6 +66,7 @@ #define R8A7790_CLK_IIC2 0 #define R8A7790_CLK_TPU0 4 #define R8A7790_CLK_MMCIF1 5 +#define R8A7790_CLK_SCIF2 10 #define R8A7790_CLK_SDHI3 11 #define R8A7790_CLK_SDHI2 12 #define R8A7790_CLK_SDHI1 13 diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index f843de6bf377..4d3ecd626c1f 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -21,6 +21,7 @@ #define R8A7794_CLK_SDH 6 #define R8A7794_CLK_SD0 7 #define R8A7794_CLK_Z 8 +#define R8A7794_CLK_RCAN 9 /* MSTP0 */ #define R8A7794_CLK_MSIOF0 0 @@ -56,6 +57,8 @@ #define R8A7794_CLK_SDHI1 12 #define R8A7794_CLK_SDHI0 14 #define R8A7794_CLK_MMCIF0 15 +#define R8A7794_CLK_IIC0 18 +#define R8A7794_CLK_IIC1 23 #define R8A7794_CLK_CMT1 29 #define R8A7794_CLK_USBDMAC0 30 #define R8A7794_CLK_USBDMAC1 31 @@ -95,6 +98,8 @@ #define R8A7794_CLK_GPIO2 10 #define R8A7794_CLK_GPIO1 11 #define R8A7794_CLK_GPIO0 12 +#define R8A7794_CLK_RCAN1 15 +#define R8A7794_CLK_RCAN0 16 #define R8A7794_CLK_QSPI_MOD 17 #define R8A7794_CLK_I2C5 25 #define R8A7794_CLK_I2C4 27 diff --git a/include/dt-bindings/power/r8a7779-sysc.h b/include/dt-bindings/power/r8a7779-sysc.h new file mode 100644 index 000000000000..183571da507e --- /dev/null +++ b/include/dt-bindings/power/r8a7779-sysc.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7779_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7779_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7779_PD_ARM1 1 +#define R8A7779_PD_ARM2 2 +#define R8A7779_PD_ARM3 3 +#define R8A7779_PD_SGX 20 +#define R8A7779_PD_VDP 21 +#define R8A7779_PD_IMP 24 + +/* Always-on power area */ +#define R8A7779_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7779_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a7790-sysc.h b/include/dt-bindings/power/r8a7790-sysc.h new file mode 100644 index 000000000000..6af4e9929bd0 --- /dev/null +++ b/include/dt-bindings/power/r8a7790-sysc.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7790_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7790_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7790_PD_CA15_CPU0 0 +#define R8A7790_PD_CA15_CPU1 1 +#define R8A7790_PD_CA15_CPU2 2 +#define R8A7790_PD_CA15_CPU3 3 +#define R8A7790_PD_CA7_CPU0 5 +#define R8A7790_PD_CA7_CPU1 6 +#define R8A7790_PD_CA7_CPU2 7 +#define R8A7790_PD_CA7_CPU3 8 +#define R8A7790_PD_CA15_SCU 12 +#define R8A7790_PD_SH_4A 16 +#define R8A7790_PD_RGX 20 +#define R8A7790_PD_CA7_SCU 21 +#define R8A7790_PD_IMP 24 + +/* Always-on power area */ +#define R8A7790_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7790_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a7791-sysc.h b/include/dt-bindings/power/r8a7791-sysc.h new file mode 100644 index 000000000000..1403baa0514f --- /dev/null +++ b/include/dt-bindings/power/r8a7791-sysc.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7791_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7791_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7791_PD_CA15_CPU0 0 +#define R8A7791_PD_CA15_CPU1 1 +#define R8A7791_PD_CA15_SCU 12 +#define R8A7791_PD_SH_4A 16 +#define R8A7791_PD_SGX 20 + +/* Always-on power area */ +#define R8A7791_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7791_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a7793-sysc.h b/include/dt-bindings/power/r8a7793-sysc.h new file mode 100644 index 000000000000..b5693df3d830 --- /dev/null +++ b/include/dt-bindings/power/r8a7793-sysc.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7793_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7793_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + * + * Note that R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. + */ + +#define R8A7793_PD_CA15_CPU0 0 +#define R8A7793_PD_CA15_CPU1 1 +#define R8A7793_PD_CA15_SCU 12 +#define R8A7793_PD_SH_4A 16 +#define R8A7793_PD_SGX 20 + +/* Always-on power area */ +#define R8A7793_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7793_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a7794-sysc.h b/include/dt-bindings/power/r8a7794-sysc.h new file mode 100644 index 000000000000..862241c2d27b --- /dev/null +++ b/include/dt-bindings/power/r8a7794-sysc.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7794_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7794_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7794_PD_CA7_CPU0 5 +#define R8A7794_PD_CA7_CPU1 6 +#define R8A7794_PD_SH_4A 16 +#define R8A7794_PD_SGX 20 +#define R8A7794_PD_CA7_SCU 21 + +/* Always-on power area */ +#define R8A7794_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7794_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h new file mode 100644 index 000000000000..ee2e26ba605e --- /dev/null +++ b/include/dt-bindings/power/r8a7795-sysc.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7795_PD_CA57_CPU0 0 +#define R8A7795_PD_CA57_CPU1 1 +#define R8A7795_PD_CA57_CPU2 2 +#define R8A7795_PD_CA57_CPU3 3 +#define R8A7795_PD_CA53_CPU0 5 +#define R8A7795_PD_CA53_CPU1 6 +#define R8A7795_PD_CA53_CPU2 7 +#define R8A7795_PD_CA53_CPU3 8 +#define R8A7795_PD_A3VP 9 +#define R8A7795_PD_CA57_SCU 12 +#define R8A7795_PD_CR7 13 +#define R8A7795_PD_A3VC 14 +#define R8A7795_PD_3DG_A 17 +#define R8A7795_PD_3DG_B 18 +#define R8A7795_PD_3DG_C 19 +#define R8A7795_PD_3DG_D 20 +#define R8A7795_PD_CA53_SCU 21 +#define R8A7795_PD_3DG_E 22 +#define R8A7795_PD_A3IR 24 +#define R8A7795_PD_A2VC0 25 +#define R8A7795_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A7795_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ diff --git a/include/soc/at91/atmel-sfr.h b/include/soc/at91/atmel-sfr.h new file mode 100644 index 000000000000..2f9bb984a4df --- /dev/null +++ b/include/soc/at91/atmel-sfr.h @@ -0,0 +1,18 @@ +/* + * Atmel SFR (Special Function Registers) register offsets and bit definitions. + * + * Copyright (C) 2016 Atmel + * + * Author: Ludovic Desroches <ludovic.desroches@atmel.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LINUX_MFD_SYSCON_ATMEL_SFR_H +#define _LINUX_MFD_SYSCON_ATMEL_SFR_H + +#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */ + +#endif /* _LINUX_MFD_SYSCON_ATMEL_SFR_H */ |