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| author | Jerome Brunet <jbrunet@baylibre.com> | 2017-01-25 11:53:06 +0100 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-01-26 15:54:48 -0800 |
| commit | 340a84ce1eddd6671ce0c57d890fd90f6ae27fa2 (patch) | |
| tree | 07fdbaaf9ff8656f670e7841cfdf8676d487d51d | |
| parent | 88c9b70bb2b2182fda8ef764ab49ec9e175c8ee2 (diff) | |
| download | linux-340a84ce1eddd6671ce0c57d890fd90f6ae27fa2.tar.gz linux-340a84ce1eddd6671ce0c57d890fd90f6ae27fa2.tar.bz2 linux-340a84ce1eddd6671ce0c57d890fd90f6ae27fa2.zip | |
clk: meson8b: fix clk81 register address
During meson8b clock probe, clk81 register address is fixed twice.
First using the meson8b_clk_gates array, then by directly changing
meson8b_clk81 register.
As a result meson8b_clk81.reg = HHI_MPEG_CLK_CNTL + clk_base + clk_base.
Fixed by just removing the second fixup.
Fixes: e31a1900c1ff ("meson: clk: Add support for clock gates")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 3f1be46cbb33..888494d4fb8a 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -607,7 +607,6 @@ static int meson8b_clkc_probe(struct platform_device *pdev) /* Populate the base address for the MPEG clks */ meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg; meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg; - meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg; /* Populate base address for gates */ for (i = 0; i < ARRAY_SIZE(meson8b_clk_gates); i++) |