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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-04-23 21:30:29 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-04-25 10:23:19 +0200 |
| commit | 5b33139b1a08eabcba7b39d8a4babd7fc2d3b534 (patch) | |
| tree | 38052ef6d2b5de60bc63cf0f459bf1abb8633ec7 | |
| parent | b251e4c88fb443b3a44c3d04268f70e2260f1f8a (diff) | |
| download | linux-5b33139b1a08eabcba7b39d8a4babd7fc2d3b534.tar.gz linux-5b33139b1a08eabcba7b39d8a4babd7fc2d3b534.tar.bz2 linux-5b33139b1a08eabcba7b39d8a4babd7fc2d3b534.zip | |
clk: meson: meson8b: fix meson8b_cpu_clk parent clock name
meson8b_cpu_clk has two parent clocks:
- meson8b_xtal
- meson8b_cpu_scale_out_sel
The name of the "xtal" clock parent is specified correctly. However,
there is a typo in the name of the second parent clock. The
meson8b_cpu_scale_out_sel definition uses the name "cpu_scale_out_sel"
(which matches the name from the datasheet). However, the mux parent
definition uses the name "cpu_out_sel" which does not match any existing
clock.
Fixes: 251b6fd38bcb9c ("clk: meson: rework meson8b cpu clock")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 2c4ff6192852..d0524ec71aad 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -632,7 +632,8 @@ static struct clk_regmap meson8b_cpu_clk = { .hw.init = &(struct clk_init_data){ .name = "cpu_clk", .ops = &clk_regmap_mux_ro_ops, - .parent_names = (const char *[]){ "xtal", "cpu_out_sel" }, + .parent_names = (const char *[]){ "xtal", + "cpu_scale_out_sel" }, .num_parents = 2, .flags = (CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT), |