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| author | Cyrill Gorcunov <gorcunov@openvz.org> | 2010-05-19 01:19:19 +0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2010-05-19 09:41:06 +0200 |
| commit | ce7f15452cc1dc1eca795542367871a07f37aa79 (patch) | |
| tree | e114d7150b0b288ba0cb1e06dee735272647633a | |
| parent | 9d36dfcf219e2ba1f1d169a7f92dcf2cbd4e05f0 (diff) | |
| download | linux-ce7f15452cc1dc1eca795542367871a07f37aa79.tar.gz linux-ce7f15452cc1dc1eca795542367871a07f37aa79.tar.bz2 linux-ce7f15452cc1dc1eca795542367871a07f37aa79.zip | |
perf, x86: P4 PMU -- add missing bit in CCCR mask
Should be there for the sake of RAW events.
Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
CC: Lin Ming <ming.m.lin@intel.com>
CC: Peter Zijlstra <a.p.zijlstra@chello.nl>
CC: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <20100518212439.354345151@openvz.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
| -rw-r--r-- | arch/x86/include/asm/perf_event_p4.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h index b05400a542ff..64a8ebff06fc 100644 --- a/arch/x86/include/asm/perf_event_p4.h +++ b/arch/x86/include/asm/perf_event_p4.h @@ -89,7 +89,8 @@ P4_CCCR_ENABLE) /* HT mask */ -#define P4_CCCR_MASK_HT (P4_CCCR_MASK | P4_CCCR_THREAD_ANY) +#define P4_CCCR_MASK_HT \ + (P4_CCCR_MASK | P4_CCCR_OVF_PMI_T1 | P4_CCCR_THREAD_ANY) #define P4_GEN_ESCR_EMASK(class, name, bit) \ class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT) |