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| author | Marc Dietrich <marvin24@gmx.de> | 2012-01-28 20:03:05 +0100 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-02-06 18:32:51 -0800 |
| commit | 0783a9bf4a5207e9d57b8c110022957f8dc88e2a (patch) | |
| tree | 8f042c3a6f365419f72592f568788185c653633b | |
| parent | 5f21f1240c5d1dad82edb21d38566da85085f530 (diff) | |
| download | linux-0783a9bf4a5207e9d57b8c110022957f8dc88e2a.tar.gz linux-0783a9bf4a5207e9d57b8c110022957f8dc88e2a.tar.bz2 linux-0783a9bf4a5207e9d57b8c110022957f8dc88e2a.zip | |
ARM: tegra: paz00: fix wrong UART port on mini-pcie plug
UARTC is connected to the mini-pcie port.
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
| -rw-r--r-- | arch/arm/boot/dts/tegra-paz00.dts | 4 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/board-paz00.c | 8 |
2 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra-paz00.dts index a94e92c98829..825d2957da0b 100644 --- a/arch/arm/boot/dts/tegra-paz00.dts +++ b/arch/arm/boot/dts/tegra-paz00.dts @@ -46,11 +46,11 @@ }; serial@70006200 { - status = "disable"; + clock-frequency = <216000000>; }; serial@70006300 { - clock-frequency = <216000000>; + status = "disable"; }; serial@70006400 { diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index fcf4f377b1dc..330afdfa2475 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -60,9 +60,9 @@ static struct plat_serial8250_port debug_uart_platform_data[] = { .uartclk = 216000000, }, { /* serial port on mini-pcie */ - .membase = IO_ADDRESS(TEGRA_UARTD_BASE), - .mapbase = TEGRA_UARTD_BASE, - .irq = INT_UARTD, + .membase = IO_ADDRESS(TEGRA_UARTC_BASE), + .mapbase = TEGRA_UARTC_BASE, + .irq = INT_UARTC, .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, .type = PORT_TEGRA, .iotype = UPIO_MEM, @@ -174,7 +174,7 @@ static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline, static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = { /* name parent rate enabled */ { "uarta", "pll_p", 216000000, true }, - { "uartd", "pll_p", 216000000, true }, + { "uartc", "pll_p", 216000000, true }, { "pll_p_out4", "pll_p", 24000000, true }, { "usbd", "clk_m", 12000000, false }, |