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authorYoshinori Sato <ysato@users.sourceforge.jp>2015-05-31 23:34:22 +0900
committerYoshinori Sato <ysato@users.sourceforge.jp>2015-11-08 22:44:39 +0900
commit780ffcd51cb287174e2d5cfe5ece2a7e73db6f37 (patch)
tree9d273982765208e2daf023d8e3a52713ba019de6
parent75078de4ac2901315b77dd813ae2bcb6a5fc1238 (diff)
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h8300: register address fix
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
-rw-r--r--arch/h8300/boot/dts/edosk2674.dts6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/h8300/boot/dts/edosk2674.dts b/arch/h8300/boot/dts/edosk2674.dts
index dfb5c102f8da..4ce9fa874a57 100644
--- a/arch/h8300/boot/dts/edosk2674.dts
+++ b/arch/h8300/boot/dts/edosk2674.dts
@@ -7,7 +7,7 @@
chosen {
bootargs = "console=ttySC2,38400";
- stdout-path = <&sci2>;
+ stdout-path = &sci2;
};
aliases {
serial0 = &sci0;
@@ -25,13 +25,13 @@
compatible = "renesas,h8s2678-pll-clock";
clocks = <&xclk>;
#clock-cells = <0>;
- reg = <0xfee03b 2>, <0xfee045 2>;
+ reg = <0xffff3b 1>, <0xffff45 1>;
};
core_clk: core_clk {
compatible = "renesas,h8300-div-clock";
clocks = <&pllclk>;
#clock-cells = <0>;
- reg = <0xfee03b 2>;
+ reg = <0xffff3b 1>;
renesas,width = <3>;
};
fclk: fclk {