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| author | Roger Quadros <rogerq@ti.com> | 2014-07-06 15:51:24 -0600 |
|---|---|---|
| committer | Paul Walmsley <paul@pwsan.com> | 2014-07-06 15:51:24 -0600 |
| commit | 1ea0999e085acb5dacaff163c3941b1d91d59c89 (patch) | |
| tree | ad56ecc287e5e54563b9ff22440d712a1ca9fe59 | |
| parent | 0cd8d4052ae4c690fc3ea6133a0ad5404360308d (diff) | |
| download | linux-1ea0999e085acb5dacaff163c3941b1d91d59c89.tar.gz linux-1ea0999e085acb5dacaff163c3941b1d91d59c89.tar.bz2 linux-1ea0999e085acb5dacaff163c3941b1d91d59c89.zip | |
ARM: DRA7: hwmod: Fixup SATA hwmod
Get rid of optional clock as that is now managed by the
AHCI platform driver.
Correct .mpu_rt_idx to 1 as the module register space (SYSCONFIG..)
is passed as the second memory resource in the device tree.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Rajendra Nayak <rnayak@ti.com>
Tested-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
| -rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c index 20b4398cec05..1209266a96b1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -1268,9 +1268,6 @@ static struct omap_hwmod_class dra7xx_sata_hwmod_class = { }; /* sata */ -static struct omap_hwmod_opt_clk sata_opt_clks[] = { - { .role = "ref_clk", .clk = "sata_ref_clk" }, -}; static struct omap_hwmod dra7xx_sata_hwmod = { .name = "sata", @@ -1278,6 +1275,7 @@ static struct omap_hwmod dra7xx_sata_hwmod = { .clkdm_name = "l3init_clkdm", .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, .main_clk = "func_48m_fclk", + .mpu_rt_idx = 1, .prcm = { .omap4 = { .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, @@ -1285,8 +1283,6 @@ static struct omap_hwmod dra7xx_sata_hwmod = { .modulemode = MODULEMODE_SWCTRL, }, }, - .opt_clks = sata_opt_clks, - .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks), }; /* |