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| author | Marc Zyngier <marc.zyngier@arm.com> | 2018-02-15 11:49:20 +0000 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2018-03-19 13:06:55 +0000 |
| commit | 4b472ffd1513407ee3607b8e638e8695e9b487ca (patch) | |
| tree | 08a8213a739f75191ec806452d18a7e6c712c8de | |
| parent | dee39247dc75465a24990cb1772c6aaced5fd910 (diff) | |
| download | linux-4b472ffd1513407ee3607b8e638e8695e9b487ca.tar.gz linux-4b472ffd1513407ee3607b8e638e8695e9b487ca.tar.bz2 linux-4b472ffd1513407ee3607b8e638e8695e9b487ca.zip | |
arm64: Enable ARM64_HARDEN_EL2_VECTORS on Cortex-A57 and A72
Cortex-A57 and A72 are vulnerable to the so-called "variant 3a" of
Meltdown, where an attacker can speculatively obtain the value
of a privileged system register.
By enabling ARM64_HARDEN_EL2_VECTORS on these CPUs, obtaining
VBAR_EL2 is not disclosing the hypervisor mappings anymore.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 8cf6b60a085a..aacdc118c4c9 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -425,6 +425,18 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .enable = enable_smccc_arch_workaround_1, }, #endif +#ifdef CONFIG_HARDEN_EL2_VECTORS + { + .desc = "Cortex-A57 EL2 vector hardening", + .capability = ARM64_HARDEN_EL2_VECTORS, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + }, + { + .desc = "Cortex-A72 EL2 vector hardening", + .capability = ARM64_HARDEN_EL2_VECTORS, + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + }, +#endif { } }; |