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| author | Brent Lu <brent.lu@intel.com> | 2020-06-12 18:50:48 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2020-06-15 15:18:34 +0100 |
| commit | 40e2c465894e5b79b49f55d9574dbcda4ac0f08f (patch) | |
| tree | ae08aff4e63622d507c0ba89a73b6f2c7e136ad4 | |
| parent | e74a1e7eaed95f2c6422e7cf9ed70154f17a6db3 (diff) | |
| download | linux-40e2c465894e5b79b49f55d9574dbcda4ac0f08f.tar.gz linux-40e2c465894e5b79b49f55d9574dbcda4ac0f08f.tar.bz2 linux-40e2c465894e5b79b49f55d9574dbcda4ac0f08f.zip | |
ASoC: SOF: Intel: hda: Clear RIRB status before reading WP
Port commit 6d011d5057ff ("ALSA: hda: Clear RIRB status before reading
WP") from legacy HDA driver to fix the get response timeout issue.
Current SOF driver does not suffer from this issue because sync write
is enabled in hda_init. The issue will come back if the sync write is
disabled for some reason.
Signed-off-by: Brent Lu <brent.lu@intel.com>
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Reviewed-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/1591959048-15813-1-git-send-email-brent.lu@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | sound/soc/sof/intel/hda-stream.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/sound/soc/sof/intel/hda-stream.c b/sound/soc/sof/intel/hda-stream.c index 7f65dcc95811..1bda14c3590c 100644 --- a/sound/soc/sof/intel/hda-stream.c +++ b/sound/soc/sof/intel/hda-stream.c @@ -653,11 +653,16 @@ irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context) if (status & AZX_INT_CTRL_EN) { rirb_status = snd_hdac_chip_readb(bus, RIRBSTS); if (rirb_status & RIRB_INT_MASK) { + /* + * Clearing the interrupt status here ensures + * that no interrupt gets masked after the RIRB + * wp is read in snd_hdac_bus_update_rirb. + */ + snd_hdac_chip_writeb(bus, RIRBSTS, + RIRB_INT_MASK); active = true; if (rirb_status & RIRB_INT_RESPONSE) snd_hdac_bus_update_rirb(bus); - snd_hdac_chip_writeb(bus, RIRBSTS, - RIRB_INT_MASK); } } #endif |