diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2007-11-03 01:01:37 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2007-11-15 23:21:48 +0000 |
| commit | a754f70886ebcc7fda3d18a828e0e54e3ffc86d9 (patch) | |
| tree | c070ecad253f24e32cb8036e6f720e0dbdcf23b6 | |
| parent | 99fee6d7e5748d96884667a4628118f7fc130ea0 (diff) | |
| download | linux-a754f70886ebcc7fda3d18a828e0e54e3ffc86d9.tar.gz linux-a754f70886ebcc7fda3d18a828e0e54e3ffc86d9.tar.bz2 linux-a754f70886ebcc7fda3d18a828e0e54e3ffc86d9.zip | |
[MIPS] Sibyte: resurrect old cache hack.
The recent switch of the Sibyte SOCs from the processor specific cache
managment code in c-sb1.c to c-r4k.c lost this old hack
[MIPS] Hack for SB1 cache issues
Removing flush_icache_page a while ago broke SB1 which was using an empty
flush_data_cache_page function. This glues things well enough so a more
efficient but also more intrusive solution can be found later.
Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
in the hope it was no longer needed. As it turns it still is so resurrect
it until there is a better solution.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 6806d58211b2..9355f1c9325f 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -7,6 +7,7 @@ * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org) * Copyright (C) 1999, 2000 Silicon Graphics, Inc. */ +#include <linux/hardirq.h> #include <linux/init.h> #include <linux/highmem.h> #include <linux/kernel.h> @@ -507,7 +508,11 @@ static inline void local_r4k_flush_data_cache_page(void * addr) static void r4k_flush_data_cache_page(unsigned long addr) { - r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, 1, 1); + if (in_atomic()) + local_r4k_flush_data_cache_page((void *)addr); + else + r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr, + 1, 1); } struct flush_icache_range_args { |