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| author | Fugang Duan <b38611@freescale.com> | 2014-05-19 15:46:41 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-06-17 21:11:18 +0800 |
| commit | 4ca2ad55553ef528c055761a9fa4d2c140f7318b (patch) | |
| tree | fe1ebbaa90cd2fa89fc558fcef6aff9eb56f470d | |
| parent | 7171511eaec5bf23fb06078f59784a3a0626b38f (diff) | |
| download | linux-4ca2ad55553ef528c055761a9fa4d2c140f7318b.tar.gz linux-4ca2ad55553ef528c055761a9fa4d2c140f7318b.tar.bz2 linux-4ca2ad55553ef528c055761a9fa4d2c140f7318b.zip | |
ARM: imx6sl: add missing enet clock for imx6sl
There's a enet clock gate missing in clock tree, thus add it.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
| -rw-r--r-- | arch/arm/mach-imx/clk-imx6sl.c | 1 | ||||
| -rw-r--r-- | include/dt-bindings/clock/imx6sl-clock.h | 3 |
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c index 21cf06cebade..5408ca70c8d6 100644 --- a/arch/arm/mach-imx/clk-imx6sl.c +++ b/arch/arm/mach-imx/clk-imx6sl.c @@ -312,6 +312,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node) clks[IMX6SL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); clks[IMX6SL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); clks[IMX6SL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); + clks[IMX6SL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); clks[IMX6SL_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12); clks[IMX6SL_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14); clks[IMX6SL_CLK_EXTERN_AUDIO] = imx_clk_gate2("extern_audio", "extern_audio_podf", base + 0x6c, 16); diff --git a/include/dt-bindings/clock/imx6sl-clock.h b/include/dt-bindings/clock/imx6sl-clock.h index 7cf5c9969336..b91dd462ba85 100644 --- a/include/dt-bindings/clock/imx6sl-clock.h +++ b/include/dt-bindings/clock/imx6sl-clock.h @@ -145,6 +145,7 @@ #define IMX6SL_CLK_USDHC4 132 #define IMX6SL_CLK_PLL4_AUDIO_DIV 133 #define IMX6SL_CLK_SPBA 134 -#define IMX6SL_CLK_END 135 +#define IMX6SL_CLK_ENET 135 +#define IMX6SL_CLK_END 136 #endif /* __DT_BINDINGS_CLOCK_IMX6SL_H */ |