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| author | Atish Patra <atish.patra@wdc.com> | 2019-08-02 21:27:23 -0700 |
|---|---|---|
| committer | Paul Walmsley <paul.walmsley@sifive.com> | 2019-08-08 16:05:38 -0700 |
| commit | 94ed3fde38c7c1347cd82b945553905cfd992ab9 (patch) | |
| tree | 8fd9a56c5a8d11503506ddcc18c501882156cfe8 | |
| parent | 713203e303ca9f75be8c729b533bf1559e442f6e (diff) | |
| download | linux-94ed3fde38c7c1347cd82b945553905cfd992ab9.tar.gz linux-94ed3fde38c7c1347cd82b945553905cfd992ab9.tar.bz2 linux-94ed3fde38c7c1347cd82b945553905cfd992ab9.zip | |
dt-bindings: Update the riscv,isa string description
Since the RISC-V specification states that ISA description strings are
case-insensitive, there's no functional difference between mixed-case,
upper-case, and lower-case ISA strings. Thus, to simplify parsing,
specify that the letters present in "riscv,isa" must be all lowercase.
Suggested-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/cpus.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c899111aa5e3..9d3fe6aada2b 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -50,6 +50,10 @@ properties: User-Level ISA document, available from https://riscv.org/specifications/ + While the isa strings in ISA specification are case + insensitive, letters in the riscv,isa string must be all + lowercase to simplify parsing. + timebase-frequency: type: integer minimum: 1 |