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| author | Jonathan Austin <jonathan.austin@arm.com> | 2016-08-30 17:27:19 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2016-09-06 15:51:07 +0100 |
| commit | f5a5c89e36d0897b65e4e6bc2f646f75f8074263 (patch) | |
| tree | beaaf4b52d04056a54fea8fc7d9706f2d01f481b | |
| parent | 296909ee6d9cf98f68a61d5e9774ff5435df2c6a (diff) | |
| download | linux-f5a5c89e36d0897b65e4e6bc2f646f75f8074263.tar.gz linux-f5a5c89e36d0897b65e4e6bc2f646f75f8074263.tar.bz2 linux-f5a5c89e36d0897b65e4e6bc2f646f75f8074263.zip | |
ARM: 8604/1: V7M: Add support for reading the CTR with read_cpuid_cachetype()
With the addition of caches to the V7M Architecture a new Cache Type
Register (CTR) is defined at 0xE000ED7C. This register serves the same
purpose as the V7A/R version and accessed via the read_cpuid_cachetype.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Andras Szemzo <sza@esh.hu>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| -rw-r--r-- | arch/arm/include/asm/cachetype.h | 15 | ||||
| -rw-r--r-- | arch/arm/include/asm/cputype.h | 15 | ||||
| -rw-r--r-- | arch/arm/kernel/setup.c | 9 |
3 files changed, 30 insertions, 9 deletions
diff --git a/arch/arm/include/asm/cachetype.h b/arch/arm/include/asm/cachetype.h index 8609de8e313a..01509ae0bbec 100644 --- a/arch/arm/include/asm/cachetype.h +++ b/arch/arm/include/asm/cachetype.h @@ -67,6 +67,7 @@ static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask) #define CSSELR_L6 (5 << 1) #define CSSELR_L7 (6 << 1) +#ifndef CONFIG_CPU_V7M static inline void set_csselr(unsigned int cache_selector) { asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector)); @@ -79,5 +80,19 @@ static inline unsigned int read_ccsidr(void) asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val)); return val; } +#else /* CONFIG_CPU_V7M */ +#include <linux/io.h> +#include "asm/v7m.h" + +static inline void set_csselr(unsigned int cache_selector) +{ + writel(cache_selector, BASEADDR_V7M_SCB + V7M_SCB_CTR); +} + +static inline unsigned int read_ccsidr(void) +{ + return readl(BASEADDR_V7M_SCB + V7M_SCB_CCSIDR); +} +#endif #endif diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index d6a4902a75d7..754f86f667d4 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -164,6 +164,11 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return read_cpuid(CPUID_ID); } +static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) +{ + return read_cpuid(CPUID_CACHETYPE); +} + #elif defined(CONFIG_CPU_V7M) static inline unsigned int __attribute_const__ read_cpuid_id(void) @@ -171,6 +176,11 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void) return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID); } +static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) +{ + return readl(BASEADDR_V7M_SCB + V7M_SCB_CTR); +} + #else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */ static inline unsigned int __attribute_const__ read_cpuid_id(void) @@ -210,11 +220,6 @@ static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void) return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK; } -static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) -{ - return read_cpuid(CPUID_CACHETYPE); -} - static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void) { return read_cpuid(CPUID_TCM); diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index d7568808eb7b..34e3f3c45634 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c @@ -312,11 +312,12 @@ static void __init cacheid_init(void) { unsigned int arch = cpu_architecture(); - if (arch == CPU_ARCH_ARMv7M) { - cacheid = 0; - } else if (arch >= CPU_ARCH_ARMv6) { + if (arch >= CPU_ARCH_ARMv6) { unsigned int cachetype = read_cpuid_cachetype(); - if ((cachetype & (7 << 29)) == 4 << 29) { + + if ((arch == CPU_ARCH_ARMv7M) && !cachetype) { + cacheid = 0; + } else if ((cachetype & (7 << 29)) == 4 << 29) { /* ARMv7 register format */ arch = CPU_ARCH_ARMv7; cacheid = CACHEID_VIPT_NONALIASING; |