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authorThomas Gleixner <tglx@linutronix.de>2013-05-05 08:24:42 +0200
committerThomas Gleixner <tglx@linutronix.de>2013-05-05 08:27:03 +0200
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tree0f448b21128c478053ee7f7765b865954c4eebe8 /Documentation/devicetree/bindings/clock/altr_socfpga.txt
parentfd29f424d458118f02e89596505c68a63dcb3007 (diff)
parentce857229e0c3adc211944a13a5579ef84fd7b4af (diff)
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Merge branch 'linus' into core/urgent
Update with Linus tree so fixes for the same can be applied. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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+Device Tree Clock bindings for Altera's SoCFPGA platform
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be one of the following:
+ "altr,socfpga-pll-clock" - for a PLL clock
+ "altr,socfpga-perip-clock" - The peripheral clock divided from the
+ PLL clock.
+- reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
+- clocks : shall be the input parent clock phandle for the clock. This is
+ either an oscillator or a pll output.
+- #clock-cells : from common clock binding, shall be set to 0.
+
+Optional properties:
+- fixed-divider : If clocks have a fixed divider value, use this property.