clk: samsung: exynos5433: Add clocks for CMU_MFC domain

This patch adds the mux/divider/gate clocks for CMU_MFC domain which
generates the clocks for MFC(Multi-Format Codec) IP.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

1 files changed, 15 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
index ecb9534c2ea6..0f35167ec15c 100644
--- a/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5433-clock.txt
@@ -39,6 +39,8 @@ Required Properties:
     L2 cache controller.
   - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
     which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
+  - "samsung,exynos5433-cmu-mfc"  - clock controller compatible for CMU_MFC
+    which generates clocks for MFC(Multi-Format Codec) IP.
 
 - reg: physical base address of the controller and length of memory mapped
   region.
@@ -125,6 +127,10 @@ Required Properties:
 		- sclk_jpeg_mscl
 		- aclk_mscl_400
 
+	Input clocks for mfc clock controller:
+		- oscclk
+		- aclk_mfc_400
+
 Each clock is assigned an identifier and client nodes can use this identifier
 to specify the clock which they consume.
 
@@ -340,6 +346,15 @@ Example 2: Examples of clock controller nodes are listed below.
 		       <&cmu_top CLK_ACLK_MSCL_400>;
 	};
 
+	cmu_mfc: clock-controller@15280000 {
+		compatible = "samsung,exynos5433-cmu-mfc";
+		reg = <0x15280000 0x0b08>;
+		#clock-cells = <1>;
+
+		clock-names = "oscclk", "aclk_mfc_400";
+		clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
+	};
+
 Example 3: UART controller node that consumes the clock generated by the clock
 	   controller.