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| author | Michael Turquette <mturquette@linaro.org> | 2015-03-25 14:51:40 -0700 |
|---|---|---|
| committer | Michael Turquette <mturquette@linaro.org> | 2015-03-25 14:51:40 -0700 |
| commit | fe15dedc02e4ee29edfc84bbbf5ee42827e36ac7 (patch) | |
| tree | b64f9ceebdbf3019f3d10ecb404f6fc002223113 /Documentation/devicetree/bindings/clock | |
| parent | c77662a4df847e7b75ff8c5f2314dd4f022377e3 (diff) | |
| parent | f1017969661dd33ead5ba7c3f4a0793c6611441a (diff) | |
| download | linux-fe15dedc02e4ee29edfc84bbbf5ee42827e36ac7.tar.gz linux-fe15dedc02e4ee29edfc84bbbf5ee42827e36ac7.tar.bz2 linux-fe15dedc02e4ee29edfc84bbbf5ee42827e36ac7.zip | |
Merge tag 'sunxi-clocks-for-4.1' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next
Allwinner clocks changes for 4.1
The usual round of clock changes for the Allwinner SoCs.
There is nothing really standing out here, but a few changes and fixes, most
notably to allow the AHB clock to be parented to a PLL, instead of the CPU
clock to avoid any AHB rate change due to cpufreq.
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/sunxi.txt | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt index 60b44285250d..4fa11af3d378 100644 --- a/Documentation/devicetree/bindings/clock/sunxi.txt +++ b/Documentation/devicetree/bindings/clock/sunxi.txt @@ -20,6 +20,7 @@ Required properties: "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23 "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates "allwinner,sun4i-a10-ahb-clk" - for the AHB clock + "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13 "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13 @@ -66,6 +67,8 @@ Required properties: "allwinner,sun4i-a10-usb-clk" - for usb gates + resets on A10 / A20 "allwinner,sun5i-a13-usb-clk" - for usb gates + resets on A13 "allwinner,sun6i-a31-usb-clk" - for usb gates + resets on A31 + "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80 + "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80 Required properties for all clocks: - reg : shall be the control register address for the clock. |