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| author | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2022-11-17 11:01:42 +0530 |
|---|---|---|
| committer | Viresh Kumar <viresh.kumar@linaro.org> | 2022-11-21 10:40:07 +0530 |
| commit | f9281ab6b8366a6697df27c11946f84a626f93b5 (patch) | |
| tree | 82b03ce187cdee7b06977ea61418f8d2fcc2b416 /Documentation/devicetree/bindings/cpufreq | |
| parent | c72cf0cb1d77f6b1b58c334dcc3d09fa13111c4c (diff) | |
| download | linux-f9281ab6b8366a6697df27c11946f84a626f93b5.tar.gz linux-f9281ab6b8366a6697df27c11946f84a626f93b5.tar.bz2 linux-f9281ab6b8366a6697df27c11946f84a626f93b5.zip | |
dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider
Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
to the CPU cores. Document the same in the binding to reflect the actual
implementation.
CPUFreq HW will become the clock provider and CPU cores will become the
clock consumers.
The clock index for each CPU core is based on the frequency domain index.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/cpufreq')
| -rw-r--r-- | Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e58c55f78aaa..676d369a6fdd 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -56,6 +56,9 @@ properties: '#freq-domain-cells': const: 1 + '#clock-cells': + const: 1 + required: - compatible - reg @@ -83,6 +86,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; cache-unified; @@ -103,6 +107,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; cache-unified; @@ -118,6 +123,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; cache-unified; @@ -133,6 +139,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; cache-unified; @@ -148,6 +155,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; cache-unified; @@ -163,6 +171,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; cache-unified; @@ -178,6 +187,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; cache-unified; @@ -193,6 +203,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_700: l2-cache { compatible = "cache"; cache-unified; @@ -215,6 +226,7 @@ examples: clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; ... |