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| author | Will Deacon <will.deacon@arm.com> | 2014-06-25 11:29:12 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2014-07-03 15:50:22 +0100 |
| commit | 44680eedf9409daf0fed618ae101f35d1f83d1a4 (patch) | |
| tree | 5951a5e3af529803ead15a7885a12f0008fabb70 /Documentation/devicetree/bindings/iommu | |
| parent | d0948945638635487111d0851218080e81de5104 (diff) | |
| download | linux-44680eedf9409daf0fed618ae101f35d1f83d1a4.tar.gz linux-44680eedf9409daf0fed618ae101f35d1f83d1a4.tar.bz2 linux-44680eedf9409daf0fed618ae101f35d1f83d1a4.zip | |
iommu/arm-smmu: remove support for chained SMMUs
The ARM SMMU driver has supported chained SMMUs (i.e. SMMUs connected
back-to-back in series) via the smmu-parent property in device tree.
This was in anticipation of somebody building such a configuration,
however that seems not to be the case.
This patch removes the unused chained SMMU hack from the driver. We can
consider adding it back later if somebody decided they need it, but for
the time being it's just pointless mess that we're carrying in mainline.
Removal of the feature also makes migration to the generic IOMMU bindings
easier.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/devicetree/bindings/iommu')
| -rw-r--r-- | Documentation/devicetree/bindings/iommu/arm,smmu.txt | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index f284b99402bc..2d0f7cd867ea 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -42,12 +42,6 @@ conditions. ** System MMU optional properties: -- smmu-parent : When multiple SMMUs are chained together, this - property can be used to provide a phandle to the - parent SMMU (that is the next SMMU on the path going - from the mmu-masters towards memory) node for this - SMMU. - - calxeda,smmu-secure-config-access : Enable proper handling of buggy implementations that always use secure access to SMMU configuration registers. In this case non-secure |