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| author | Maxime Ripard <mripard@kernel.org> | 2019-10-03 17:48:41 +0200 |
|---|---|---|
| committer | Maxime Ripard <mripard@kernel.org> | 2019-10-07 14:12:06 +0200 |
| commit | 90b32268e15c003d894e5567b7181bcc2bad6b2c (patch) | |
| tree | 26aecef1f799b2b163617fbe4c363f786138f079 /Documentation/devicetree | |
| parent | e1056f9bbf0d79e9120dc4cbdc96ce7fee6cd15f (diff) | |
| download | linux-90b32268e15c003d894e5567b7181bcc2bad6b2c.tar.gz linux-90b32268e15c003d894e5567b7181bcc2bad6b2c.tar.bz2 linux-90b32268e15c003d894e5567b7181bcc2bad6b2c.zip | |
dt-bindings: media: sun4i-csi: Drop the module clock
It turns out that what was thought to be the module clock was actually the
clock meant to be used by the sensor, and isn't playing any role with the
CSI controller itself. Let's drop that clock from our binding.
Fixes: c5e8f4ccd775 ("media: dt-bindings: media: Add Allwinner A10 CSI binding")
Reported-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml index 5dd1cf490cd9..d3e423fcb6c2 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml @@ -27,14 +27,12 @@ properties: clocks: items: - description: The CSI interface clock - - description: The CSI module clock - description: The CSI ISP clock - description: The CSI DRAM clock clock-names: items: - const: bus - - const: mod - const: isp - const: ram @@ -89,9 +87,8 @@ examples: compatible = "allwinner,sun7i-a20-csi0"; reg = <0x01c09000 0x1000>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI0>, - <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; - clock-names = "bus", "mod", "isp", "ram"; + clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>; + clock-names = "bus", "isp", "ram"; resets = <&ccu RST_CSI0>; port { |