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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2015-01-13 19:08:14 +0200
committerVinod Koul <vinod.koul@intel.com>2015-02-04 22:39:44 -0800
commitd8ded50f8b26a224df48f9f93e49440c6a39b77f (patch)
tree7c7620107180b0a2c3ea77770ef8fb9bccfa8341 /Documentation/devicetree
parentcfd8fef322305bbe9955817464f0d2054ce545c0 (diff)
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dmaengine: dw: define DW_DMA_MAX_NR_MASTERS
Instead of using magic number in the code the patch provides DW_DMA_MAX_NR_MASTERS constant. While here, restrict the reading of data width array by amount of the actual number of AHB masters. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/dma/snps-dma.txt2
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt
index d58675ea1abf..c261598164a7 100644
--- a/Documentation/devicetree/bindings/dma/snps-dma.txt
+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
@@ -38,7 +38,7 @@ Example:
chan_allocation_order = <1>;
chan_priority = <1>;
block_size = <0xfff>;
- data_width = <3 3 0 0>;
+ data_width = <3 3>;
};
DMA clients connected to the Designware DMA controller must use the format