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authorJoao Pinto <Joao.Pinto@synopsys.com>2017-03-10 18:24:59 +0000
committerDavid S. Miller <davem@davemloft.net>2017-03-12 23:41:04 -0700
commit19d9187317979cf0c25f67017d2676149abc46b2 (patch)
tree5107036a3df1310fc8e7d58ef545d9905591368e /Documentation/devicetree
parentad5a87d7e3c5fcea987728027a3fae2c2f067173 (diff)
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net: stmmac: configuration of CBS in case of a TX AVB queue
This patch adds the configuration of the AVB Credit-Based Shaper. Signed-off-by: Joao Pinto <jpinto@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/net/stmmac.txt22
1 files changed, 19 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/net/stmmac.txt b/Documentation/devicetree/bindings/net/stmmac.txt
index 04a258e2d4e0..a7b0e41cb264 100644
--- a/Documentation/devicetree/bindings/net/stmmac.txt
+++ b/Documentation/devicetree/bindings/net/stmmac.txt
@@ -92,8 +92,15 @@ Optional properties:
- snps,tx-sched-dwrr: Deficit Weighted Round Robin
- snps,tx-sched-sp: Strict priority
- For each TX queue
- - snps,weight: TX queue weight (if using a weighted algorithm)
-
+ - snps,weight: TX queue weight (if using a DCB weight algorithm)
+ - Choose one of these modes:
+ - snps,dcb-algorithm: TX queue will be working in DCB
+ - snps,avb-algorithm: TX queue will be working in AVB
+ - Configure Credit Base Shaper (if AVB Mode selected):
+ - snps,send_slope: enable Low Power Interface
+ - snps,idle_slope: unlock on WoL
+ - snps,high_credit: max write outstanding req. limit
+ - snps,low_credit: max read outstanding req. limit
Examples:
stmmac_axi_setup: stmmac-axi-config {
@@ -112,10 +119,19 @@ Examples:
};
mtl_tx_setup: tx-queues-config {
- snps,tx-queues-to-use = <1>;
+ snps,tx-queues-to-use = <2>;
snps,tx-sched-wrr;
queue0 {
snps,weight = <0x10>;
+ snps,dcb-algorithm;
+ };
+
+ queue1 {
+ snps,avb-algorithm;
+ snps,send_slope = <0x1000>;
+ snps,idle_slope = <0x1000>;
+ snps,high_credit = <0x3E800>;
+ snps,low_credit = <0xFFC18000>;
};
};