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authorIngo Molnar <mingo@elte.hu>2009-10-06 15:02:30 +0200
committerIngo Molnar <mingo@elte.hu>2009-10-06 15:02:34 +0200
commitd9b2002c406011164f245de7a81304625989f1c9 (patch)
treea2bb74773cd1409acbec5eb2fbba2ae9889d55e8 /Documentation/powerpc/dts-bindings/fsl/esdhc.txt
parentc3b32fcbc7f4fd9a9b84718b991b175b0fd53f8c (diff)
parent906010b2134e14a2e377decbadd357b3d0ab9c6a (diff)
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Merge branch 'perf/urgent' into perf/core
Merge reason: Upcoming patch is dependent on a fix in perf/urgent. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'Documentation/powerpc/dts-bindings/fsl/esdhc.txt')
-rw-r--r--Documentation/powerpc/dts-bindings/fsl/esdhc.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
index 3ed3797b5086..8a0040738969 100644
--- a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt
@@ -10,6 +10,8 @@ Required properties:
- interrupts : should contain eSDHC interrupt.
- interrupt-parent : interrupt source phandle.
- clock-frequency : specifies eSDHC base clock frequency.
+ - sdhci,wp-inverted : (optional) specifies that eSDHC controller
+ reports inverted write-protect state;
- sdhci,1-bit-only : (optional) specifies that a controller can
only handle 1-bit data transfers.