summaryrefslogtreecommitdiffstats
path: root/Documentation
diff options
context:
space:
mode:
authorMars Cheng <mars.cheng@mediatek.com>2017-03-19 23:26:22 +0800
committerMarc Zyngier <marc.zyngier@arm.com>2017-04-07 10:51:48 +0100
commitd240fe0a4066e592f8e3a698d8648bdd47bc51b7 (patch)
tree51ef0d374995dec5efcfb807ff38c0627f29af68 /Documentation
parent390d2d490b4618fe147927778a8fdbc8e22f3dc3 (diff)
downloadlinux-d240fe0a4066e592f8e3a698d8648bdd47bc51b7.tar.gz
linux-d240fe0a4066e592f8e3a698d8648bdd47bc51b7.tar.bz2
linux-d240fe0a4066e592f8e3a698d8648bdd47bc51b7.zip
dt-bindings: mtk-sysirq: Add multiple bases support for Mediatek sysirq
This describes how to specify multiple base addresses for sysirq in mediatek platforms. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Mars Cheng <mars.cheng@mediatek.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt11
1 files changed, 7 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
index 9d1d72c65489..a89c03bb1a81 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt
@@ -21,13 +21,16 @@ Required properties:
- interrupt-parent: phandle of irq parent for sysirq. The parent must
use the same interrupt-cells format as GIC.
- reg: Physical base address of the intpol registers and length of memory
- mapped region.
+ mapped region. Could be multiple bases here. Ex: mt6797 needs 2 reg, others
+ need 1.
Example:
- sysirq: interrupt-controller@10200100 {
- compatible = "mediatek,mt6589-sysirq", "mediatek,mt6577-sysirq";
+ sysirq: intpol-controller@10200620 {
+ compatible = "mediatek,mt6797-sysirq",
+ "mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
- reg = <0 0x10200100 0 0x1c>;
+ reg = <0 0x10220620 0 0x20>,
+ <0 0x10220690 0 0x10>;
};