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author | Lucas Stach <l.stach@pengutronix.de> | 2017-03-08 12:13:13 +0100 |
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committer | Philipp Zabel <p.zabel@pengutronix.de> | 2017-03-15 15:42:34 +0100 |
commit | dcddda561b91fe82a8201ba7f5b4237be4c79219 (patch) | |
tree | 0150fb537ee6a7aa03a3b274e75e3951c81a1cc7 /Documentation | |
parent | f6b50ef14ea84725c1b41c9ffea611cdfb71c7dd (diff) | |
download | linux-dcddda561b91fe82a8201ba7f5b4237be4c79219.tar.gz linux-dcddda561b91fe82a8201ba7f5b4237be4c79219.tar.bz2 linux-dcddda561b91fe82a8201ba7f5b4237be4c79219.zip |
gpu: ipu-v3: add DT binding for the Prefetch Resolve Engine
The Prefetch Resolve Engine is a prefetch and tile resolve engine
which prefetches display data from DRAM to an internal SRAM region.
It has a single clock for configuration register access and the
functional units. A single shared interrupt is used for status and
error signaling.
The only external dependency is the SRAM region to use for the
prefetch double buffer.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'Documentation')
-rw-r--r-- | Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index 971c3eedb1c7..70ae5335d1e3 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -53,6 +53,32 @@ ipu: ipu@18000000 { }; }; +Freescale i.MX PRE (Prefetch Resolve Engine) +============================================ + +Required properties: +- compatible: should be "fsl,imx6qp-pre" +- reg: should be register base and length as documented in the + datasheet +- clocks : phandle to the PRE axi clock input, as described + in Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx6q-clock.txt. +- clock-names: should be "axi" +- interrupts: should contain the PRE interrupt +- fsl,iram: phandle pointing to the mmio-sram device node, that should be + used for the PRE SRAM double buffer. + +example: + +pre@21c8000 { + compatible = "fsl,imx6qp-pre"; + reg = <0x021c8000 0x1000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; + clocks = <&clks IMX6QDL_CLK_PRE0>; + clock-names = "axi"; + fsl,iram = <&ocram2>; +}; + Parallel display support ======================== |