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| author | Chew, Chiau Ee <chiau.ee.chew@intel.com> | 2014-06-13 23:57:25 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@linaro.org> | 2014-06-17 15:45:52 +0100 |
| commit | e61f487fd596ce570e87ccfdc0a7fc9fa87aced9 (patch) | |
| tree | 7f7ac8e9170d7c41cb49f2abde20542e80309df2 /Documentation | |
| parent | 01d7aafb3fbaafe2403780ef9ed497b3289ab1b9 (diff) | |
| download | linux-e61f487fd596ce570e87ccfdc0a7fc9fa87aced9.tar.gz linux-e61f487fd596ce570e87ccfdc0a7fc9fa87aced9.tar.bz2 linux-e61f487fd596ce570e87ccfdc0a7fc9fa87aced9.zip | |
spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI
It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.
Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions