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| author | Vineet Gupta <vgupta@synopsys.com> | 2017-08-03 17:45:44 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2017-08-04 13:56:35 +0530 |
| commit | b5ddb6d54729d814356937572d6c9b599f10c29f (patch) | |
| tree | 122ddb43a2f0a0472237e20114ea78b1db5ff7a3 /arch/arc/include | |
| parent | 7d79cee2c6540ea64dd917a14e2fd63d4ac3d3c0 (diff) | |
| download | linux-b5ddb6d54729d814356937572d6c9b599f10c29f.tar.gz linux-b5ddb6d54729d814356937572d6c9b599f10c29f.tar.bz2 linux-b5ddb6d54729d814356937572d6c9b599f10c29f.zip | |
ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoC
PAE40 confiuration in hardware extends some of the address registers
for TLB/cache ops to 2 words.
So far kernel was NOT setting the higher word if feature was not enabled
in software which is wrong. Those need to be set to 0 in such case.
Normally this would be done in the cache flush / tlb ops, however since
these registers only exist conditionally, this would have to be
conditional to a flag being set on boot which is expensive/ugly -
specially for the more common case of PAE exists but not in use.
Optimize that by zero'ing them once at boot - nobody will write to
them afterwards
Cc: stable@vger.kernel.org #4.4+
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/include')
| -rw-r--r-- | arch/arc/include/asm/mmu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arc/include/asm/mmu.h b/arch/arc/include/asm/mmu.h index db7319e9b506..efb79fafff1d 100644 --- a/arch/arc/include/asm/mmu.h +++ b/arch/arc/include/asm/mmu.h @@ -94,6 +94,8 @@ static inline int is_pae40_enabled(void) return IS_ENABLED(CONFIG_ARC_HAS_PAE40); } +extern int pae40_exist_but_not_enab(void); + #endif /* !__ASSEMBLY__ */ #endif |