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| author | Will Deacon <will.deacon@arm.com> | 2010-08-05 11:20:51 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2010-08-10 22:10:54 +0100 |
| commit | cdf357f1e13a08a11261edacb3083746f65c1ed9 (patch) | |
| tree | bb49c4536929906b69f6e99e2457fc2ccc7944d9 /arch/arm/Kconfig | |
| parent | 988257cfcbc468cb26b3addfcab1d0187c4e2399 (diff) | |
| download | linux-cdf357f1e13a08a11261edacb3083746f65c1ed9.tar.gz linux-cdf357f1e13a08a11261edacb3083746f65c1ed9.tar.bz2 linux-cdf357f1e13a08a11261edacb3083746f65c1ed9.zip | |
ARM: 6299/1: errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID
On versions of the Cortex-A9 prior to r2p0, performing TLB invalidations by
ASID match can result in the incorrect ASID being broadcast to other CPUs.
As a consequence of this, the targetted TLB entries are not invalidated
across the system.
This workaround changes the TLB flushing routines to invalidate entries
regardless of the ASID.
Cc: <stable@kernel.org>
Tested-by: Rob Clark <rob@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 232f0c758252..e3956042892c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1040,6 +1040,18 @@ config PL310_ERRATA_588369 is not correctly implemented in PL310 as clean lines are not invalidated as a result of these operations. Note that this errata uses Texas Instrument's secure monitor api. + +config ARM_ERRATA_720789 + bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 720789 Cortex-A9 (prior to + r2p0) erratum. A faulty ASID can be sent to the other CPUs for the + broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. + As a consequence of this erratum, some TLB entries which should be + invalidated are not, resulting in an incoherency in the system page + tables. The workaround changes the TLB flushing routines to invalidate + entries regardless of the ASID. endmenu source "arch/arm/common/Kconfig" |