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| author | Haojian Zhuang <haojian.zhuang@gmail.com> | 2012-04-19 18:44:50 +0800 |
|---|---|---|
| committer | Haojian Zhuang <haojian.zhuang@gmail.com> | 2012-05-05 16:39:29 +0800 |
| commit | ff290fc3ed7c4f451ea029190624cff692f028a5 (patch) | |
| tree | 43b0b2588cd2602186a58e696cebab538ce69b2b /arch/arm/boot/dts/pxa168.dtsi | |
| parent | 641f4d562cf69e1839c84c9415169644025ec247 (diff) | |
| download | linux-ff290fc3ed7c4f451ea029190624cff692f028a5.tar.gz linux-ff290fc3ed7c4f451ea029190624cff692f028a5.tar.bz2 linux-ff290fc3ed7c4f451ea029190624cff692f028a5.zip | |
ARM: dts: refresh dts file for arch mmp
Append mmp2 and pxa910 dts files. Update PXA168 dts files for irq,
timer, gpio components.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/pxa168.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/pxa168.dtsi | 67 |
1 files changed, 51 insertions, 16 deletions
diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index d32d5128f225..31a718696080 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -18,13 +18,6 @@ i2c1 = &twsi2; }; - intc: intc-interrupt-controller@d4282000 { - compatible = "mrvl,mmp-intc", "mrvl,intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0xd4282000 0x1000>; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -32,6 +25,23 @@ interrupt-parent = <&intc>; ranges; + axi@d4200000 { /* AXI */ + compatible = "mrvl,axi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0xd4200000 0x00200000>; + ranges; + + intc: interrupt-controller@d4282000 { + compatible = "mrvl,mmp-intc"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xd4282000 0x1000>; + mrvl,intc-nr-irqs = <64>; + }; + + }; + apb@d4000000 { /* APB */ compatible = "mrvl,apb-bus", "simple-bus"; #address-cells = <1>; @@ -39,40 +49,65 @@ reg = <0xd4000000 0x00200000>; ranges; + timer0: timer@d4014000 { + compatible = "mrvl,mmp-timer"; + reg = <0xd4014000 0x100>; + interrupts = <13>; + }; + uart1: uart@d4017000 { - compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + compatible = "mrvl,mmp-uart"; reg = <0xd4017000 0x1000>; interrupts = <27>; status = "disabled"; }; uart2: uart@d4018000 { - compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + compatible = "mrvl,mmp-uart"; reg = <0xd4018000 0x1000>; interrupts = <28>; status = "disabled"; }; uart3: uart@d4026000 { - compatible = "mrvl,mmp-uart", "mrvl,pxa-uart"; + compatible = "mrvl,mmp-uart"; reg = <0xd4026000 0x1000>; interrupts = <29>; status = "disabled"; }; - gpio: gpio@d4019000 { - compatible = "mrvl,mmp-gpio", "mrvl,pxa-gpio"; + gpio@d4019000 { + compatible = "mrvl,mmp-gpio"; + #address-cells = <1>; + #size-cells = <1>; reg = <0xd4019000 0x1000>; + gpio-controller; + #gpio-cells = <2>; interrupts = <49>; interrupt-names = "gpio_mux"; - gpio-controller; - #gpio-cells = <1>; interrupt-controller; #interrupt-cells = <1>; + ranges; + + gcb0: gpio@d4019000 { + reg = <0xd4019000 0x4>; + }; + + gcb1: gpio@d4019004 { + reg = <0xd4019004 0x4>; + }; + + gcb2: gpio@d4019008 { + reg = <0xd4019008 0x4>; + }; + + gcb3: gpio@d4019100 { + reg = <0xd4019100 0x4>; + }; }; twsi1: i2c@d4011000 { - compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; + compatible = "mrvl,mmp-twsi"; reg = <0xd4011000 0x1000>; interrupts = <7>; mrvl,i2c-fast-mode; @@ -80,7 +115,7 @@ }; twsi2: i2c@d4025000 { - compatible = "mrvl,mmp-twsi", "mrvl,pxa-i2c"; + compatible = "mrvl,mmp-twsi"; reg = <0xd4025000 0x1000>; interrupts = <58>; status = "disabled"; |