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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-06 17:40:40 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-03-07 07:44:49 +0100 |
| commit | 5d6a2165abd4635ecf5ece3d02fe8677f00d32c5 (patch) | |
| tree | 36d048b320c3765fb89913bb53ee00fc0e579311 /arch/arm/boot/dts/r8a7791.dtsi | |
| parent | d492909c84b895564d7ac413546ae988945c68db (diff) | |
| download | linux-5d6a2165abd4635ecf5ece3d02fe8677f00d32c5.tar.gz linux-5d6a2165abd4635ecf5ece3d02fe8677f00d32c5.tar.bz2 linux-5d6a2165abd4635ecf5ece3d02fe8677f00d32c5.zip | |
ARM: dts: r8a7791: Remove unit-address and reg from integrated cache
The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 6f9314ce258c8504 ("ARM: dts: r8a7791: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7791.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7791.dtsi | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 9f9e48511836..7cad65a28f25 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -74,9 +74,8 @@ next-level-cache = <&L2_CA15>; }; - L2_CA15: cache-controller@0 { + L2_CA15: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc R8A7791_PD_CA15_SCU>; cache-unified; cache-level = <2>; |