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| author | Stephen Warren <swarren@nvidia.com> | 2013-10-31 17:23:05 -0600 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-12-16 14:09:18 -0700 |
| commit | 784c7444f052dda27db8d40ed35b57aefd2e04b8 (patch) | |
| tree | 4db46e83d29084757d11d25ead7a0b5c5c3e6486 /arch/arm/boot/dts/tegra124.dtsi | |
| parent | caefe637b494c437e86fa6c90bb4b17e01ea558e (diff) | |
| download | linux-784c7444f052dda27db8d40ed35b57aefd2e04b8.tar.gz linux-784c7444f052dda27db8d40ed35b57aefd2e04b8.tar.bz2 linux-784c7444f052dda27db8d40ed35b57aefd2e04b8.zip | |
ARM: tegra: add MMC controllers to Tegra124 DT
Tegra124 has 4 MMC controllers just like previous versions of the SoC.
Note that there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW.
Also enable the relevant controllers in the Venice2 board DT.
power-gpios property suggested by Thierry Reding.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra124.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index fe070bc4c862..eb61456d2dc3 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -190,6 +190,46 @@ clock-names = "pclk", "clk32k_in"; }; + sdhci@700b0000 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0000 0x200>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0200 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0200 0x200>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0400 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0400 0x200>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; + status = "disable"; + }; + + sdhci@700b0600 { + compatible = "nvidia,tegra124-sdhci"; + reg = <0x700b0600 0x200>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; + status = "disable"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; |