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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-10-02 15:23:00 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-10-02 15:23:00 -0700 |
| commit | f76d9c61d91343806e59335493806e87daf78947 (patch) | |
| tree | e3c98a687783c5fbe9862646f455435fb6bfe3f8 /arch/arm/boot | |
| parent | be67d60ba944bdd38571b79bdcd506e34c0f16c1 (diff) | |
| parent | 117e5e9c4cfcb7628f08de074fbfefec1bb678b7 (diff) | |
| download | linux-f76d9c61d91343806e59335493806e87daf78947.tar.gz linux-f76d9c61d91343806e59335493806e87daf78947.tar.bz2 linux-f76d9c61d91343806e59335493806e87daf78947.zip | |
Merge branch 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm
Pull ARM fixes from Russell King:
"Three relatively small fixes for ARM:
- Roger noticed that dma_max_pfn() was calculating the upper limit
wrongly, by adding the PFN offset of memory twice.
- A fix from Robin to correct parsing of MPIDR values when the
address size is larger than one BE32 unit.
- A fix from Srinivas to ensure that we do not rely on the boot
loader (or previous Linux kernel) setting the translation table
base register a certain way in the decompressor, which can lead to
crashes"
* 'fixes' of git://git.armlinux.org.uk/~rmk/linux-arm:
ARM: 8618/1: decompressor: reset ttbcr fields to use TTBR0 on ARMv7
ARM: 8617/1: dma: fix dma_max_pfn()
ARM: 8616/1: dt: Respect property size when parsing CPUs
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/compressed/head.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index af11c2f8f3b7..fc6d541549a2 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -779,7 +779,7 @@ __armv7_mmu_cache_on: orrne r0, r0, #1 @ MMU enabled movne r1, #0xfffffffd @ domain 0 = client bic r6, r6, #1 << 31 @ 32-bit translation system - bic r6, r6, #3 << 0 @ use only ttbr0 + bic r6, r6, #(7 << 0) | (1 << 4) @ use only ttbr0 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer mcrne p15, 0, r1, c3, c0, 0 @ load domain access control mcrne p15, 0, r6, c2, c0, 2 @ load ttb control |