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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2023-03-08 13:54:19 +0530
committerBjorn Andersson <andersson@kernel.org>2023-03-15 19:38:50 -0700
commitf9364a7ced5e6e36904c359cafe23cbf03645884 (patch)
tree64126f795fdee207343e45d196f1920aa447f774 /arch/arm/boot
parent2b20437e67a4b74b990d19d3dbf55388e941f30f (diff)
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ARM: dts: qcom: sdx55: List the property values vertically
To align with the rest of the devicetree files and the relative properties, let's list the values of properties such as {reg/clock/interrupt}-names vertically. Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230308082424.140224-9-manivannan.sadhasivam@linaro.org
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/qcom-sdx55.dtsi23
1 files changed, 18 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi
index 9dabb94eafbc..286fa92da428 100644
--- a/arch/arm/boot/dts/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom-sdx55.dtsi
@@ -393,7 +393,11 @@
<0x40001000 0x1000>,
<0x40200000 0x100000>,
<0x01c03000 0x3000>;
- reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "addr_space",
"mmio";
qcom,perst-regs = <&tcsr 0xb258 0xb270>;
@@ -405,12 +409,18 @@
<&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
<&gcc GCC_PCIE_SLEEP_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>;
- clock-names = "aux", "cfg", "bus_master", "bus_slave",
- "slave_q2a", "sleep", "ref";
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "sleep",
+ "ref";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "global", "doorbell";
+ interrupt-names = "global",
+ "doorbell";
reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_PCIE_BCR>;
@@ -434,7 +444,10 @@
<&gcc GCC_PCIE_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_CLKREF_CLK>,
<&gcc GCC_PCIE_RCHNG_PHY_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "refgen";
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "refgen";
resets = <&gcc GCC_PCIE_PHY_BCR>;
reset-names = "phy";