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author | Will Deacon <will.deacon@arm.com> | 2013-05-13 12:01:12 +0100 |
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committer | Will Deacon <will.deacon@arm.com> | 2013-08-12 12:25:45 +0100 |
commit | 6abdd491698a27f7df04a32ca12cc453810e4396 (patch) | |
tree | 34f4aa721441439634e721fe0eeba614b076a889 /arch/arm/include/asm/spinlock.h | |
parent | 62cbbc42e0019aff6310259f275ae812463f8836 (diff) | |
download | linux-6abdd491698a27f7df04a32ca12cc453810e4396.tar.gz linux-6abdd491698a27f7df04a32ca12cc453810e4396.tar.bz2 linux-6abdd491698a27f7df04a32ca12cc453810e4396.zip |
ARM: mm: use inner-shareable barriers for TLB and user cache operations
System-wide barriers aren't required for situations where we only need
to make visibility and ordering guarantees in the inner-shareable domain
(i.e. we are not dealing with devices or potentially incoherent CPUs).
This patch changes the v7 TLB operations, coherent_user_range and
dcache_clean_area functions to user inner-shareable barriers. For cache
maintenance, only the store access type is required to ensure completion.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm/include/asm/spinlock.h')
0 files changed, 0 insertions, 0 deletions