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| author | Russell King <rmk+kernel@armlinux.org.uk> | 2016-08-19 15:15:03 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2016-08-23 10:25:17 +0100 |
| commit | 83809b90a6dbedbcd94fcb99c9cde9477534f3d3 (patch) | |
| tree | 6a056e9ad30d5dfd5183cdaa0cac99d959b39023 /arch/arm/include | |
| parent | 10b52a49ac62cd8cedc08c50178dc6fbb8925b87 (diff) | |
| download | linux-83809b90a6dbedbcd94fcb99c9cde9477534f3d3.tar.gz linux-83809b90a6dbedbcd94fcb99c9cde9477534f3d3.tar.bz2 linux-83809b90a6dbedbcd94fcb99c9cde9477534f3d3.zip | |
ARM: sa1100: move StrongARM CPU ID checks to cputype.h
Move the StrongARM CPU ID checks out of the platform's hardware.h
file into asm/cputype.h
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/asm/cputype.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index 1ee94c716a7f..d6a4902a75d7 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h @@ -60,6 +60,7 @@ ((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK) #define ARM_CPU_IMP_ARM 0x41 +#define ARM_CPU_IMP_DEC 0x44 #define ARM_CPU_IMP_INTEL 0x69 /* ARM implemented processors */ @@ -76,6 +77,17 @@ #define ARM_CPU_PART_CORTEX_A15 0x4100c0f0 #define ARM_CPU_PART_MASK 0xff00fff0 +/* DEC implemented cores */ +#define ARM_CPU_PART_SA1100 0x4400a110 + +/* Intel implemented cores */ +#define ARM_CPU_PART_SA1110 0x6900b110 +#define ARM_CPU_REV_SA1110_A0 0 +#define ARM_CPU_REV_SA1110_B0 4 +#define ARM_CPU_REV_SA1110_B1 5 +#define ARM_CPU_REV_SA1110_B2 6 +#define ARM_CPU_REV_SA1110_B4 8 + #define ARM_CPU_XSCALE_ARCH_MASK 0xe000 #define ARM_CPU_XSCALE_ARCH_V1 0x2000 #define ARM_CPU_XSCALE_ARCH_V2 0x4000 @@ -173,6 +185,11 @@ static inline unsigned int __attribute_const__ read_cpuid_implementor(void) return (read_cpuid_id() & 0xFF000000) >> 24; } +static inline unsigned int __attribute_const__ read_cpuid_revision(void) +{ + return read_cpuid_id() & 0x0000000f; +} + /* * The CPU part number is meaningless without referring to the CPU * implementer: implementers are free to define their own part numbers @@ -208,6 +225,10 @@ static inline unsigned int __attribute_const__ read_cpuid_mpidr(void) return read_cpuid(CPUID_MPIDR); } +/* StrongARM-11x0 CPUs */ +#define cpu_is_sa1100() (read_cpuid_part() == ARM_CPU_PART_SA1100) +#define cpu_is_sa1110() (read_cpuid_part() == ARM_CPU_PART_SA1110) + /* * Intel's XScale3 core supports some v6 features (supersections, L2) * but advertises itself as v5 as it does not support the v6 ISA. For |