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| author | Catalin Marinas <catalin.marinas@arm.com> | 2009-07-24 12:32:54 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2009-07-24 12:32:54 +0100 |
| commit | b86040a59feb255a8193173caa4d5199464433d5 (patch) | |
| tree | 89c07450eabc2abb88bb4d6e32d61fd3855f000e /arch/arm/kernel/head-nommu.S | |
| parent | 0becb088501886f37ade38762c8eaaf4263572cc (diff) | |
| download | linux-b86040a59feb255a8193173caa4d5199464433d5.tar.gz linux-b86040a59feb255a8193173caa4d5199464433d5.tar.bz2 linux-b86040a59feb255a8193173caa4d5199464433d5.zip | |
Thumb-2: Implementation of the unified start-up and exceptions code
This patch implements the ARM/Thumb-2 unified kernel start-up and
exception handling code.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm/kernel/head-nommu.S')
| -rw-r--r-- | arch/arm/kernel/head-nommu.S | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S index cc87e1765ed2..b16393d2b71e 100644 --- a/arch/arm/kernel/head-nommu.S +++ b/arch/arm/kernel/head-nommu.S @@ -34,7 +34,7 @@ */ .section ".text.head", "ax" ENTRY(stext) - msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode + setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode @ and irqs disabled #ifndef CONFIG_CPU_CP15 ldr r9, =CONFIG_PROCESSOR_ID @@ -50,8 +50,10 @@ ENTRY(stext) ldr r13, __switch_data @ address to jump to after @ the initialization is done - adr lr, __after_proc_init @ return (PIC) address - add pc, r10, #PROCINFO_INITFUNC + adr lr, BSYM(__after_proc_init) @ return (PIC) address + ARM( add pc, r10, #PROCINFO_INITFUNC ) + THUMB( add r12, r10, #PROCINFO_INITFUNC ) + THUMB( mov pc, r12 ) ENDPROC(stext) /* @@ -82,7 +84,8 @@ __after_proc_init: mcr p15, 0, r0, c1, c0, 0 @ write control reg #endif /* CONFIG_CPU_CP15 */ - mov pc, r13 @ clear the BSS and jump + mov r3, r13 + mov pc, r3 @ clear the BSS and jump @ to start_kernel ENDPROC(__after_proc_init) .ltorg |