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| author | Victor Kamensky <victor.kamensky@linaro.org> | 2014-06-12 09:30:02 -0700 |
|---|---|---|
| committer | Christoffer Dall <christoffer.dall@linaro.org> | 2014-07-11 04:57:38 -0700 |
| commit | 19b0e60a63f758a28329aa40f4270a6c98c2dcb7 (patch) | |
| tree | e0daa0196fc1f1ad793340121e276ab75981df02 /arch/arm/kvm/init.S | |
| parent | 64054c25cf7e060cd6780744fefe7ed3990e4f21 (diff) | |
| download | linux-19b0e60a63f758a28329aa40f4270a6c98c2dcb7.tar.gz linux-19b0e60a63f758a28329aa40f4270a6c98c2dcb7.tar.bz2 linux-19b0e60a63f758a28329aa40f4270a6c98c2dcb7.zip | |
ARM: KVM: handle 64bit values passed to mrcc or from mcrr instructions in BE case
In some cases the mcrr and mrrc instructions in combination with the ldrd
and strd instructions need to deal with 64bit value in memory. The ldrd
and strd instructions already handle endianness within word (register)
boundaries but to get effect of the whole 64bit value represented correctly,
rr_lo_hi macro is introduced and is used to swap registers positions when
the mcrr and mrrc instructions are used. That has the effect of swapping
two words.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm/kvm/init.S')
| -rw-r--r-- | arch/arm/kvm/init.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/kvm/init.S b/arch/arm/kvm/init.S index 1b9844d369cc..2cc14dfad049 100644 --- a/arch/arm/kvm/init.S +++ b/arch/arm/kvm/init.S @@ -71,7 +71,7 @@ __do_hyp_init: bne phase2 @ Yes, second stage init @ Set the HTTBR to point to the hypervisor PGD pointer passed - mcrr p15, 4, r2, r3, c2 + mcrr p15, 4, rr_lo_hi(r2, r3), c2 @ Set the HTCR and VTCR to the same shareability and cacheability @ settings as the non-secure TTBCR and with T0SZ == 0. @@ -137,7 +137,7 @@ phase2: mov pc, r0 target: @ We're now in the trampoline code, switch page tables - mcrr p15, 4, r2, r3, c2 + mcrr p15, 4, rr_lo_hi(r2, r3), c2 isb @ Invalidate the old TLBs |