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| author | Saeed Bishara <saeed@marvell.com> | 2009-08-06 15:12:43 +0300 |
|---|---|---|
| committer | Nicolas Pitre <nico@fluxnic.net> | 2009-11-27 15:43:06 -0500 |
| commit | edabd38e1a017e922e3e3b485ee3ddb4df433aa4 (patch) | |
| tree | c79cef3e59f62014c12ff1203e84b0bac5610a55 /arch/arm/mach-dove/include/mach/entry-macro.S | |
| parent | 8d27b2f7988b652dbabf79291a3e2550c06e1af5 (diff) | |
| download | linux-edabd38e1a017e922e3e3b485ee3ddb4df433aa4.tar.gz linux-edabd38e1a017e922e3e3b485ee3ddb4df433aa4.tar.bz2 linux-edabd38e1a017e922e3e3b485ee3ddb4df433aa4.zip | |
ARM: add base support for Marvell Dove SoC
The Marvell Dove (88AP510) is a high-performance, highly integrated,
low power SoC with high-end ARM-compatible processor (known as PJ4),
graphics processing unit, high-definition video decoding acceleration
hardware, and a broad range of peripherals.
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Saeed Bishara <saeed@marvell.com>
Signed-off-by: Nicolas Pitre <nico@marvell.com>
Diffstat (limited to 'arch/arm/mach-dove/include/mach/entry-macro.S')
| -rw-r--r-- | arch/arm/mach-dove/include/mach/entry-macro.S | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/mach-dove/include/mach/entry-macro.S b/arch/arm/mach-dove/include/mach/entry-macro.S new file mode 100644 index 000000000000..e84c78c2a8b7 --- /dev/null +++ b/arch/arm/mach-dove/include/mach/entry-macro.S @@ -0,0 +1,39 @@ +/* + * arch/arm/mach-dove/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for Marvell Dove platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <mach/bridge-regs.h> + + .macro disable_fiq + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_preamble, base, tmp + ldr \base, =IRQ_VIRT_BASE + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + @ check low interrupts + ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF] + ldr \tmp, [\base, #IRQ_MASK_LOW_OFF] + mov \irqnr, #31 + ands \irqstat, \irqstat, \tmp + + @ if no low interrupts set, check high interrupts + ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF] + ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF] + moveq \irqnr, #63 + andeqs \irqstat, \irqstat, \tmp + + @ find first active interrupt source + clzne \irqstat, \irqstat + subne \irqnr, \irqnr, \irqstat + .endm |