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| author | Florian Tobias Schandinat <FlorianSchandinat@gmx.de> | 2012-05-27 20:58:20 +0000 |
|---|---|---|
| committer | Florian Tobias Schandinat <FlorianSchandinat@gmx.de> | 2012-05-27 20:58:20 +0000 |
| commit | d85d135d8babbc917b370f36cbc02b7b4a2f2d99 (patch) | |
| tree | 2f06e02940d87099670aa31459ad1ab41a1ca036 /arch/arm/mach-exynos/include/mach/regs-clock.h | |
| parent | 5e7b911f9a3e582635801675b7fe935b16cd4af5 (diff) | |
| parent | e92a5b28f71aea01b281f9c89d97a4bc5b24748f (diff) | |
| download | linux-d85d135d8babbc917b370f36cbc02b7b4a2f2d99.tar.gz linux-d85d135d8babbc917b370f36cbc02b7b4a2f2d99.tar.bz2 linux-d85d135d8babbc917b370f36cbc02b7b4a2f2d99.zip | |
Merge tag 'omapdss-for-3.5' of git://github.com/tomba/linux into fbdev-next
Omapdss driver changes for 3.5 merge window.
Lots of normal development commits, but perhaps most notable changes are:
* HDMI rework to properly decouple the HDMI audio part from the HDMI video part.
* Restructure omapdss core driver so that it's possible to implement device
tree support. This included changing how platform data is passed to the
drivers, changing display device registration and improving the panel driver's
ability to configure the underlying video output interface.
* Basic support for DSI packet interleaving
Diffstat (limited to 'arch/arm/mach-exynos/include/mach/regs-clock.h')
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-clock.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index e141c1fd68d8..d9578a58ae7f 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -255,9 +255,15 @@ /* For EXYNOS5250 */ +#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) #define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100) #define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200) +#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400) #define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500) +#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504) +#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600) +#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604) + #define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100) #define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204) |