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authorLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 13:43:38 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2013-07-02 13:43:38 -0700
commit3883cbb6c1bda013a3ce2dbdab7dc97c52e4a232 (patch)
tree5b69f83b049d24ac81123ac954ca8c9128e48443 /arch/arm/mach-exynos/include
parentd2033f2c1d1de2239ded15e478ddb4028f192a15 (diff)
parent1eb92b24e243085d242cf5ffd64829bba70972e1 (diff)
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Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC specific changes from Arnd Bergmann: "These changes are all to SoC-specific code, a total of 33 branches on 17 platforms were pulled into this. Like last time, Renesas sh-mobile is now the platform with the most changes, followed by OMAP and EXYNOS. Two new platforms, TI Keystone and Rockchips RK3xxx are added in this branch, both containing almost no platform specific code at all, since they are using generic subsystem interfaces for clocks, pinctrl, interrupts etc. The device drivers are getting merged through the respective subsystem maintainer trees. One more SoC (u300) is now multiplatform capable and several others (shmobile, exynos, msm, integrator, kirkwood, clps711x) are moving towards that goal with this series but need more work. Also noteworthy is the work on PCI here, which is traditionally part of the SoC specific code. With the changes done by Thomas Petazzoni, we can now more easily have PCI host controller drivers as loadable modules and keep them separate from the platform code in drivers/pci/host. This has already led to the discovery that three platforms (exynos, spear and imx) are actually using an identical PCIe host controller and will be able to share a driver once support for spear and imx is added." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (480 commits) ARM: integrator: let pciv3 use mem/premem from device tree ARM: integrator: set local side PCI addresses right ARM: dts: Add pcie controller node for exynos5440-ssdk5440 ARM: dts: Add pcie controller node for Samsung EXYNOS5440 SoC ARM: EXYNOS: Enable PCIe support for Exynos5440 pci: Add PCIe driver for Samsung Exynos ARM: OMAP5: voltagedomain data: remove temporary OMAP4 voltage data ARM: keystone: Move CPU bringup code to dedicated asm file ARM: multiplatform: always pick one CPU type ARM: imx: select syscon for IMX6SL ARM: keystone: select ARM_ERRATA_798181 only for SMP ARM: imx: Synertronixx scb9328 needs to select SOC_IMX1 ARM: OMAP2+: AM43x: resolve SMP related build error dmaengine: edma: enable build for AM33XX ARM: edma: Add EDMA crossbar event mux support ARM: edma: Add DT and runtime PM support to the private EDMA API dmaengine: edma: Add TI EDMA device tree binding arm: add basic support for Rockchip RK3066a boards arm: add debug uarts for rockchip rk29xx and rk3xxx series arm: Add basic clocks for Rockchip rk3066a SoCs ...
Diffstat (limited to 'arch/arm/mach-exynos/include')
-rw-r--r--arch/arm/mach-exynos/include/mach/gpio.h289
-rw-r--r--arch/arm/mach-exynos/include/mach/irqs.h476
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h214
-rw-r--r--arch/arm/mach-exynos/include/mach/pm-core.h12
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-gpio.h40
-rw-r--r--arch/arm/mach-exynos/include/mach/regs-usb-phy.h74
6 files changed, 6 insertions, 1099 deletions
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
deleted file mode 100644
index eb24f1eb8e3b..000000000000
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ /dev/null
@@ -1,289 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS - GPIO lib support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H __FILE__
-
-/* Macro for EXYNOS GPIO numbering */
-
-#define EXYNOS_GPIO_NEXT(__gpio) \
- ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
-
-/* EXYNOS4 GPIO bank sizes */
-
-#define EXYNOS4_GPIO_A0_NR (8)
-#define EXYNOS4_GPIO_A1_NR (6)
-#define EXYNOS4_GPIO_B_NR (8)
-#define EXYNOS4_GPIO_C0_NR (5)
-#define EXYNOS4_GPIO_C1_NR (5)
-#define EXYNOS4_GPIO_D0_NR (4)
-#define EXYNOS4_GPIO_D1_NR (4)
-#define EXYNOS4_GPIO_E0_NR (5)
-#define EXYNOS4_GPIO_E1_NR (8)
-#define EXYNOS4_GPIO_E2_NR (6)
-#define EXYNOS4_GPIO_E3_NR (8)
-#define EXYNOS4_GPIO_E4_NR (8)
-#define EXYNOS4_GPIO_F0_NR (8)
-#define EXYNOS4_GPIO_F1_NR (8)
-#define EXYNOS4_GPIO_F2_NR (8)
-#define EXYNOS4_GPIO_F3_NR (6)
-#define EXYNOS4_GPIO_J0_NR (8)
-#define EXYNOS4_GPIO_J1_NR (5)
-#define EXYNOS4_GPIO_K0_NR (7)
-#define EXYNOS4_GPIO_K1_NR (7)
-#define EXYNOS4_GPIO_K2_NR (7)
-#define EXYNOS4_GPIO_K3_NR (7)
-#define EXYNOS4_GPIO_L0_NR (8)
-#define EXYNOS4_GPIO_L1_NR (3)
-#define EXYNOS4_GPIO_L2_NR (8)
-#define EXYNOS4_GPIO_X0_NR (8)
-#define EXYNOS4_GPIO_X1_NR (8)
-#define EXYNOS4_GPIO_X2_NR (8)
-#define EXYNOS4_GPIO_X3_NR (8)
-#define EXYNOS4_GPIO_Y0_NR (6)
-#define EXYNOS4_GPIO_Y1_NR (4)
-#define EXYNOS4_GPIO_Y2_NR (6)
-#define EXYNOS4_GPIO_Y3_NR (8)
-#define EXYNOS4_GPIO_Y4_NR (8)
-#define EXYNOS4_GPIO_Y5_NR (8)
-#define EXYNOS4_GPIO_Y6_NR (8)
-#define EXYNOS4_GPIO_Z_NR (7)
-
-/* EXYNOS4 GPIO bank numbers */
-
-enum exynos4_gpio_number {
- EXYNOS4_GPIO_A0_START = 0,
- EXYNOS4_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
- EXYNOS4_GPIO_B_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
- EXYNOS4_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
- EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
- EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
- EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
- EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
- EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
- EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
- EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
- EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
- EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
- EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
- EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
- EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
- EXYNOS4_GPIO_J0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
- EXYNOS4_GPIO_J1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
- EXYNOS4_GPIO_K0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
- EXYNOS4_GPIO_K1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
- EXYNOS4_GPIO_K2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
- EXYNOS4_GPIO_K3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
- EXYNOS4_GPIO_L0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
- EXYNOS4_GPIO_L1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
- EXYNOS4_GPIO_L2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
- EXYNOS4_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
- EXYNOS4_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
- EXYNOS4_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
- EXYNOS4_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
- EXYNOS4_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
- EXYNOS4_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
- EXYNOS4_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
- EXYNOS4_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
- EXYNOS4_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
- EXYNOS4_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
- EXYNOS4_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
- EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
-};
-
-/* EXYNOS4 GPIO number definitions */
-
-#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
-#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
-#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
-#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
-#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
-#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
-#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
-#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
-#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
-#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
-#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
-#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
-#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
-#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
-#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
-#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
-#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
-#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
-#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
-#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
-#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
-#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
-#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
-#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
-#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
-#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
-#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
-#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
-#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
-#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr))
-#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr))
-#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr))
-#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr))
-#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr))
-#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr))
-#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr))
-#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
-
-/* the end of the EXYNOS4 specific gpios */
-
-#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
-
-/* EXYNOS5 GPIO bank sizes */
-
-#define EXYNOS5_GPIO_A0_NR (8)
-#define EXYNOS5_GPIO_A1_NR (6)
-#define EXYNOS5_GPIO_A2_NR (8)
-#define EXYNOS5_GPIO_B0_NR (5)
-#define EXYNOS5_GPIO_B1_NR (5)
-#define EXYNOS5_GPIO_B2_NR (4)
-#define EXYNOS5_GPIO_B3_NR (4)
-#define EXYNOS5_GPIO_C0_NR (7)
-#define EXYNOS5_GPIO_C1_NR (4)
-#define EXYNOS5_GPIO_C2_NR (7)
-#define EXYNOS5_GPIO_C3_NR (7)
-#define EXYNOS5_GPIO_C4_NR (7)
-#define EXYNOS5_GPIO_D0_NR (4)
-#define EXYNOS5_GPIO_D1_NR (8)
-#define EXYNOS5_GPIO_Y0_NR (6)
-#define EXYNOS5_GPIO_Y1_NR (4)
-#define EXYNOS5_GPIO_Y2_NR (6)
-#define EXYNOS5_GPIO_Y3_NR (8)
-#define EXYNOS5_GPIO_Y4_NR (8)
-#define EXYNOS5_GPIO_Y5_NR (8)
-#define EXYNOS5_GPIO_Y6_NR (8)
-#define EXYNOS5_GPIO_X0_NR (8)
-#define EXYNOS5_GPIO_X1_NR (8)
-#define EXYNOS5_GPIO_X2_NR (8)
-#define EXYNOS5_GPIO_X3_NR (8)
-#define EXYNOS5_GPIO_E0_NR (8)
-#define EXYNOS5_GPIO_E1_NR (2)
-#define EXYNOS5_GPIO_F0_NR (4)
-#define EXYNOS5_GPIO_F1_NR (4)
-#define EXYNOS5_GPIO_G0_NR (8)
-#define EXYNOS5_GPIO_G1_NR (8)
-#define EXYNOS5_GPIO_G2_NR (2)
-#define EXYNOS5_GPIO_H0_NR (4)
-#define EXYNOS5_GPIO_H1_NR (8)
-#define EXYNOS5_GPIO_V0_NR (8)
-#define EXYNOS5_GPIO_V1_NR (8)
-#define EXYNOS5_GPIO_V2_NR (8)
-#define EXYNOS5_GPIO_V3_NR (8)
-#define EXYNOS5_GPIO_V4_NR (2)
-#define EXYNOS5_GPIO_Z_NR (7)
-
-/* EXYNOS5 GPIO bank numbers */
-
-enum exynos5_gpio_number {
- EXYNOS5_GPIO_A0_START = 0,
- EXYNOS5_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
- EXYNOS5_GPIO_A2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
- EXYNOS5_GPIO_B0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
- EXYNOS5_GPIO_B1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
- EXYNOS5_GPIO_B2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
- EXYNOS5_GPIO_B3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
- EXYNOS5_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
- EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
- EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
- EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
- EXYNOS5_GPIO_C4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
- EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C4),
- EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
- EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
- EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
- EXYNOS5_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
- EXYNOS5_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
- EXYNOS5_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
- EXYNOS5_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
- EXYNOS5_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
- EXYNOS5_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
- EXYNOS5_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
- EXYNOS5_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
- EXYNOS5_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
- EXYNOS5_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
- EXYNOS5_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
- EXYNOS5_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
- EXYNOS5_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
- EXYNOS5_GPIO_G0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
- EXYNOS5_GPIO_G1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
- EXYNOS5_GPIO_G2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
- EXYNOS5_GPIO_H0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
- EXYNOS5_GPIO_H1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
- EXYNOS5_GPIO_V0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
- EXYNOS5_GPIO_V1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
- EXYNOS5_GPIO_V2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
- EXYNOS5_GPIO_V3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
- EXYNOS5_GPIO_V4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
- EXYNOS5_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
-};
-
-/* EXYNOS5 GPIO number definitions */
-
-#define EXYNOS5_GPA0(_nr) (EXYNOS5_GPIO_A0_START + (_nr))
-#define EXYNOS5_GPA1(_nr) (EXYNOS5_GPIO_A1_START + (_nr))
-#define EXYNOS5_GPA2(_nr) (EXYNOS5_GPIO_A2_START + (_nr))
-#define EXYNOS5_GPB0(_nr) (EXYNOS5_GPIO_B0_START + (_nr))
-#define EXYNOS5_GPB1(_nr) (EXYNOS5_GPIO_B1_START + (_nr))
-#define EXYNOS5_GPB2(_nr) (EXYNOS5_GPIO_B2_START + (_nr))
-#define EXYNOS5_GPB3(_nr) (EXYNOS5_GPIO_B3_START + (_nr))
-#define EXYNOS5_GPC0(_nr) (EXYNOS5_GPIO_C0_START + (_nr))
-#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
-#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
-#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
-#define EXYNOS5_GPC4(_nr) (EXYNOS5_GPIO_C4_START + (_nr))
-#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
-#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
-#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
-#define EXYNOS5_GPY1(_nr) (EXYNOS5_GPIO_Y1_START + (_nr))
-#define EXYNOS5_GPY2(_nr) (EXYNOS5_GPIO_Y2_START + (_nr))
-#define EXYNOS5_GPY3(_nr) (EXYNOS5_GPIO_Y3_START + (_nr))
-#define EXYNOS5_GPY4(_nr) (EXYNOS5_GPIO_Y4_START + (_nr))
-#define EXYNOS5_GPY5(_nr) (EXYNOS5_GPIO_Y5_START + (_nr))
-#define EXYNOS5_GPY6(_nr) (EXYNOS5_GPIO_Y6_START + (_nr))
-#define EXYNOS5_GPX0(_nr) (EXYNOS5_GPIO_X0_START + (_nr))
-#define EXYNOS5_GPX1(_nr) (EXYNOS5_GPIO_X1_START + (_nr))
-#define EXYNOS5_GPX2(_nr) (EXYNOS5_GPIO_X2_START + (_nr))
-#define EXYNOS5_GPX3(_nr) (EXYNOS5_GPIO_X3_START + (_nr))
-#define EXYNOS5_GPE0(_nr) (EXYNOS5_GPIO_E0_START + (_nr))
-#define EXYNOS5_GPE1(_nr) (EXYNOS5_GPIO_E1_START + (_nr))
-#define EXYNOS5_GPF0(_nr) (EXYNOS5_GPIO_F0_START + (_nr))
-#define EXYNOS5_GPF1(_nr) (EXYNOS5_GPIO_F1_START + (_nr))
-#define EXYNOS5_GPG0(_nr) (EXYNOS5_GPIO_G0_START + (_nr))
-#define EXYNOS5_GPG1(_nr) (EXYNOS5_GPIO_G1_START + (_nr))
-#define EXYNOS5_GPG2(_nr) (EXYNOS5_GPIO_G2_START + (_nr))
-#define EXYNOS5_GPH0(_nr) (EXYNOS5_GPIO_H0_START + (_nr))
-#define EXYNOS5_GPH1(_nr) (EXYNOS5_GPIO_H1_START + (_nr))
-#define EXYNOS5_GPV0(_nr) (EXYNOS5_GPIO_V0_START + (_nr))
-#define EXYNOS5_GPV1(_nr) (EXYNOS5_GPIO_V1_START + (_nr))
-#define EXYNOS5_GPV2(_nr) (EXYNOS5_GPIO_V2_START + (_nr))
-#define EXYNOS5_GPV3(_nr) (EXYNOS5_GPIO_V3_START + (_nr))
-#define EXYNOS5_GPV4(_nr) (EXYNOS5_GPIO_V4_START + (_nr))
-#define EXYNOS5_GPZ(_nr) (EXYNOS5_GPIO_Z_START + (_nr))
-
-/* the end of the EXYNOS5 specific gpios */
-
-#define EXYNOS5_GPIO_END (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
-
-/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
-
-#define S3C_GPIO_END (EXYNOS5_GPIO_END)
-
-/* define the number of gpios */
-
-#define ARCH_NR_GPIOS (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
-
-#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
deleted file mode 100644
index c72f59d91fce..000000000000
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS - IRQ definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H __FILE__
-
-#include <plat/irqs.h>
-
-/* PPI: Private Peripheral Interrupt */
-
-#define IRQ_PPI(x) (x + 16)
-
-/* SPI: Shared Peripheral Interrupt */
-
-#define IRQ_SPI(x) (x + 32)
-
-/* COMBINER */
-
-#define MAX_IRQ_IN_COMBINER 8
-#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
-#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
-
-/* For EXYNOS4 and EXYNOS5 */
-
-#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
-
-/* For EXYNOS4 SoCs */
-
-#define EXYNOS4_IRQ_EINT0 IRQ_SPI(16)
-#define EXYNOS4_IRQ_EINT1 IRQ_SPI(17)
-#define EXYNOS4_IRQ_EINT2 IRQ_SPI(18)
-#define EXYNOS4_IRQ_EINT3 IRQ_SPI(19)
-#define EXYNOS4_IRQ_EINT4 IRQ_SPI(20)
-#define EXYNOS4_IRQ_EINT5 IRQ_SPI(21)
-#define EXYNOS4_IRQ_EINT6 IRQ_SPI(22)
-#define EXYNOS4_IRQ_EINT7 IRQ_SPI(23)
-#define EXYNOS4_IRQ_EINT8 IRQ_SPI(24)
-#define EXYNOS4_IRQ_EINT9 IRQ_SPI(25)
-#define EXYNOS4_IRQ_EINT10 IRQ_SPI(26)
-#define EXYNOS4_IRQ_EINT11 IRQ_SPI(27)
-#define EXYNOS4_IRQ_EINT12 IRQ_SPI(28)
-#define EXYNOS4_IRQ_EINT13 IRQ_SPI(29)
-#define EXYNOS4_IRQ_EINT14 IRQ_SPI(30)
-#define EXYNOS4_IRQ_EINT15 IRQ_SPI(31)
-
-#define EXYNOS4_IRQ_MDMA0 IRQ_SPI(33)
-#define EXYNOS4_IRQ_MDMA1 IRQ_SPI(34)
-#define EXYNOS4_IRQ_PDMA0 IRQ_SPI(35)
-#define EXYNOS4_IRQ_PDMA1 IRQ_SPI(36)
-#define EXYNOS4_IRQ_TIMER0_VIC IRQ_SPI(37)
-#define EXYNOS4_IRQ_TIMER1_VIC IRQ_SPI(38)
-#define EXYNOS4_IRQ_TIMER2_VIC IRQ_SPI(39)
-#define EXYNOS4_IRQ_TIMER3_VIC IRQ_SPI(40)
-#define EXYNOS4_IRQ_TIMER4_VIC IRQ_SPI(41)
-#define EXYNOS4_IRQ_MCT_L0 IRQ_SPI(42)
-#define EXYNOS4_IRQ_WDT IRQ_SPI(43)
-#define EXYNOS4_IRQ_RTC_ALARM IRQ_SPI(44)
-#define EXYNOS4_IRQ_RTC_TIC IRQ_SPI(45)
-#define EXYNOS4_IRQ_GPIO_XB IRQ_SPI(46)
-#define EXYNOS4_IRQ_GPIO_XA IRQ_SPI(47)
-#define EXYNOS4_IRQ_MCT_L1 IRQ_SPI(48)
-
-#define EXYNOS4_IRQ_UART0 IRQ_SPI(52)
-#define EXYNOS4_IRQ_UART1 IRQ_SPI(53)
-#define EXYNOS4_IRQ_UART2 IRQ_SPI(54)
-#define EXYNOS4_IRQ_UART3 IRQ_SPI(55)
-#define EXYNOS4_IRQ_UART4 IRQ_SPI(56)
-#define EXYNOS4_IRQ_MCT_G0 IRQ_SPI(57)
-#define EXYNOS4_IRQ_IIC IRQ_SPI(58)
-#define EXYNOS4_IRQ_IIC1 IRQ_SPI(59)
-#define EXYNOS4_IRQ_IIC2 IRQ_SPI(60)
-#define EXYNOS4_IRQ_IIC3 IRQ_SPI(61)
-#define EXYNOS4_IRQ_IIC4 IRQ_SPI(62)
-#define EXYNOS4_IRQ_IIC5 IRQ_SPI(63)
-#define EXYNOS4_IRQ_IIC6 IRQ_SPI(64)
-#define EXYNOS4_IRQ_IIC7 IRQ_SPI(65)
-#define EXYNOS4_IRQ_SPI0 IRQ_SPI(66)
-#define EXYNOS4_IRQ_SPI1 IRQ_SPI(67)
-#define EXYNOS4_IRQ_SPI2 IRQ_SPI(68)
-
-#define EXYNOS4_IRQ_USB_HOST IRQ_SPI(70)
-#define EXYNOS4_IRQ_USB_HSOTG IRQ_SPI(71)
-#define EXYNOS4_IRQ_MODEM_IF IRQ_SPI(72)
-#define EXYNOS4_IRQ_HSMMC0 IRQ_SPI(73)
-#define EXYNOS4_IRQ_HSMMC1 IRQ_SPI(74)
-#define EXYNOS4_IRQ_HSMMC2 IRQ_SPI(75)
-#define EXYNOS4_IRQ_HSMMC3 IRQ_SPI(76)
-#define EXYNOS4_IRQ_DWMCI IRQ_SPI(77)
-
-#define EXYNOS4_IRQ_MIPI_CSIS0 IRQ_SPI(78)
-#define EXYNOS4_IRQ_MIPI_CSIS1 IRQ_SPI(80)
-
-#define EXYNOS4_IRQ_ONENAND_AUDI IRQ_SPI(82)
-#define EXYNOS4_IRQ_ROTATOR IRQ_SPI(83)
-#define EXYNOS4_IRQ_FIMC0 IRQ_SPI(84)
-#define EXYNOS4_IRQ_FIMC1 IRQ_SPI(85)
-#define EXYNOS4_IRQ_FIMC2 IRQ_SPI(86)
-#define EXYNOS4_IRQ_FIMC3 IRQ_SPI(87)
-#define EXYNOS4_IRQ_JPEG IRQ_SPI(88)
-#define EXYNOS4_IRQ_2D IRQ_SPI(89)
-#define EXYNOS4_IRQ_PCIE IRQ_SPI(90)
-
-#define EXYNOS4_IRQ_MIXER IRQ_SPI(91)
-#define EXYNOS4_IRQ_HDMI IRQ_SPI(92)
-#define EXYNOS4_IRQ_IIC_HDMIPHY IRQ_SPI(93)
-#define EXYNOS4_IRQ_MFC IRQ_SPI(94)
-#define EXYNOS4_IRQ_SDO IRQ_SPI(95)
-
-#define EXYNOS4_IRQ_AUDIO_SS IRQ_SPI(96)
-#define EXYNOS4_IRQ_I2S0 IRQ_SPI(97)
-#define EXYNOS4_IRQ_I2S1 IRQ_SPI(98)
-#define EXYNOS4_IRQ_I2S2 IRQ_SPI(99)
-#define EXYNOS4_IRQ_AC97 IRQ_SPI(100)
-
-#define EXYNOS4_IRQ_SPDIF IRQ_SPI(104)
-#define EXYNOS4_IRQ_ADC0 IRQ_SPI(105)
-#define EXYNOS4_IRQ_PEN0 IRQ_SPI(106)
-#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
-#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
-#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
-#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
-#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
-#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
-#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
-
-#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
-#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
-
-#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
-#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
-#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
-#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
-
-#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
-#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
-
-#define EXYNOS4_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
-#define EXYNOS4_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(4, 1)
-#define EXYNOS4_IRQ_SYSMMU_FIMC0_0 COMBINER_IRQ(4, 2)
-#define EXYNOS4_IRQ_SYSMMU_FIMC1_0 COMBINER_IRQ(4, 3)
-#define EXYNOS4_IRQ_SYSMMU_FIMC2_0 COMBINER_IRQ(4, 4)
-#define EXYNOS4_IRQ_SYSMMU_FIMC3_0 COMBINER_IRQ(4, 5)
-#define EXYNOS4_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 6)
-#define EXYNOS4_IRQ_SYSMMU_2D_0 COMBINER_IRQ(4, 7)
-
-#define EXYNOS4_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(5, 0)
-#define EXYNOS4_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(5, 1)
-#define EXYNOS4_IRQ_SYSMMU_LCD0_M0_0 COMBINER_IRQ(5, 2)
-#define EXYNOS4_IRQ_SYSMMU_LCD1_M1_0 COMBINER_IRQ(5, 3)
-#define EXYNOS4_IRQ_SYSMMU_TV_M0_0 COMBINER_IRQ(5, 4)
-#define EXYNOS4_IRQ_SYSMMU_MFC_M0_0 COMBINER_IRQ(5, 5)
-#define EXYNOS4_IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
-#define EXYNOS4_IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
-
-#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE0_0 COMBINER_IRQ(16, 0)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_LITE1_0 COMBINER_IRQ(16, 1)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_ISP_0 COMBINER_IRQ(16, 2)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_DRC_0 COMBINER_IRQ(16, 3)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_FD_0 COMBINER_IRQ(16, 4)
-#define EXYNOS4_IRQ_SYSMMU_FIMC_CX_0 COMBINER_IRQ(16, 5)
-
-#define EXYNOS4_IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
-#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
-#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
-
-#define EXYNOS4210_MAX_COMBINER_NR 16
-#define EXYNOS4212_MAX_COMBINER_NR 18
-#define EXYNOS4412_MAX_COMBINER_NR 20
-#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR
-
-#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
-#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
-
-/*
- * For Compatibility:
- * the default is for EXYNOS4, and
- * for exynos5, should be re-mapped at function
- */
-
-#define IRQ_TIMER0_VIC EXYNOS4_IRQ_TIMER0_VIC
-#define IRQ_TIMER1_VIC EXYNOS4_IRQ_TIMER1_VIC
-#define IRQ_TIMER2_VIC EXYNOS4_IRQ_TIMER2_VIC
-#define IRQ_TIMER3_VIC EXYNOS4_IRQ_TIMER3_VIC
-#define IRQ_TIMER4_VIC EXYNOS4_IRQ_TIMER4_VIC
-
-#define IRQ_WDT EXYNOS4_IRQ_WDT
-#define IRQ_RTC_ALARM EXYNOS4_IRQ_RTC_ALARM
-#define IRQ_RTC_TIC EXYNOS4_IRQ_RTC_TIC
-#define IRQ_GPIO_XB EXYNOS4_IRQ_GPIO_XB
-#define IRQ_GPIO_XA EXYNOS4_IRQ_GPIO_XA
-
-#define IRQ_IIC EXYNOS4_IRQ_IIC
-#define IRQ_IIC1 EXYNOS4_IRQ_IIC1
-#define IRQ_IIC3 EXYNOS4_IRQ_IIC3
-#define IRQ_IIC5 EXYNOS4_IRQ_IIC5
-#define IRQ_IIC6 EXYNOS4_IRQ_IIC6
-#define IRQ_IIC7 EXYNOS4_IRQ_IIC7
-
-#define IRQ_SPI0 EXYNOS4_IRQ_SPI0
-#define IRQ_SPI1 EXYNOS4_IRQ_SPI1
-#define IRQ_SPI2 EXYNOS4_IRQ_SPI2
-
-#define IRQ_USB_HOST EXYNOS4_IRQ_USB_HOST
-#define IRQ_OTG EXYNOS4_IRQ_USB_HSOTG
-
-#define IRQ_HSMMC0 EXYNOS4_IRQ_HSMMC0
-#define IRQ_HSMMC1 EXYNOS4_IRQ_HSMMC1
-#define IRQ_HSMMC2 EXYNOS4_IRQ_HSMMC2
-#define IRQ_HSMMC3 EXYNOS4_IRQ_HSMMC3
-
-#define IRQ_MIPI_CSIS0 EXYNOS4_IRQ_MIPI_CSIS0
-
-#define IRQ_ONENAND_AUDI EXYNOS4_IRQ_ONENAND_AUDI
-
-#define IRQ_FIMC0 EXYNOS4_IRQ_FIMC0
-#define IRQ_FIMC1 EXYNOS4_IRQ_FIMC1
-#define IRQ_FIMC2 EXYNOS4_IRQ_FIMC2
-#define IRQ_FIMC3 EXYNOS4_IRQ_FIMC3
-#define IRQ_JPEG EXYNOS4_IRQ_JPEG
-#define IRQ_2D EXYNOS4_IRQ_2D
-
-#define IRQ_MIXER EXYNOS4_IRQ_MIXER
-#define IRQ_HDMI EXYNOS4_IRQ_HDMI
-#define IRQ_IIC_HDMIPHY EXYNOS4_IRQ_IIC_HDMIPHY
-#define IRQ_MFC EXYNOS4_IRQ_MFC
-#define IRQ_SDO EXYNOS4_IRQ_SDO
-
-#define IRQ_I2S0 EXYNOS4_IRQ_I2S0
-
-#define IRQ_ADC EXYNOS4_IRQ_ADC0
-#define IRQ_TC EXYNOS4_IRQ_PEN0
-
-#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
-
-#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
-#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
-#define IRQ_FIMD0_SYSTEM EXYNOS4_IRQ_FIMD0_SYSTEM
-
-#define IRQ_GPIO1_NR_GROUPS EXYNOS4_IRQ_GPIO1_NR_GROUPS
-#define IRQ_GPIO2_NR_GROUPS EXYNOS4_IRQ_GPIO2_NR_GROUPS
-
-/* For EXYNOS5 SoCs */
-
-#define EXYNOS5_IRQ_MDMA0 IRQ_SPI(33)
-#define EXYNOS5_IRQ_PDMA0 IRQ_SPI(34)
-#define EXYNOS5_IRQ_PDMA1 IRQ_SPI(35)
-#define EXYNOS5_IRQ_TIMER0_VIC IRQ_SPI(36)
-#define EXYNOS5_IRQ_TIMER1_VIC IRQ_SPI(37)
-#define EXYNOS5_IRQ_TIMER2_VIC IRQ_SPI(38)
-#define EXYNOS5_IRQ_TIMER3_VIC IRQ_SPI(39)
-#define EXYNOS5_IRQ_TIMER4_VIC IRQ_SPI(40)
-#define EXYNOS5_IRQ_RTIC IRQ_SPI(41)
-#define EXYNOS5_IRQ_WDT IRQ_SPI(42)
-#define EXYNOS5_IRQ_RTC_ALARM IRQ_SPI(43)
-#define EXYNOS5_IRQ_RTC_TIC IRQ_SPI(44)
-#define EXYNOS5_IRQ_GPIO_XB IRQ_SPI(45)
-#define EXYNOS5_IRQ_GPIO_XA IRQ_SPI(46)
-#define EXYNOS5_IRQ_GPIO IRQ_SPI(47)
-#define EXYNOS5_IRQ_IEM_IEC IRQ_SPI(48)
-#define EXYNOS5_IRQ_IEM_APC IRQ_SPI(49)
-#define EXYNOS5_IRQ_GPIO_C2C IRQ_SPI(50)
-#define EXYNOS5_IRQ_IIC IRQ_SPI(56)
-#define EXYNOS5_IRQ_IIC1 IRQ_SPI(57)
-#define EXYNOS5_IRQ_IIC2 IRQ_SPI(58)
-#define EXYNOS5_IRQ_IIC3 IRQ_SPI(59)
-#define EXYNOS5_IRQ_IIC4 IRQ_SPI(60)
-#define EXYNOS5_IRQ_IIC5 IRQ_SPI(61)
-#define EXYNOS5_IRQ_IIC6 IRQ_SPI(62)
-#define EXYNOS5_IRQ_IIC7 IRQ_SPI(63)
-#define EXYNOS5_IRQ_IIC_HDMIPHY IRQ_SPI(64)
-#define EXYNOS5_IRQ_TMU IRQ_SPI(65)
-#define EXYNOS5_IRQ_FIQ_0 IRQ_SPI(66)
-#define EXYNOS5_IRQ_FIQ_1 IRQ_SPI(67)
-#define EXYNOS5_IRQ_SPI0 IRQ_SPI(68)
-#define EXYNOS5_IRQ_SPI1 IRQ_SPI(69)
-#define EXYNOS5_IRQ_SPI2 IRQ_SPI(70)
-#define EXYNOS5_IRQ_USB_HOST IRQ_SPI(71)
-#define EXYNOS5_IRQ_USB3_DRD IRQ_SPI(72)
-#define EXYNOS5_IRQ_MIPI_HSI IRQ_SPI(73)
-#define EXYNOS5_IRQ_USB_HSOTG IRQ_SPI(74)
-#define EXYNOS5_IRQ_HSMMC0 IRQ_SPI(75)
-#define EXYNOS5_IRQ_HSMMC1 IRQ_SPI(76)
-#define EXYNOS5_IRQ_HSMMC2 IRQ_SPI(77)
-#define EXYNOS5_IRQ_HSMMC3 IRQ_SPI(78)
-#define EXYNOS5_IRQ_MIPICSI0 IRQ_SPI(79)
-#define EXYNOS5_IRQ_MIPICSI1 IRQ_SPI(80)
-#define EXYNOS5_IRQ_EFNFCON_DMA_ABORT IRQ_SPI(81)
-#define EXYNOS5_IRQ_MIPIDSI0 IRQ_SPI(82)
-#define EXYNOS5_IRQ_WDT_IOP IRQ_SPI(83)
-#define EXYNOS5_IRQ_ROTATOR IRQ_SPI(84)
-#define EXYNOS5_IRQ_GSC0 IRQ_SPI(85)
-#define EXYNOS5_IRQ_GSC1 IRQ_SPI(86)
-#define EXYNOS5_IRQ_GSC2 IRQ_SPI(87)
-#define EXYNOS5_IRQ_GSC3 IRQ_SPI(88)
-#define EXYNOS5_IRQ_JPEG IRQ_SPI(89)
-#define EXYNOS5_IRQ_EFNFCON_DMA IRQ_SPI(90)
-#define EXYNOS5_IRQ_2D IRQ_SPI(91)
-#define EXYNOS5_IRQ_EFNFCON_0 IRQ_SPI(92)
-#define EXYNOS5_IRQ_EFNFCON_1 IRQ_SPI(93)
-#define EXYNOS5_IRQ_MIXER IRQ_SPI(94)
-#define EXYNOS5_IRQ_HDMI IRQ_SPI(95)
-#define EXYNOS5_IRQ_MFC IRQ_SPI(96)
-#define EXYNOS5_IRQ_AUDIO_SS IRQ_SPI(97)
-#define EXYNOS5_IRQ_I2S0 IRQ_SPI(98)
-#define EXYNOS5_IRQ_I2S1 IRQ_SPI(99)
-#define EXYNOS5_IRQ_I2S2 IRQ_SPI(100)
-#define EXYNOS5_IRQ_AC97 IRQ_SPI(101)
-#define EXYNOS5_IRQ_PCM0 IRQ_SPI(102)
-#define EXYNOS5_IRQ_PCM1 IRQ_SPI(103)
-#define EXYNOS5_IRQ_PCM2 IRQ_SPI(104)
-#define EXYNOS5_IRQ_SPDIF IRQ_SPI(105)
-#define EXYNOS5_IRQ_ADC0 IRQ_SPI(106)
-#define EXYNOS5_IRQ_ADC1 IRQ_SPI(107)
-#define EXYNOS5_IRQ_SATA_PHY IRQ_SPI(108)
-#define EXYNOS5_IRQ_SATA_PMEMREQ IRQ_SPI(109)
-#define EXYNOS5_IRQ_CAM_C IRQ_SPI(110)
-#define EXYNOS5_IRQ_EAGLE_PMU IRQ_SPI(111)
-#define EXYNOS5_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
-#define EXYNOS5_IRQ_DP1_INTP1 IRQ_SPI(113)
-#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
-#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
-
-#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
-#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
-#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
-#define EXYNOS5_IRQ_FIMC_LITE1 IRQ_SPI(126)
-#define EXYNOS5_IRQ_RP_TIMER IRQ_SPI(127)
-
-/* EXYNOS5440 */
-
-#define EXYNOS5440_IRQ_UART0 IRQ_SPI(2)
-#define EXYNOS5440_IRQ_UART1 IRQ_SPI(3)
-
-#define EXYNOS5_IRQ_PMU COMBINER_IRQ(1, 2)
-
-#define EXYNOS5_IRQ_SYSMMU_GSC0_0 COMBINER_IRQ(2, 0)
-#define EXYNOS5_IRQ_SYSMMU_GSC0_1 COMBINER_IRQ(2, 1)
-#define EXYNOS5_IRQ_SYSMMU_GSC1_0 COMBINER_IRQ(2, 2)
-#define EXYNOS5_IRQ_SYSMMU_GSC1_1 COMBINER_IRQ(2, 3)
-#define EXYNOS5_IRQ_SYSMMU_GSC2_0 COMBINER_IRQ(2, 4)
-#define EXYNOS5_IRQ_SYSMMU_GSC2_1 COMBINER_IRQ(2, 5)
-#define EXYNOS5_IRQ_SYSMMU_GSC3_0 COMBINER_IRQ(2, 6)
-#define EXYNOS5_IRQ_SYSMMU_GSC3_1 COMBINER_IRQ(2, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_LITE2_0 COMBINER_IRQ(3, 0)
-#define EXYNOS5_IRQ_SYSMMU_LITE2_1 COMBINER_IRQ(3, 1)
-#define EXYNOS5_IRQ_SYSMMU_FIMD1_0 COMBINER_IRQ(3, 2)
-#define EXYNOS5_IRQ_SYSMMU_FIMD1_1 COMBINER_IRQ(3, 3)
-#define EXYNOS5_IRQ_SYSMMU_LITE0_0 COMBINER_IRQ(3, 4)
-#define EXYNOS5_IRQ_SYSMMU_LITE0_1 COMBINER_IRQ(3, 5)
-#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_0 COMBINER_IRQ(3, 6)
-#define EXYNOS5_IRQ_SYSMMU_SCALERPISP_1 COMBINER_IRQ(3, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ROTATOR_0 COMBINER_IRQ(4, 0)
-#define EXYNOS5_IRQ_SYSMMU_ROTATOR_1 COMBINER_IRQ(4, 1)
-#define EXYNOS5_IRQ_SYSMMU_JPEG_0 COMBINER_IRQ(4, 2)
-#define EXYNOS5_IRQ_SYSMMU_JPEG_1 COMBINER_IRQ(4, 3)
-
-#define EXYNOS5_IRQ_SYSMMU_FD_0 COMBINER_IRQ(5, 0)
-#define EXYNOS5_IRQ_SYSMMU_FD_1 COMBINER_IRQ(5, 1)
-#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_0 COMBINER_IRQ(5, 2)
-#define EXYNOS5_IRQ_SYSMMU_SCALERCISP_1 COMBINER_IRQ(5, 3)
-#define EXYNOS5_IRQ_SYSMMU_MCUISP_0 COMBINER_IRQ(5, 4)
-#define EXYNOS5_IRQ_SYSMMU_MCUISP_1 COMBINER_IRQ(5, 5)
-#define EXYNOS5_IRQ_SYSMMU_3DNR_0 COMBINER_IRQ(5, 6)
-#define EXYNOS5_IRQ_SYSMMU_3DNR_1 COMBINER_IRQ(5, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ARM_0 COMBINER_IRQ(6, 0)
-#define EXYNOS5_IRQ_SYSMMU_ARM_1 COMBINER_IRQ(6, 1)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_0 COMBINER_IRQ(6, 2)
-#define EXYNOS5_IRQ_SYSMMU_MFC_R_1 COMBINER_IRQ(6, 3)
-#define EXYNOS5_IRQ_SYSMMU_RTIC_0 COMBINER_IRQ(6, 4)
-#define EXYNOS5_IRQ_SYSMMU_RTIC_1 COMBINER_IRQ(6, 5)
-#define EXYNOS5_IRQ_SYSMMU_SSS_0 COMBINER_IRQ(6, 6)
-#define EXYNOS5_IRQ_SYSMMU_SSS_1 COMBINER_IRQ(6, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(7, 0)
-#define EXYNOS5_IRQ_SYSMMU_MDMA0_1 COMBINER_IRQ(7, 1)
-#define EXYNOS5_IRQ_SYSMMU_MDMA1_0 COMBINER_IRQ(7, 2)
-#define EXYNOS5_IRQ_SYSMMU_MDMA1_1 COMBINER_IRQ(7, 3)
-#define EXYNOS5_IRQ_SYSMMU_TV_0 COMBINER_IRQ(7, 4)
-#define EXYNOS5_IRQ_SYSMMU_TV_1 COMBINER_IRQ(7, 5)
-
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_0 COMBINER_IRQ(8, 5)
-#define EXYNOS5_IRQ_SYSMMU_MFC_L_1 COMBINER_IRQ(8, 6)
-
-#define EXYNOS5_IRQ_SYSMMU_DIS1_0 COMBINER_IRQ(9, 4)
-#define EXYNOS5_IRQ_SYSMMU_DIS1_1 COMBINER_IRQ(9, 5)
-
-#define EXYNOS5_IRQ_DP COMBINER_IRQ(10, 3)
-#define EXYNOS5_IRQ_SYSMMU_DIS0_0 COMBINER_IRQ(10, 4)
-#define EXYNOS5_IRQ_SYSMMU_DIS0_1 COMBINER_IRQ(10, 5)
-#define EXYNOS5_IRQ_SYSMMU_ISP_0 COMBINER_IRQ(10, 6)
-#define EXYNOS5_IRQ_SYSMMU_ISP_1 COMBINER_IRQ(10, 7)
-
-#define EXYNOS5_IRQ_SYSMMU_ODC_0 COMBINER_IRQ(11, 0)
-#define EXYNOS5_IRQ_SYSMMU_ODC_1 COMBINER_IRQ(11, 1)
-#define EXYNOS5_IRQ_SYSMMU_DRC_0 COMBINER_IRQ(11, 6)
-#define EXYNOS5_IRQ_SYSMMU_DRC_1 COMBINER_IRQ(11, 7)
-
-#define EXYNOS5_IRQ_MDMA1_ABORT COMBINER_IRQ(13, 1)
-
-#define EXYNOS5_IRQ_MDMA0_ABORT COMBINER_IRQ(15, 3)
-
-#define EXYNOS5_IRQ_FIMD1_FIFO COMBINER_IRQ(18, 4)
-#define EXYNOS5_IRQ_FIMD1_VSYNC COMBINER_IRQ(18, 5)
-#define EXYNOS5_IRQ_FIMD1_SYSTEM COMBINER_IRQ(18, 6)
-
-#define EXYNOS5_IRQ_ARMIOP_GIC COMBINER_IRQ(19, 0)
-#define EXYNOS5_IRQ_ARMISP_GIC COMBINER_IRQ(19, 1)
-#define EXYNOS5_IRQ_IOP_GIC COMBINER_IRQ(19, 3)
-#define EXYNOS5_IRQ_ISP_GIC COMBINER_IRQ(19, 4)
-
-#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
-
-#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
-
-#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
-#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
-#define EXYNOS5_IRQ_SYSMMU_LITE1_1 COMBINER_IRQ(24, 2)
-#define EXYNOS5_IRQ_SYSMMU_2D_0 COMBINER_IRQ(24, 5)
-#define EXYNOS5_IRQ_SYSMMU_2D_1 COMBINER_IRQ(24, 6)
-
-#define EXYNOS5_IRQ_EINT2 COMBINER_IRQ(25, 0)
-#define EXYNOS5_IRQ_EINT3 COMBINER_IRQ(25, 1)
-
-#define EXYNOS5_IRQ_EINT4 COMBINER_IRQ(26, 0)
-#define EXYNOS5_IRQ_EINT5 COMBINER_IRQ(26, 1)
-
-#define EXYNOS5_IRQ_EINT6 COMBINER_IRQ(27, 0)
-#define EXYNOS5_IRQ_EINT7 COMBINER_IRQ(27, 1)
-
-#define EXYNOS5_IRQ_EINT8 COMBINER_IRQ(28, 0)
-#define EXYNOS5_IRQ_EINT9 COMBINER_IRQ(28, 1)
-
-#define EXYNOS5_IRQ_EINT10 COMBINER_IRQ(29, 0)
-#define EXYNOS5_IRQ_EINT11 COMBINER_IRQ(29, 1)
-
-#define EXYNOS5_IRQ_EINT12 COMBINER_IRQ(30, 0)
-#define EXYNOS5_IRQ_EINT13 COMBINER_IRQ(30, 1)
-
-#define EXYNOS5_IRQ_EINT14 COMBINER_IRQ(31, 0)
-#define EXYNOS5_IRQ_EINT15 COMBINER_IRQ(31, 1)
-
-#define EXYNOS5_MAX_COMBINER_NR 32
-
-#define EXYNOS5_IRQ_GPIO1_NR_GROUPS 14
-#define EXYNOS5_IRQ_GPIO2_NR_GROUPS 9
-#define EXYNOS5_IRQ_GPIO3_NR_GROUPS 5
-#define EXYNOS5_IRQ_GPIO4_NR_GROUPS 1
-
-#define MAX_COMBINER_NR (EXYNOS4_MAX_COMBINER_NR > EXYNOS5_MAX_COMBINER_NR ? \
- EXYNOS4_MAX_COMBINER_NR : EXYNOS5_MAX_COMBINER_NR)
-
-#define S5P_EINT_BASE1 COMBINER_IRQ(MAX_COMBINER_NR, 0)
-#define S5P_EINT_BASE2 (S5P_EINT_BASE1 + 16)
-#define S5P_GPIOINT_BASE (S5P_EINT_BASE1 + 32)
-#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
-#define IRQ_TIMER_BASE (IRQ_GPIO_END + 64)
-
-/* Set the default NR_IRQS */
-#define EXYNOS_NR_IRQS (IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
-
-#ifndef CONFIG_SPARSE_IRQ
-#define NR_IRQS EXYNOS_NR_IRQS
-#endif
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 92b29bb583cb..7b046b59d9ec 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -30,31 +30,6 @@
#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
-#define EXYNOS4_PA_FIMC0 0x11800000
-#define EXYNOS4_PA_FIMC1 0x11810000
-#define EXYNOS4_PA_FIMC2 0x11820000
-#define EXYNOS4_PA_FIMC3 0x11830000
-
-#define EXYNOS4_PA_JPEG 0x11840000
-
-/* x = 0...1 */
-#define EXYNOS4_PA_FIMC_LITE(x) (0x12390000 + ((x) * 0x10000))
-
-#define EXYNOS4_PA_G2D 0x12800000
-
-#define EXYNOS4_PA_I2S0 0x03830000
-#define EXYNOS4_PA_I2S1 0xE3100000
-#define EXYNOS4_PA_I2S2 0xE2A00000
-
-#define EXYNOS4_PA_PCM0 0x03840000
-#define EXYNOS4_PA_PCM1 0x13980000
-#define EXYNOS4_PA_PCM2 0x13990000
-
-#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
-
-#define EXYNOS4_PA_ONENAND 0x0C000000
-#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
-
#define EXYNOS_PA_CHIPID 0x10000000
#define EXYNOS4_PA_SYSCON 0x10010000
@@ -71,10 +46,6 @@
#define EXYNOS4_PA_WATCHDOG 0x10060000
#define EXYNOS5_PA_WATCHDOG 0x101D0000
-#define EXYNOS4_PA_RTC 0x10070000
-
-#define EXYNOS4_PA_KEYPAD 0x100A0000
-
#define EXYNOS4_PA_DMC0 0x10400000
#define EXYNOS4_PA_DMC1 0x10410000
@@ -87,207 +58,22 @@
#define EXYNOS5_PA_GIC_DIST 0x10481000
#define EXYNOS4_PA_COREPERI 0x10500000
-#define EXYNOS4_PA_TWD 0x10500600
#define EXYNOS4_PA_L2CC 0x10502000
-#define EXYNOS4_PA_TMU 0x100C0000
-
-#define EXYNOS4_PA_MDMA0 0x10810000
-#define EXYNOS4_PA_MDMA1 0x12850000
-#define EXYNOS4_PA_S_MDMA1 0x12840000
-#define EXYNOS4_PA_PDMA0 0x12680000
-#define EXYNOS4_PA_PDMA1 0x12690000
-#define EXYNOS5_PA_MDMA0 0x10800000
-#define EXYNOS5_PA_MDMA1 0x11C10000
-#define EXYNOS5_PA_PDMA0 0x121A0000
-#define EXYNOS5_PA_PDMA1 0x121B0000
-
-#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
-#define EXYNOS4_PA_SYSMMU_2D_ACP 0x10A40000
-#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
-#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
-#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
-#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
-#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
-#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
-#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
-#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
-#define EXYNOS4_PA_SYSMMU_FIMC_ISP 0x12260000
-#define EXYNOS4_PA_SYSMMU_FIMC_DRC 0x12270000
-#define EXYNOS4_PA_SYSMMU_FIMC_FD 0x122A0000
-#define EXYNOS4_PA_SYSMMU_ISPCPU 0x122B0000
-#define EXYNOS4_PA_SYSMMU_FIMC_LITE0 0x123B0000
-#define EXYNOS4_PA_SYSMMU_FIMC_LITE1 0x123C0000
-#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
-#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
-#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
-#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
-#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
-#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
-#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
-
-#define EXYNOS5_PA_GSC0 0x13E00000
-#define EXYNOS5_PA_GSC1 0x13E10000
-#define EXYNOS5_PA_GSC2 0x13E20000
-#define EXYNOS5_PA_GSC3 0x13E30000
-
-#define EXYNOS5_PA_SYSMMU_MDMA1 0x10A40000
-#define EXYNOS5_PA_SYSMMU_SSS 0x10A50000
-#define EXYNOS5_PA_SYSMMU_2D 0x10A60000
-#define EXYNOS5_PA_SYSMMU_MFC_L 0x11200000
-#define EXYNOS5_PA_SYSMMU_MFC_R 0x11210000
-#define EXYNOS5_PA_SYSMMU_ROTATOR 0x11D40000
-#define EXYNOS5_PA_SYSMMU_MDMA2 0x11D50000
-#define EXYNOS5_PA_SYSMMU_JPEG 0x11F20000
-#define EXYNOS5_PA_SYSMMU_IOP 0x12360000
-#define EXYNOS5_PA_SYSMMU_RTIC 0x12370000
-#define EXYNOS5_PA_SYSMMU_ISP 0x13260000
-#define EXYNOS5_PA_SYSMMU_DRC 0x12370000
-#define EXYNOS5_PA_SYSMMU_SCALERC 0x13280000
-#define EXYNOS5_PA_SYSMMU_SCALERP 0x13290000
-#define EXYNOS5_PA_SYSMMU_FD 0x132A0000
-#define EXYNOS5_PA_SYSMMU_ISPCPU 0x132B0000
-#define EXYNOS5_PA_SYSMMU_ODC 0x132C0000
-#define EXYNOS5_PA_SYSMMU_DIS0 0x132D0000
-#define EXYNOS5_PA_SYSMMU_DIS1 0x132E0000
-#define EXYNOS5_PA_SYSMMU_3DNR 0x132F0000
-#define EXYNOS5_PA_SYSMMU_LITE0 0x13C40000
-#define EXYNOS5_PA_SYSMMU_LITE1 0x13C50000
-#define EXYNOS5_PA_SYSMMU_GSC0 0x13E80000
-#define EXYNOS5_PA_SYSMMU_GSC1 0x13E90000
-#define EXYNOS5_PA_SYSMMU_GSC2 0x13EA0000
-#define EXYNOS5_PA_SYSMMU_GSC3 0x13EB0000
-#define EXYNOS5_PA_SYSMMU_FIMD1 0x14640000
-#define EXYNOS5_PA_SYSMMU_TV 0x14650000
-
-#define EXYNOS4_PA_SPI0 0x13920000
-#define EXYNOS4_PA_SPI1 0x13930000
-#define EXYNOS4_PA_SPI2 0x13940000
-#define EXYNOS5_PA_SPI0 0x12D20000
-#define EXYNOS5_PA_SPI1 0x12D30000
-#define EXYNOS5_PA_SPI2 0x12D40000
-
-#define EXYNOS4_PA_GPIO1 0x11400000
-#define EXYNOS4_PA_GPIO2 0x11000000
-#define EXYNOS4_PA_GPIO3 0x03860000
-#define EXYNOS5_PA_GPIO1 0x11400000
-#define EXYNOS5_PA_GPIO2 0x13400000
-#define EXYNOS5_PA_GPIO3 0x10D10000
-#define EXYNOS5_PA_GPIO4 0x03860000
-
-#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
-#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
-
-#define EXYNOS4_PA_FIMD0 0x11C00000
-
-#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
-#define EXYNOS4_PA_DWMCI 0x12550000
-#define EXYNOS5_PA_DWMCI0 0x12200000
-#define EXYNOS5_PA_DWMCI1 0x12210000
-#define EXYNOS5_PA_DWMCI2 0x12220000
-#define EXYNOS5_PA_DWMCI3 0x12230000
-
-#define EXYNOS4_PA_HSOTG 0x12480000
-#define EXYNOS4_PA_USB_HSPHY 0x125B0000
-
-#define EXYNOS4_PA_SATA 0x12560000
-#define EXYNOS4_PA_SATAPHY 0x125D0000
-#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
-
#define EXYNOS4_PA_SROMC 0x12570000
#define EXYNOS5_PA_SROMC 0x12250000
-#define EXYNOS4_PA_EHCI 0x12580000
-#define EXYNOS4_PA_OHCI 0x12590000
#define EXYNOS4_PA_HSPHY 0x125B0000
-#define EXYNOS4_PA_MFC 0x13400000
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS5_PA_UART 0x12C00000
-#define EXYNOS4_PA_VP 0x12C00000
-#define EXYNOS4_PA_MIXER 0x12C10000
-#define EXYNOS4_PA_SDO 0x12C20000
-#define EXYNOS4_PA_HDMI 0x12D00000
-#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
-
-#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
-#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
-
-#define EXYNOS4_PA_ADC 0x13910000
-#define EXYNOS4_PA_ADC1 0x13911000
-
-#define EXYNOS4_PA_AC97 0x139A0000
-
-#define EXYNOS4_PA_SPDIF 0x139B0000
-
#define EXYNOS4_PA_TIMER 0x139D0000
#define EXYNOS5_PA_TIMER 0x12DD0000
-#define EXYNOS4_PA_SDRAM 0x40000000
-#define EXYNOS5_PA_SDRAM 0x40000000
-
-/* Compatibiltiy Defines */
-
-#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
-#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
-#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
-#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
-#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
-#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
-#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
-#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
-#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
-#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
-#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
-#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
-#define S3C_PA_RTC EXYNOS4_PA_RTC
-#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
-#define S3C_PA_SPI0 EXYNOS4_PA_SPI0
-#define S3C_PA_SPI1 EXYNOS4_PA_SPI1
-#define S3C_PA_SPI2 EXYNOS4_PA_SPI2
-#define S3C_PA_USB_HSOTG EXYNOS4_PA_HSOTG
-
-#define S5P_PA_EHCI EXYNOS4_PA_EHCI
-#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
-#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
-#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
-#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
-#define S5P_PA_JPEG EXYNOS4_PA_JPEG
-#define S5P_PA_G2D EXYNOS4_PA_G2D
-#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
-#define S5P_PA_HDMI EXYNOS4_PA_HDMI
-#define S5P_PA_IIC_HDMIPHY EXYNOS4_PA_IIC_HDMIPHY
-#define S5P_PA_MFC EXYNOS4_PA_MFC
-#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
-#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
-#define S5P_PA_MIXER EXYNOS4_PA_MIXER
-#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
-#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
-#define S5P_PA_SDO EXYNOS4_PA_SDO
-#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
-#define S5P_PA_VP EXYNOS4_PA_VP
-
-#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
-#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
-#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
-
/* Compatibility UART */
-#define EXYNOS4_PA_UART0 0x13800000
-#define EXYNOS4_PA_UART1 0x13810000
-#define EXYNOS4_PA_UART2 0x13820000
-#define EXYNOS4_PA_UART3 0x13830000
-#define EXYNOS4_SZ_UART SZ_256
-
-#define EXYNOS5_PA_UART0 0x12C00000
-#define EXYNOS5_PA_UART1 0x12C10000
-#define EXYNOS5_PA_UART2 0x12C20000
-#define EXYNOS5_PA_UART3 0x12C30000
-
#define EXYNOS5440_PA_UART0 0x000B0000
-#define EXYNOS5440_PA_UART1 0x000C0000
-#define EXYNOS5440_SZ_UART SZ_256
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h
index 296090e7f423..2b00833b6641 100644
--- a/arch/arm/mach-exynos/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos/include/mach/pm-core.h
@@ -34,12 +34,7 @@ static inline void s3c_pm_debug_init_uart(void)
static inline void s3c_pm_arch_prepare_irqs(void)
{
- u32 eintmask = s3c_irqwake_eintmask;
-
- if (of_have_populated_dt())
- eintmask = exynos_get_eint_wake_mask();
-
- __raw_writel(eintmask, S5P_EINT_WAKEUP_MASK);
+ __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
__raw_writel(s3c_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
}
@@ -69,4 +64,9 @@ static inline void samsung_pm_saved_gpios(void)
/* nothing here yet */
}
+/* Compatibility definitions to make plat-samsung/pm.c compile */
+#define IRQ_EINT_BIT(x) 1
+#define s3c_irqwake_intallow 0
+#define s3c_irqwake_eintallow 0
+
#endif /* __ASM_ARCH_PM_CORE_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-gpio.h b/arch/arm/mach-exynos/include/mach/regs-gpio.h
deleted file mode 100644
index e4b5b60dcb85..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 - GPIO (including EINT) register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_GPIO_H
-#define __ASM_ARCH_REGS_GPIO_H __FILE__
-
-#include <mach/map.h>
-#include <mach/irqs.h>
-
-#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
-#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
-#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
-#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
-#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
-
-#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
-
-/* compatibility for plat-s5p/irq-pm.c */
-#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
-#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
-
-#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
-#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
-
-#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
-#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
-
-#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
-#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
-
-#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
deleted file mode 100644
index 07277735252e..000000000000
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (C) 2011 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef __PLAT_S5P_REGS_USB_PHY_H
-#define __PLAT_S5P_REGS_USB_PHY_H
-
-#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY)
-
-#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
-#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
-#define PHY1_HSIC1_SLEEP (1 << 12)
-#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11)
-#define PHY1_HSIC0_SLEEP (1 << 10)
-#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9)
-
-#define PHY1_STD_NORMAL_MASK (0x7 << 6)
-#define PHY1_STD_SLEEP (1 << 8)
-#define PHY1_STD_ANALOG_POWERDOWN (1 << 7)
-#define PHY1_STD_FORCE_SUSPEND (1 << 6)
-
-#define PHY0_NORMAL_MASK (0x39 << 0)
-#define PHY0_SLEEP (1 << 5)
-#define PHY0_OTG_DISABLE (1 << 4)
-#define PHY0_ANALOG_POWERDOWN (1 << 3)
-#define PHY0_FORCE_SUSPEND (1 << 0)
-
-#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04)
-#define PHY1_COMMON_ON_N (1 << 7)
-#define PHY0_COMMON_ON_N (1 << 4)
-#define PHY0_ID_PULLUP (1 << 2)
-
-#define EXYNOS4_CLKSEL_SHIFT (0)
-
-#define EXYNOS4210_CLKSEL_MASK (0x3 << 0)
-#define EXYNOS4210_CLKSEL_48M (0x0 << 0)
-#define EXYNOS4210_CLKSEL_12M (0x2 << 0)
-#define EXYNOS4210_CLKSEL_24M (0x3 << 0)
-
-#define EXYNOS4X12_CLKSEL_MASK (0x7 << 0)
-#define EXYNOS4X12_CLKSEL_9600K (0x0 << 0)
-#define EXYNOS4X12_CLKSEL_10M (0x1 << 0)
-#define EXYNOS4X12_CLKSEL_12M (0x2 << 0)
-#define EXYNOS4X12_CLKSEL_19200K (0x3 << 0)
-#define EXYNOS4X12_CLKSEL_20M (0x4 << 0)
-#define EXYNOS4X12_CLKSEL_24M (0x5 << 0)
-
-#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
-#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
-#define HOST_LINK_PORT2_SWRST (1 << 9)
-#define HOST_LINK_PORT1_SWRST (1 << 8)
-#define HOST_LINK_PORT0_SWRST (1 << 7)
-#define HOST_LINK_ALL_SWRST (1 << 6)
-
-#define PHY1_SWRST_MASK (0x7 << 3)
-#define PHY1_HSIC_SWRST (1 << 5)
-#define PHY1_STD_SWRST (1 << 4)
-#define PHY1_ALL_SWRST (1 << 3)
-
-#define PHY0_SWRST_MASK (0x7 << 0)
-#define PHY0_PHYLINK_SWRST (1 << 2)
-#define PHY0_HLINK_SWRST (1 << 1)
-#define PHY0_SWRST (1 << 0)
-
-#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
-#define FPENABLEN (1 << 0)
-
-#endif /* __PLAT_S5P_REGS_USB_PHY_H */