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authorRussell King <rmk+kernel@arm.linux.org.uk>2012-01-05 13:25:15 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-01-05 13:25:27 +0000
commit7b9dd47136c07ffd883aff6926c7b281e4c1eea4 (patch)
treeb835312e76fe323de3e1cbbb0d15fca5a3f7ef9c /arch/arm/mach-footbridge/common.c
parent2e0e943436912ffe0848ece58167edfe754edb96 (diff)
parent0575fb754dbfc32a01f297e778533340a533ec68 (diff)
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Merge branch 'restart' into for-linus
Conflicts: arch/arm/mach-exynos/cpu.c The changes to arch/arm/mach-exynos/cpu.c were moved to mach-exynos/common.c.
Diffstat (limited to 'arch/arm/mach-footbridge/common.c')
-rw-r--r--arch/arm/mach-footbridge/common.c27
1 files changed, 27 insertions, 0 deletions
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 38a44f9b9da2..41978ee4f9d0 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -199,6 +199,33 @@ void __init footbridge_map_io(void)
iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
}
+void footbridge_restart(char mode, const char *cmd)
+{
+ if (mode == 's') {
+ /* Jump into the ROM */
+ soft_restart(0x41000000);
+ } else {
+ /*
+ * Force the watchdog to do a CPU reset.
+ *
+ * After making sure that the watchdog is disabled
+ * (so we can change the timer registers) we first
+ * enable the timer to autoreload itself. Next, the
+ * timer interval is set really short and any
+ * current interrupt request is cleared (so we can
+ * see an edge transition). Finally, TIMER4 is
+ * enabled as the watchdog.
+ */
+ *CSR_SA110_CNTL &= ~(1 << 13);
+ *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
+ TIMER_CNTL_AUTORELOAD |
+ TIMER_CNTL_DIV16;
+ *CSR_TIMER4_LOAD = 0x2;
+ *CSR_TIMER4_CLR = 0;
+ *CSR_SA110_CNTL |= (1 << 13);
+ }
+}
+
#ifdef CONFIG_FOOTBRIDGE_ADDIN
static inline unsigned long fb_bus_sdram_offset(void)