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| author | Roland Stigge <stigge@antcom.de> | 2012-11-07 13:30:50 +0100 |
|---|---|---|
| committer | Roland Stigge <stigge@antcom.de> | 2012-11-07 13:30:50 +0100 |
| commit | e40ec953b6ac21257760730af8c36e2695e4beac (patch) | |
| tree | 50eb73d7f58fd046455901894b3e620c0ed4d7b4 /arch/arm/mach-lpc32xx | |
| parent | 2998b1d3b1ee31e1c21085383226be1b0c496eab (diff) | |
| download | linux-e40ec953b6ac21257760730af8c36e2695e4beac.tar.gz linux-e40ec953b6ac21257760730af8c36e2695e4beac.tar.bz2 linux-e40ec953b6ac21257760730af8c36e2695e4beac.zip | |
ARM: LPC32xx: Relocate calls to irq_set_chained_handler()
This patch fixes the issue of an access to a yet uninitialized data structure
at the point where irq_set_chained_handler() was called by moving the
respective calls to the end of lpc32xx_init_irq().
The call path was:
irq_set_chained_handler()
-> __irq_set_handler()
-> irq_startup()
-> irq_enable()
-> desc->irq_data.chip->irq_unmask()
at which point lpc32xx_unmask_irq() effectively read desc->irq_data.hwirq which
was only later initialized.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Diffstat (limited to 'arch/arm/mach-lpc32xx')
| -rw-r--r-- | arch/arm/mach-lpc32xx/irq.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c index 54c68b12bae0..f06229687026 100644 --- a/arch/arm/mach-lpc32xx/irq.c +++ b/arch/arm/mach-lpc32xx/irq.c @@ -447,10 +447,6 @@ void __init lpc32xx_init_irq(void) __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE)); __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); - /* MIC SUBIRQx interrupts will route handling to the chain handlers */ - irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); - irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); - /* Initially disable all wake events */ __raw_writel(0, LPC32XX_CLKPWR_P01_ER); __raw_writel(0, LPC32XX_CLKPWR_INT_ER); @@ -479,4 +475,8 @@ void __init lpc32xx_init_irq(void) NULL); if (!lpc32xx_mic_domain) panic("Unable to add MIC irq domain\n"); + + /* MIC SUBIRQx interrupts will route handling to the chain handlers */ + irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); + irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); } |