Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (65 commits)
  ARM: 6826/1: Merge v6 and v7 DEBUG_LL DCC support
  ARM: 6838/1: etm: fix section mismatch warning
  ARM: 6837/1: remove unused pci_fixup_prpmc1100
  ARM: 6836/1: kprobes/fix emulation of LDR/STR instruction when Rn == PC
  Fix the broken build for Marvell Dove platform.
  ARM: 6835/1: perf: ensure overflows aren't missed due to IRQ latency
  ARM: 6834/1: perf: reset counters on all CPUs during initialisation
  ARM: 6833/1: perf: add required isbs() to ARMv7 backend
  ARM: 6825/1: kernel/sleep.S: fix Thumb2 compilation issues
  ARM: 6807/1: realview: Fix secondary GIC initialisation for EB with MPCore tile
  arm: mach-mx3: pcm043: add write-protect and card-detect for SD1
  eukrea_mbimxsd51: add SD Card detect
  eukrea_mbimxsd25-baseboard: add SD card detect
  mx3/eukrea_mbimxsd-baseboard: add SD card detect support
  mx3/eukrea_mbimxsd-baseboard: fix gpio request
  ARM: mxs/mx28evk: add mmc device
  ARM: mxs/mx23evk: add mmc device
  ARM: mxs: dynamically allocate mmc device
  ARM: mx51_efika: update platform data for new mfd changes
  mx2/iomux: Set direction for CSPI2 pins
  ...

1 files changed, 59 insertions, 0 deletions

diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index df46b5e60857..472bdfab2e55 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -21,6 +21,7 @@
 static int cpu_silicon_rev = -1;
 
 #define IIM_SREV 0x24
+#define MX50_HW_ADADIG_DIGPROG	0xB0
 
 static int get_mx51_srev(void)
 {
@@ -51,6 +52,26 @@ int mx51_revision(void)
 }
 EXPORT_SYMBOL(mx51_revision);
 
+void mx51_display_revision(void)
+{
+	int rev;
+	char *srev;
+	rev = mx51_revision();
+
+	switch (rev) {
+	case IMX_CHIP_REVISION_2_0:
+		srev = IMX_CHIP_REVISION_2_0_STRING;
+		break;
+	case IMX_CHIP_REVISION_3_0:
+		srev = IMX_CHIP_REVISION_3_0_STRING;
+		break;
+	default:
+		srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
+	}
+	printk(KERN_INFO "CPU identified as i.MX51, silicon rev %s\n", srev);
+}
+EXPORT_SYMBOL(mx51_display_revision);
+
 #ifdef CONFIG_NEON
 
 /*
@@ -107,6 +128,44 @@ int mx53_revision(void)
 }
 EXPORT_SYMBOL(mx53_revision);
 
+static int get_mx50_srev(void)
+{
+	void __iomem *anatop = ioremap(MX50_ANATOP_BASE_ADDR, SZ_8K);
+	u32 rev;
+
+	if (!anatop) {
+		cpu_silicon_rev = -EINVAL;
+		return 0;
+	}
+
+	rev = readl(anatop + MX50_HW_ADADIG_DIGPROG);
+	rev &= 0xff;
+
+	iounmap(anatop);
+	if (rev == 0x0)
+		return IMX_CHIP_REVISION_1_0;
+	else if (rev == 0x1)
+		return IMX_CHIP_REVISION_1_1;
+	return 0;
+}
+
+/*
+ * Returns:
+ *	the silicon revision of the cpu
+ *	-EINVAL - not a mx50
+ */
+int mx50_revision(void)
+{
+	if (!cpu_is_mx50())
+		return -EINVAL;
+
+	if (cpu_silicon_rev == -1)
+		cpu_silicon_rev = get_mx50_srev();
+
+	return cpu_silicon_rev;
+}
+EXPORT_SYMBOL(mx50_revision);
+
 static int __init post_cpu_init(void)
 {
 	unsigned int reg;