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| author | Heiko Stuebner <heiko@sntech.de> | 2012-04-24 18:07:10 -0700 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-04-24 18:07:10 -0700 |
| commit | f03eb25e223cf1fc9e807a479b776e8e2f1cc9e1 (patch) | |
| tree | db2a10c2eeb2005e3f3ffdeac3a9f0418ecf658d /arch/arm/mach-s3c24xx/setup-spi.c | |
| parent | 5c2f2917168e7a36c0fda0e7c2b0246c83eb7fe0 (diff) | |
| download | linux-f03eb25e223cf1fc9e807a479b776e8e2f1cc9e1.tar.gz linux-f03eb25e223cf1fc9e807a479b776e8e2f1cc9e1.tar.bz2 linux-f03eb25e223cf1fc9e807a479b776e8e2f1cc9e1.zip | |
ARM: S3C24XX: Add HSSPI setup callback for s3c64xx-spi driver
This lets the s3c64xx-spi driver know the specifics of the controller-
variant and also setups the gpios and the misccr bit.
This setup is valid for all S3C24XX SoCs containing a HSSPI controller
(i.e. S3C2416/2450 and S3C2443)
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm/mach-s3c24xx/setup-spi.c')
| -rw-r--r-- | arch/arm/mach-s3c24xx/setup-spi.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c new file mode 100644 index 000000000000..5712c85f39b1 --- /dev/null +++ b/arch/arm/mach-s3c24xx/setup-spi.c @@ -0,0 +1,39 @@ +/* + * HS-SPI device setup for S3C2443/S3C2416 + * + * Copyright (C) 2011 Samsung Electronics Ltd. + * http://www.samsung.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/gpio.h> +#include <linux/platform_device.h> + +#include <plat/gpio-cfg.h> +#include <plat/s3c64xx-spi.h> + +#include <mach/hardware.h> +#include <mach/regs-gpio.h> + +#ifdef CONFIG_S3C64XX_DEV_SPI0 +struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = { + .fifo_lvl_mask = 0x7f, + .rx_lvl_offset = 13, + .tx_st_done = 21, + .high_speed = 1, +}; + +int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev) +{ + /* enable hsspi bit in misccr */ + s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1); + + s3c_gpio_cfgall_range(S3C2410_GPE(11), 3, + S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); + + return 0; +} +#endif |