diff options
| author | Jens Axboe <jens.axboe@oracle.com> | 2010-03-19 08:05:10 +0100 |
|---|---|---|
| committer | Jens Axboe <jens.axboe@oracle.com> | 2010-03-19 08:05:10 +0100 |
| commit | b4b7a4ef097f288f724420b473dbf92a89c0ab7e (patch) | |
| tree | 23ad8101e3e77c32a8d1e1b95a9c1cd7f7a475b7 /arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h | |
| parent | e9ce335df51ff782035a15c261a3c0c9892a1767 (diff) | |
| parent | a3d3203e4bb40f253b1541e310dc0f9305be7c84 (diff) | |
| download | linux-b4b7a4ef097f288f724420b473dbf92a89c0ab7e.tar.gz linux-b4b7a4ef097f288f724420b473dbf92a89c0ab7e.tar.bz2 linux-b4b7a4ef097f288f724420b473dbf92a89c0ab7e.zip | |
Merge branch 'master' into for-linus
Conflicts:
block/Kconfig
Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
Diffstat (limited to 'arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h')
| -rw-r--r-- | arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h new file mode 100644 index 000000000000..f057adb627dd --- /dev/null +++ b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h @@ -0,0 +1,44 @@ +/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h + * + * Copyright 2008 Openmoko, Inc. + * Copyright 2008 Simtec Electronics + * Ben Dooks <ben@simtec.co.uk> + * http://armlinux.simtec.co.uk/ + * + * GPIO Bank E register and configuration definitions + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00) +#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04) +#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08) +#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c) +#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10) + +#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4)) +#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4)) +#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) + +#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0) +#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0) +#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0) + +#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4) +#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4) +#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4) + +#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8) +#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8) +#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8) + +#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12) +#define S3C64XX_GPE3_I2S1_DI (0x03 << 12) +#define S3C64XX_GPE3_AC97_SDI (0x04 << 12) + +#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16) +#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16) +#define S3C64XX_GPE4_AC97_SDO (0x04 << 16) + |