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| author | Dmitry Osipenko <digetx@gmail.com> | 2014-10-10 17:24:47 +0400 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2014-11-17 11:43:21 +0100 |
| commit | e4a680099a6e97ecdbb81081cff9e4a489a4dc44 (patch) | |
| tree | 5479bb4266407c3fdc5a73257643f561bb017897 /arch/arm/mach-tegra | |
| parent | f114040e3ea6e07372334ade75d1ee0775c355e1 (diff) | |
| download | linux-e4a680099a6e97ecdbb81081cff9e4a489a4dc44.tar.gz linux-e4a680099a6e97ecdbb81081cff9e4a489a4dc44.tar.bz2 linux-e4a680099a6e97ecdbb81081cff9e4a489a4dc44.zip | |
ARM: tegra: Re-add removed SoC id macro to tegra_resume()
Commit d127e9c ("ARM: tegra: make tegra_resume can work with current and later
chips") removed tegra_get_soc_id macro leaving used cpu register corrupted after
branching to v7_invalidate_l1() and as result causing execution of unintended
code on tegra20. Possibly it was expected that r6 would be SoC id func argument
since common cpu reset handler is setting r6 before branching to tegra_resume(),
but neither tegra20_lp1_reset() nor tegra30_lp1_reset() aren't setting r6
register before jumping to resume function. Fix it by re-adding macro.
Fixes: d127e9c (ARM: tegra: make tegra_resume can work with current and later chips)
Cc: <stable@vger.kernel.org> # v3.13+
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra')
| -rw-r--r-- | arch/arm/mach-tegra/reset-handler.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 7b2baab0f0bd..71be4af5e975 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -51,6 +51,7 @@ ENTRY(tegra_resume) THUMB( it ne ) bne cpu_resume @ no + tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 /* Are we on Tegra20? */ cmp r6, #TEGRA20 beq 1f @ Yes |