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authorFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2012-03-06 08:09:16 +0000
committerFlorian Tobias Schandinat <FlorianSchandinat@gmx.de>2012-03-06 08:09:16 +0000
commitd282e4d9353b9e7971713aa9e78da716e4a1262d (patch)
tree123aa2391841f37f4b8ae80c02eda4094e17994a /arch/arm/mm
parent2c0fad8e907abf059b21bdb24d183dcbf8d14c10 (diff)
parent192cfd58774b4d17b2fe8bdc77d89c2ef4e0591d (diff)
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Merge commit 'v3.3-rc6' into fbdev-next
Diffstat (limited to 'arch/arm/mm')
-rw-r--r--arch/arm/mm/Kconfig3
-rw-r--r--arch/arm/mm/cache-v7.S2
2 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 1a3ca2488164..7edef9121632 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -631,7 +631,8 @@ comment "Processor Features"
config ARM_LPAE
bool "Support for the Large Physical Address Extension"
- depends on MMU && CPU_V7
+ depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
+ !CPU_32v4 && !CPU_32v3
help
Say Y if you have an ARMv7 processor supporting the LPAE page
table format and you would like to access memory beyond the
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 7a24d39661f0..a655d3da386d 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -55,7 +55,7 @@ loop1:
cmp r1, #2 @ see what cache we have at this level
blt skip @ skip if no cache, or just i-cache
#ifdef CONFIG_PREEMPT
- save_and_disable_irqs r9 @ make cssr&csidr read atomic
+ save_and_disable_irqs_notrace r9 @ make cssr&csidr read atomic
#endif
mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
isb @ isb to sych the new cssr&csidr